UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmiCr3" with PatchInstructionX86()
[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / SmramSaveState.c
CommitLineData
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1/** @file\r
2Provides services to access SMRAM Save State Map\r
3\r
8491e302 4Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>\r
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5This program and the accompanying materials\r
6are licensed and made available under the terms and conditions of the BSD License\r
7which accompanies this distribution. The full text of the license may be found at\r
8http://opensource.org/licenses/bsd-license.php\r
9\r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include <PiSmm.h>\r
16\r
17#include <Library/SmmCpuFeaturesLib.h>\r
18\r
19#include <Library/BaseLib.h>\r
20#include <Library/BaseMemoryLib.h>\r
21#include <Library/SmmServicesTableLib.h>\r
22#include <Library/DebugLib.h>\r
23#include <Register/Cpuid.h>\r
24#include <Register/SmramSaveStateMap.h>\r
25\r
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26#include "PiSmmCpuDxeSmm.h"\r
27\r
28typedef struct {\r
29 UINT64 Signature; // Offset 0x00\r
30 UINT16 Reserved1; // Offset 0x08\r
31 UINT16 Reserved2; // Offset 0x0A\r
32 UINT16 Reserved3; // Offset 0x0C\r
33 UINT16 SmmCs; // Offset 0x0E\r
34 UINT16 SmmDs; // Offset 0x10\r
35 UINT16 SmmSs; // Offset 0x12\r
36 UINT16 SmmOtherSegment; // Offset 0x14\r
37 UINT16 Reserved4; // Offset 0x16\r
38 UINT64 Reserved5; // Offset 0x18\r
39 UINT64 Reserved6; // Offset 0x20\r
40 UINT64 Reserved7; // Offset 0x28\r
41 UINT64 SmmGdtPtr; // Offset 0x30\r
42 UINT32 SmmGdtSize; // Offset 0x38\r
43 UINT32 Reserved8; // Offset 0x3C\r
44 UINT64 Reserved9; // Offset 0x40\r
45 UINT64 Reserved10; // Offset 0x48\r
46 UINT16 Reserved11; // Offset 0x50\r
47 UINT16 Reserved12; // Offset 0x52\r
48 UINT32 Reserved13; // Offset 0x54\r
49 UINT64 Reserved14; // Offset 0x58\r
50} PROCESSOR_SMM_DESCRIPTOR;\r
51\r
52extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;\r
53\r
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54//\r
55// EFER register LMA bit\r
56//\r
57#define LMA BIT10\r
58\r
59///\r
60/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
61///\r
62#define SMM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)\r
63\r
64///\r
65/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE\r
66///\r
67#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }\r
68\r
69///\r
70/// Structure used to describe a range of registers\r
71///\r
72typedef struct {\r
73 EFI_SMM_SAVE_STATE_REGISTER Start;\r
74 EFI_SMM_SAVE_STATE_REGISTER End;\r
75 UINTN Length;\r
76} CPU_SMM_SAVE_STATE_REGISTER_RANGE;\r
77\r
78///\r
79/// Structure used to build a lookup table to retrieve the widths and offsets\r
80/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value\r
81///\r
82\r
83#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1\r
84#define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX 2\r
85#define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX 3\r
86#define SMM_SAVE_STATE_REGISTER_MAX_INDEX 4\r
87\r
88typedef struct {\r
89 UINT8 Width32;\r
90 UINT8 Width64;\r
91 UINT16 Offset32;\r
92 UINT16 Offset64Lo;\r
93 UINT16 Offset64Hi;\r
94 BOOLEAN Writeable;\r
95} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;\r
96\r
97///\r
98/// Structure used to build a lookup table for the IOMisc width information\r
99///\r
100typedef struct {\r
101 UINT8 Width;\r
102 EFI_SMM_SAVE_STATE_IO_WIDTH IoWidth;\r
103} CPU_SMM_SAVE_STATE_IO_WIDTH;\r
104\r
105///\r
106/// Variables from SMI Handler\r
107///\r
5a1bfda4 108X86_ASSEMBLY_PATCH_LABEL gPatchSmbase;\r
fc504fde 109X86_ASSEMBLY_PATCH_LABEL gPatchSmiStack;\r
c455687f 110X86_ASSEMBLY_PATCH_LABEL gPatchSmiCr3;\r
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111extern volatile UINT8 gcSmiHandlerTemplate[];\r
112extern CONST UINT16 gcSmiHandlerSize;\r
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113\r
114//\r
115// Variables used by SMI Handler\r
116//\r
117IA32_DESCRIPTOR gSmiHandlerIdtr;\r
118\r
119///\r
120/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER\r
121/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
122///\r
123CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {\r
124 SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO),\r
125 SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP),\r
126 SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4),\r
127 { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }\r
128};\r
129\r
130///\r
131/// Lookup table used to retrieve the widths and offsets associated with each\r
132/// supported EFI_SMM_SAVE_STATE_REGISTER value\r
133///\r
134CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {\r
135 {0, 0, 0, 0, 0, FALSE}, // Reserved\r
136\r
137 //\r
138 // Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol.\r
139 //\r
140 {4, 4, SMM_CPU_OFFSET (x86.SMMRevId) , SMM_CPU_OFFSET (x64.SMMRevId) , 0 , FALSE}, // SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX = 1\r
141 {4, 4, SMM_CPU_OFFSET (x86.IOMisc) , SMM_CPU_OFFSET (x64.IOMisc) , 0 , FALSE}, // SMM_SAVE_STATE_REGISTER_IOMISC_INDEX = 2\r
142 {4, 8, SMM_CPU_OFFSET (x86.IOMemAddr) , SMM_CPU_OFFSET (x64.IOMemAddr) , SMM_CPU_OFFSET (x64.IOMemAddr) + 4, FALSE}, // SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX = 3\r
143\r
144 //\r
145 // CPU Save State registers defined in PI SMM CPU Protocol.\r
146 //\r
147 {0, 8, 0 , SMM_CPU_OFFSET (x64.GdtBaseLoDword) , SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4\r
148 {0, 8, 0 , SMM_CPU_OFFSET (x64.IdtBaseLoDword) , SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5\r
149 {0, 8, 0 , SMM_CPU_OFFSET (x64.LdtBaseLoDword) , SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6\r
150 {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7\r
151 {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8\r
152 {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9\r
153 {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10\r
154\r
155 {4, 4, SMM_CPU_OFFSET (x86._ES) , SMM_CPU_OFFSET (x64._ES) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20\r
156 {4, 4, SMM_CPU_OFFSET (x86._CS) , SMM_CPU_OFFSET (x64._CS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21\r
157 {4, 4, SMM_CPU_OFFSET (x86._SS) , SMM_CPU_OFFSET (x64._SS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22\r
158 {4, 4, SMM_CPU_OFFSET (x86._DS) , SMM_CPU_OFFSET (x64._DS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23\r
159 {4, 4, SMM_CPU_OFFSET (x86._FS) , SMM_CPU_OFFSET (x64._FS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24\r
160 {4, 4, SMM_CPU_OFFSET (x86._GS) , SMM_CPU_OFFSET (x64._GS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25\r
161 {0, 4, 0 , SMM_CPU_OFFSET (x64._LDTR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26\r
162 {4, 4, SMM_CPU_OFFSET (x86._TR) , SMM_CPU_OFFSET (x64._TR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27\r
163 {4, 8, SMM_CPU_OFFSET (x86._DR7) , SMM_CPU_OFFSET (x64._DR7) , SMM_CPU_OFFSET (x64._DR7) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28\r
164 {4, 8, SMM_CPU_OFFSET (x86._DR6) , SMM_CPU_OFFSET (x64._DR6) , SMM_CPU_OFFSET (x64._DR6) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29\r
165 {0, 8, 0 , SMM_CPU_OFFSET (x64._R8) , SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30\r
166 {0, 8, 0 , SMM_CPU_OFFSET (x64._R9) , SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31\r
167 {0, 8, 0 , SMM_CPU_OFFSET (x64._R10) , SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32\r
168 {0, 8, 0 , SMM_CPU_OFFSET (x64._R11) , SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33\r
169 {0, 8, 0 , SMM_CPU_OFFSET (x64._R12) , SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34\r
170 {0, 8, 0 , SMM_CPU_OFFSET (x64._R13) , SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35\r
171 {0, 8, 0 , SMM_CPU_OFFSET (x64._R14) , SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36\r
172 {0, 8, 0 , SMM_CPU_OFFSET (x64._R15) , SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37\r
173 {4, 8, SMM_CPU_OFFSET (x86._EAX) , SMM_CPU_OFFSET (x64._RAX) , SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38\r
174 {4, 8, SMM_CPU_OFFSET (x86._EBX) , SMM_CPU_OFFSET (x64._RBX) , SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39\r
175 {4, 8, SMM_CPU_OFFSET (x86._ECX) , SMM_CPU_OFFSET (x64._RCX) , SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40\r
176 {4, 8, SMM_CPU_OFFSET (x86._EDX) , SMM_CPU_OFFSET (x64._RDX) , SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41\r
177 {4, 8, SMM_CPU_OFFSET (x86._ESP) , SMM_CPU_OFFSET (x64._RSP) , SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42\r
178 {4, 8, SMM_CPU_OFFSET (x86._EBP) , SMM_CPU_OFFSET (x64._RBP) , SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43\r
179 {4, 8, SMM_CPU_OFFSET (x86._ESI) , SMM_CPU_OFFSET (x64._RSI) , SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44\r
180 {4, 8, SMM_CPU_OFFSET (x86._EDI) , SMM_CPU_OFFSET (x64._RDI) , SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45\r
181 {4, 8, SMM_CPU_OFFSET (x86._EIP) , SMM_CPU_OFFSET (x64._RIP) , SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46\r
182\r
183 {4, 8, SMM_CPU_OFFSET (x86._EFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51\r
184 {4, 8, SMM_CPU_OFFSET (x86._CR0) , SMM_CPU_OFFSET (x64._CR0) , SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52\r
185 {4, 8, SMM_CPU_OFFSET (x86._CR3) , SMM_CPU_OFFSET (x64._CR3) , SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53\r
186 {0, 4, 0 , SMM_CPU_OFFSET (x64._CR4) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54\r
187};\r
188\r
189///\r
190/// Lookup table for the IOMisc width information\r
191///\r
192CONST CPU_SMM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] = {\r
193 { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 0\r
194 { 1, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // SMM_IO_LENGTH_BYTE = 1\r
195 { 2, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 }, // SMM_IO_LENGTH_WORD = 2\r
196 { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 3\r
197 { 4, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 }, // SMM_IO_LENGTH_DWORD = 4\r
198 { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 5\r
199 { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 6\r
200 { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 } // Undefined = 7\r
201};\r
202\r
203///\r
204/// Lookup table for the IOMisc type information\r
205///\r
206CONST EFI_SMM_SAVE_STATE_IO_TYPE mSmmCpuIoType[] = {\r
207 EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_DX = 0\r
208 EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_IN_DX = 1\r
209 EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_OUTS = 2\r
210 EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_INS = 3\r
211 (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 4\r
212 (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 5\r
213 EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_OUTS = 6\r
214 EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_INS = 7\r
215 EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_IMMEDIATE = 8\r
216 EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_OUT_IMMEDIATE = 9\r
217 (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 10\r
218 (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 11\r
219 (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 12\r
220 (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 13\r
221 (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 14\r
222 (EFI_SMM_SAVE_STATE_IO_TYPE)0 // Undefined = 15\r
223};\r
224\r
225///\r
226/// The mode of the CPU at the time an SMI occurs\r
227///\r
228UINT8 mSmmSaveStateRegisterLma;\r
229\r
230/**\r
231 Read information from the CPU save state.\r
232\r
233 @param Register Specifies the CPU register to read form the save state.\r
234\r
235 @retval 0 Register is not valid\r
236 @retval >0 Index into mSmmCpuWidthOffset[] associated with Register\r
237\r
238**/\r
239UINTN\r
240GetRegisterIndex (\r
241 IN EFI_SMM_SAVE_STATE_REGISTER Register\r
242 )\r
243{\r
244 UINTN Index;\r
245 UINTN Offset;\r
246\r
247 for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_MAX_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) {\r
248 if (Register >= mSmmCpuRegisterRanges[Index].Start && Register <= mSmmCpuRegisterRanges[Index].End) {\r
249 return Register - mSmmCpuRegisterRanges[Index].Start + Offset;\r
250 }\r
251 Offset += mSmmCpuRegisterRanges[Index].Length;\r
252 }\r
253 return 0;\r
254}\r
255\r
256/**\r
257 Read a CPU Save State register on the target processor.\r
258\r
259 This function abstracts the differences that whether the CPU Save State register is in the\r
260 IA32 CPU Save State Map or X64 CPU Save State Map.\r
261\r
262 This function supports reading a CPU Save State register in SMBase relocation handler.\r
263\r
264 @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
265 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
266 @param[in] Width The number of bytes to read from the CPU save state.\r
267 @param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r
268\r
269 @retval EFI_SUCCESS The register was read from Save State.\r
270 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
271 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
272\r
273**/\r
274EFI_STATUS\r
275ReadSaveStateRegisterByIndex (\r
276 IN UINTN CpuIndex,\r
277 IN UINTN RegisterIndex,\r
278 IN UINTN Width,\r
279 OUT VOID *Buffer\r
280 )\r
281{\r
282 SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
283\r
284 if (RegisterIndex == 0) {\r
285 return EFI_NOT_FOUND;\r
286 }\r
287\r
288 CpuSaveState = gSmst->CpuSaveState[CpuIndex];\r
289\r
290 if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {\r
291 //\r
292 // If 32-bit mode width is zero, then the specified register can not be accessed\r
293 //\r
294 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r
295 return EFI_NOT_FOUND;\r
296 }\r
297\r
298 //\r
299 // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed\r
300 //\r
301 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r
302 return EFI_INVALID_PARAMETER;\r
303 }\r
304\r
305 //\r
306 // Write return buffer\r
307 //\r
308 ASSERT(CpuSaveState != NULL);\r
309 CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);\r
310 } else {\r
311 //\r
312 // If 64-bit mode width is zero, then the specified register can not be accessed\r
313 //\r
314 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r
315 return EFI_NOT_FOUND;\r
316 }\r
317\r
318 //\r
319 // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed\r
320 //\r
321 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r
322 return EFI_INVALID_PARAMETER;\r
323 }\r
324\r
325 //\r
326 // Write lower 32-bits of return buffer\r
327 //\r
328 CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN(4, Width));\r
329 if (Width >= 4) {\r
330 //\r
331 // Write upper 32-bits of return buffer\r
332 //\r
333 CopyMem((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);\r
334 }\r
335 }\r
336 return EFI_SUCCESS;\r
337}\r
338\r
339/**\r
340 Read a CPU Save State register on the target processor.\r
341\r
342 This function abstracts the differences that whether the CPU Save State register is in the\r
343 IA32 CPU Save State Map or X64 CPU Save State Map.\r
344\r
345 This function supports reading a CPU Save State register in SMBase relocation handler.\r
346\r
347 @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
348 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
349 @param[in] Width The number of bytes to read from the CPU save state.\r
350 @param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r
351\r
352 @retval EFI_SUCCESS The register was read from Save State.\r
353 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
354 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
355\r
356**/\r
357EFI_STATUS\r
358EFIAPI\r
359ReadSaveStateRegister (\r
360 IN UINTN CpuIndex,\r
361 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
362 IN UINTN Width,\r
363 OUT VOID *Buffer\r
364 )\r
365{\r
366 UINT32 SmmRevId;\r
367 SMRAM_SAVE_STATE_IOMISC IoMisc;\r
368 EFI_SMM_SAVE_STATE_IO_INFO *IoInfo;\r
369 VOID *IoMemAddr;\r
370\r
371 //\r
372 // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA\r
373 //\r
374 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {\r
375 //\r
376 // Only byte access is supported for this register\r
377 //\r
378 if (Width != 1) {\r
379 return EFI_INVALID_PARAMETER;\r
380 }\r
381\r
382 *(UINT8 *)Buffer = mSmmSaveStateRegisterLma;\r
383\r
384 return EFI_SUCCESS;\r
385 }\r
386\r
387 //\r
388 // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO\r
389 //\r
390 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {\r
391 //\r
392 // Get SMM Revision ID\r
393 //\r
394 ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof(SmmRevId), &SmmRevId);\r
395\r
396 //\r
397 // See if the CPU supports the IOMisc register in the save state\r
398 //\r
399 if (SmmRevId < SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC) {\r
400 return EFI_NOT_FOUND;\r
401 }\r
402\r
403 //\r
404 // Get the IOMisc register value\r
405 //\r
406 ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_IOMISC_INDEX, sizeof(IoMisc.Uint32), &IoMisc.Uint32);\r
407\r
408 //\r
409 // Check for the SMI_FLAG in IOMisc\r
410 //\r
411 if (IoMisc.Bits.SmiFlag == 0) {\r
412 return EFI_NOT_FOUND;\r
413 }\r
414\r
415 //\r
416 // Compute index for the I/O Length and I/O Type lookup tables\r
417 //\r
418 if (mSmmCpuIoWidth[IoMisc.Bits.Length].Width == 0 || mSmmCpuIoType[IoMisc.Bits.Type] == 0) {\r
419 return EFI_NOT_FOUND;\r
420 }\r
421\r
422 //\r
423 // Zero the IoInfo structure that will be returned in Buffer\r
424 //\r
425 IoInfo = (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer;\r
426 ZeroMem (IoInfo, sizeof(EFI_SMM_SAVE_STATE_IO_INFO));\r
427\r
428 //\r
429 // Use lookup tables to help fill in all the fields of the IoInfo structure\r
430 //\r
431 IoInfo->IoPort = (UINT16)IoMisc.Bits.Port;\r
432 IoInfo->IoWidth = mSmmCpuIoWidth[IoMisc.Bits.Length].IoWidth;\r
433 IoInfo->IoType = mSmmCpuIoType[IoMisc.Bits.Type];\r
434 if (IoInfo->IoType == EFI_SMM_SAVE_STATE_IO_TYPE_INPUT || IoInfo->IoType == EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT) {\r
435 ReadSaveStateRegister (CpuIndex, EFI_SMM_SAVE_STATE_REGISTER_RAX, mSmmCpuIoWidth[IoMisc.Bits.Length].Width, &IoInfo->IoData);\r
436 }\r
437 else {\r
438 ReadSaveStateRegisterByIndex(CpuIndex, SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX, sizeof(IoMemAddr), &IoMemAddr);\r
439 CopyMem(&IoInfo->IoData, IoMemAddr, mSmmCpuIoWidth[IoMisc.Bits.Length].Width);\r
440 }\r
441 return EFI_SUCCESS;\r
442 }\r
443\r
444 //\r
445 // Convert Register to a register lookup table index\r
446 //\r
447 return ReadSaveStateRegisterByIndex (CpuIndex, GetRegisterIndex (Register), Width, Buffer);\r
448}\r
449\r
450/**\r
451 Write value to a CPU Save State register on the target processor.\r
452\r
453 This function abstracts the differences that whether the CPU Save State register is in the\r
454 IA32 CPU Save State Map or X64 CPU Save State Map.\r
455\r
456 This function supports writing a CPU Save State register in SMBase relocation handler.\r
457\r
458 @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
459 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
460 @param[in] Width The number of bytes to read from the CPU save state.\r
461 @param[in] Buffer Upon entry, this holds the new CPU register value.\r
462\r
463 @retval EFI_SUCCESS The register was written to Save State.\r
464 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
465 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct.\r
466\r
467**/\r
468EFI_STATUS\r
469EFIAPI\r
470WriteSaveStateRegister (\r
471 IN UINTN CpuIndex,\r
472 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
473 IN UINTN Width,\r
474 IN CONST VOID *Buffer\r
475 )\r
476{\r
477 UINTN RegisterIndex;\r
478 SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
479\r
480 //\r
481 // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored\r
482 //\r
483 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {\r
484 return EFI_SUCCESS;\r
485 }\r
486\r
487 //\r
488 // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported\r
489 //\r
490 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {\r
491 return EFI_NOT_FOUND;\r
492 }\r
493\r
494 //\r
495 // Convert Register to a register lookup table index\r
496 //\r
497 RegisterIndex = GetRegisterIndex (Register);\r
498 if (RegisterIndex == 0) {\r
499 return EFI_NOT_FOUND;\r
500 }\r
501\r
502 CpuSaveState = gSmst->CpuSaveState[CpuIndex];\r
503\r
504 //\r
505 // Do not write non-writable SaveState, because it will cause exception.\r
506 //\r
507 if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {\r
508 return EFI_UNSUPPORTED;\r
509 }\r
510\r
511 //\r
512 // Check CPU mode\r
513 //\r
514 if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {\r
515 //\r
516 // If 32-bit mode width is zero, then the specified register can not be accessed\r
517 //\r
518 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r
519 return EFI_NOT_FOUND;\r
520 }\r
521\r
522 //\r
523 // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed\r
524 //\r
525 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r
526 return EFI_INVALID_PARAMETER;\r
527 }\r
528 //\r
529 // Write SMM State register\r
530 //\r
531 ASSERT (CpuSaveState != NULL);\r
532 CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);\r
533 } else {\r
534 //\r
535 // If 64-bit mode width is zero, then the specified register can not be accessed\r
536 //\r
537 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r
538 return EFI_NOT_FOUND;\r
539 }\r
540\r
541 //\r
542 // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed\r
543 //\r
544 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r
545 return EFI_INVALID_PARAMETER;\r
546 }\r
547\r
548 //\r
549 // Write lower 32-bits of SMM State register\r
550 //\r
551 CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));\r
552 if (Width >= 4) {\r
553 //\r
554 // Write upper 32-bits of SMM State register\r
555 //\r
556 CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);\r
557 }\r
558 }\r
559 return EFI_SUCCESS;\r
560}\r
561\r
562/**\r
563 Hook the code executed immediately after an RSM instruction on the currently\r
564 executing CPU. The mode of code executed immediately after RSM must be\r
565 detected, and the appropriate hook must be selected. Always clear the auto\r
566 HALT restart flag if it is set.\r
567\r
568 @param[in] CpuIndex The processor index for the currently\r
569 executing CPU.\r
570 @param[in] CpuState Pointer to SMRAM Save State Map for the\r
571 currently executing CPU.\r
572 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
573 32-bit mode from 64-bit SMM.\r
574 @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
575 same mode as SMM.\r
576\r
577 @retval The value of the original instruction pointer before it was hooked.\r
578\r
579**/\r
580UINT64\r
581EFIAPI\r
582HookReturnFromSmm (\r
583 IN UINTN CpuIndex,\r
584 SMRAM_SAVE_STATE_MAP *CpuState,\r
585 UINT64 NewInstructionPointer32,\r
586 UINT64 NewInstructionPointer\r
587 )\r
588{\r
589 UINT64 OriginalInstructionPointer;\r
590\r
591 OriginalInstructionPointer = SmmCpuFeaturesHookReturnFromSmm (\r
592 CpuIndex,\r
593 CpuState,\r
594 NewInstructionPointer32,\r
595 NewInstructionPointer\r
596 );\r
597 if (OriginalInstructionPointer != 0) {\r
598 return OriginalInstructionPointer;\r
599 }\r
600\r
601 if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {\r
602 OriginalInstructionPointer = (UINT64)CpuState->x86._EIP;\r
603 CpuState->x86._EIP = (UINT32)NewInstructionPointer;\r
604 //\r
605 // Clear the auto HALT restart flag so the RSM instruction returns\r
606 // program control to the instruction following the HLT instruction.\r
607 //\r
608 if ((CpuState->x86.AutoHALTRestart & BIT0) != 0) {\r
609 CpuState->x86.AutoHALTRestart &= ~BIT0;\r
610 }\r
611 } else {\r
612 OriginalInstructionPointer = CpuState->x64._RIP;\r
613 if ((CpuState->x64.IA32_EFER & LMA) == 0) {\r
614 CpuState->x64._RIP = (UINT32)NewInstructionPointer32;\r
615 } else {\r
616 CpuState->x64._RIP = (UINT32)NewInstructionPointer;\r
617 }\r
618 //\r
619 // Clear the auto HALT restart flag so the RSM instruction returns\r
620 // program control to the instruction following the HLT instruction.\r
621 //\r
622 if ((CpuState->x64.AutoHALTRestart & BIT0) != 0) {\r
623 CpuState->x64.AutoHALTRestart &= ~BIT0;\r
624 }\r
625 }\r
626 return OriginalInstructionPointer;\r
627}\r
628\r
629/**\r
630 Get the size of the SMI Handler in bytes.\r
631\r
632 @retval The size, in bytes, of the SMI Handler.\r
633\r
634**/\r
635UINTN\r
636EFIAPI\r
637GetSmiHandlerSize (\r
638 VOID\r
639 )\r
640{\r
641 UINTN Size;\r
642\r
643 Size = SmmCpuFeaturesGetSmiHandlerSize ();\r
644 if (Size != 0) {\r
645 return Size;\r
646 }\r
647 return gcSmiHandlerSize;\r
648}\r
649\r
650/**\r
651 Install the SMI handler for the CPU specified by CpuIndex. This function\r
652 is called by the CPU that was elected as monarch during System Management\r
653 Mode initialization.\r
654\r
655 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
656 The value must be between 0 and the NumberOfCpus field\r
657 in the System Management System Table (SMST).\r
658 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
659 @param[in] SmiStack The stack to use when an SMI is processed by the\r
660 the CPU specified by CpuIndex.\r
661 @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
662 processed by the CPU specified by CpuIndex.\r
663 @param[in] GdtBase The base address of the GDT to use when an SMI is\r
664 processed by the CPU specified by CpuIndex.\r
665 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
666 processed by the CPU specified by CpuIndex.\r
667 @param[in] IdtBase The base address of the IDT to use when an SMI is\r
668 processed by the CPU specified by CpuIndex.\r
669 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
670 processed by the CPU specified by CpuIndex.\r
671 @param[in] Cr3 The base address of the page tables to use when an SMI\r
672 is processed by the CPU specified by CpuIndex.\r
673**/\r
674VOID\r
675EFIAPI\r
676InstallSmiHandler (\r
677 IN UINTN CpuIndex,\r
678 IN UINT32 SmBase,\r
679 IN VOID *SmiStack,\r
680 IN UINTN StackSize,\r
681 IN UINTN GdtBase,\r
682 IN UINTN GdtSize,\r
683 IN UINTN IdtBase,\r
684 IN UINTN IdtSize,\r
685 IN UINT32 Cr3\r
686 )\r
687{\r
f12367a0 688 PROCESSOR_SMM_DESCRIPTOR *Psd;\r
fc504fde 689 UINT32 CpuSmiStack;\r
f12367a0 690\r
a6b7bc7a
MK
691 //\r
692 // Initialize PROCESSOR_SMM_DESCRIPTOR\r
693 //\r
8491e302 694 Psd = (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + SMM_PSD_OFFSET);\r
a6b7bc7a
MK
695 CopyMem (Psd, &gcPsd, sizeof (gcPsd));\r
696 Psd->SmmGdtPtr = (UINT64)GdtBase;\r
697 Psd->SmmGdtSize = (UINT32)GdtSize;\r
698\r
529a5a86
MK
699 if (SmmCpuFeaturesGetSmiHandlerSize () != 0) {\r
700 //\r
701 // Install SMI handler provided by library\r
702 //\r
703 SmmCpuFeaturesInstallSmiHandler (\r
704 CpuIndex,\r
705 SmBase,\r
706 SmiStack,\r
707 StackSize,\r
708 GdtBase,\r
709 GdtSize,\r
710 IdtBase,\r
711 IdtSize,\r
712 Cr3\r
713 );\r
714 return;\r
715 }\r
716\r
717 //\r
718 // Initialize values in template before copy\r
719 //\r
fc504fde
LE
720 CpuSmiStack = (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN));\r
721 PatchInstructionX86 (gPatchSmiStack, CpuSmiStack, 4);\r
c455687f 722 PatchInstructionX86 (gPatchSmiCr3, Cr3, 4);\r
5a1bfda4 723 PatchInstructionX86 (gPatchSmbase, SmBase, 4);\r
529a5a86
MK
724 gSmiHandlerIdtr.Base = IdtBase;\r
725 gSmiHandlerIdtr.Limit = (UINT16)(IdtSize - 1);\r
726\r
727 //\r
728 // Set the value at the top of the CPU stack to the CPU Index\r
729 //\r
fc504fde 730 *(UINTN*)(UINTN)CpuSmiStack = CpuIndex;\r
529a5a86
MK
731\r
732 //\r
733 // Copy template to CPU specific SMI handler location\r
734 //\r
735 CopyMem (\r
8491e302 736 (VOID*)((UINTN)SmBase + SMM_HANDLER_OFFSET),\r
529a5a86
MK
737 (VOID*)gcSmiHandlerTemplate,\r
738 gcSmiHandlerSize\r
739 );\r
740}\r