UefiCpuPkg/PiSmmCpuDxeSmm: Put AP into safe hlt-loop code on S3 path

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / SmmFuncsArch.c

/** @file\r
  SMM CPU misc functions for x64 arch specific.\r
  \r
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "PiSmmCpuDxeSmm.h"\r
\r
/**\r
  Initialize Gdt for all processors.\r
  \r
  @param[in]   Cr3          CR3 value.\r
  @param[out]  GdtStepSize  The step size for GDT table.\r
\r
  @return GdtBase for processor 0.\r
          GdtBase for processor X is: GdtBase + (GdtStepSize * X)\r
**/\r
VOID *\r
InitGdt (\r
  IN  UINTN  Cr3,\r
  OUT UINTN  *GdtStepSize\r
  )\r
{\r
  UINTN                     Index;\r
  IA32_SEGMENT_DESCRIPTOR   *GdtDescriptor;\r
  UINTN                     TssBase;\r
  UINTN                     GdtTssTableSize;\r
  UINT8                     *GdtTssTables;\r
  UINTN                     GdtTableStepSize;\r
\r
  //\r
  // For X64 SMM, we allocate separate GDT/TSS for each CPUs to avoid TSS load contention\r
  // on each SMI entry.\r
  //\r
  GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + 7) & ~7; // 8 bytes aligned\r
  GdtTssTables = (UINT8*)AllocatePages (EFI_SIZE_TO_PAGES (GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus));\r
  ASSERT (GdtTssTables != NULL);\r
  GdtTableStepSize = GdtTssTableSize;\r
\r
  for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {\r
    CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE);\r
\r
    //\r
    // Fixup TSS descriptors\r
    //\r
    TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);\r
    GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;\r
    GdtDescriptor->Bits.BaseLow = (UINT16)(UINTN)TssBase;\r
    GdtDescriptor->Bits.BaseMid = (UINT8)((UINTN)TssBase >> 16);\r
    GdtDescriptor->Bits.BaseHigh = (UINT8)((UINTN)TssBase >> 24);\r
\r
    if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
      //\r
      // Setup top of known good stack as IST1 for each processor.\r
      //\r
      *(UINTN *)(TssBase + TSS_X64_IST1_OFFSET) = (mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize);\r
    }\r
  }\r
\r
  *GdtStepSize = GdtTableStepSize;\r
  return GdtTssTables;\r
}\r
\r
/**\r
  Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.\r
\r
  @param[in] ApHltLoopCode    The 32-bit address of the safe hlt-loop function.\r
  @param[in] TopOfStack       A pointer to the new stack to use for the ApHltLoopCode.\r
\r
**/\r
VOID\r
TransferApToSafeState (\r
  IN UINT32             ApHltLoopCode,\r
  IN UINT32             TopOfStack\r
  )\r
{\r
  SwitchStack (\r
    (SWITCH_STACK_ENTRY_POINT) (UINTN) ApHltLoopCode,\r
    NULL,\r
    NULL,\r
    (VOID *) (UINTN) TopOfStack\r
    );\r
  //\r
  // It should never reach here\r
  //\r
  ASSERT (FALSE);\r
}\r
\r
\r