Update the copyright notice format
[mirror_edk2.git] / UefiCpuPkg / ResetVector / Vtf0 / SerialDebug.asm
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1;------------------------------------------------------------------------------\r
2; @file\r
3; Serial port debug support macros\r
4;\r
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5; Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.<BR>\r
6; This program and the accompanying materials\r
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7; are licensed and made available under the terms and conditions of the BSD License\r
8; which accompanies this distribution. The full text of the license may be found at\r
9; http://opensource.org/licenses/bsd-license.php\r
10;\r
11; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13;\r
14;------------------------------------------------------------------------------\r
15\r
16;//---------------------------------------------\r
17;// UART Register Offsets\r
18;//---------------------------------------------\r
19%define BAUD_LOW_OFFSET 0x00\r
20%define BAUD_HIGH_OFFSET 0x01\r
21%define IER_OFFSET 0x01\r
22%define LCR_SHADOW_OFFSET 0x01\r
23%define FCR_SHADOW_OFFSET 0x02\r
24%define IR_CONTROL_OFFSET 0x02\r
25%define FCR_OFFSET 0x02\r
26%define EIR_OFFSET 0x02\r
27%define BSR_OFFSET 0x03\r
28%define LCR_OFFSET 0x03\r
29%define MCR_OFFSET 0x04\r
30%define LSR_OFFSET 0x05\r
31%define MSR_OFFSET 0x06\r
32\r
33;//---------------------------------------------\r
34;// UART Register Bit Defines\r
35;//---------------------------------------------\r
36%define LSR_TXRDY 0x20\r
37%define LSR_RXDA 0x01\r
38%define DLAB 0x01\r
39\r
40; UINT16 gComBase = 0x3f8;\r
41; UINTN gBps = 115200;\r
42; UINT8 gData = 8;\r
43; UINT8 gStop = 1;\r
44; UINT8 gParity = 0;\r
45; UINT8 gBreakSet = 0;\r
46\r
47%define DEFAULT_COM_BASE 0x3f8\r
48%define DEFAULT_BPS 115200\r
49%define DEFAULT_DATA 8\r
50%define DEFAULT_STOP 1\r
51%define DEFAULT_PARITY 0\r
52%define DEFAULT_BREAK_SET 0\r
53\r
54%define SERIAL_DEFAULT_LCR ( \\r
55 (DEFAULT_BREAK_SET << 6) | \\r
56 (DEFAULT_PARITY << 3) | \\r
57 (DEFAULT_STOP << 2) | \\r
58 (DEFAULT_DATA - 5) \\r
59 )\r
60\r
61%define SERIAL_PORT_IO_BASE_ADDRESS DEFAULT_COM_BASE\r
62\r
63%macro inFromSerialPort 1\r
64 mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1)\r
65 in al, dx\r
66%endmacro\r
67\r
68%macro waitForSerialTxReady 0\r
69\r
70%%waitingForTx:\r
71 inFromSerialPort LSR_OFFSET\r
72 test al, LSR_TXRDY\r
73 jz %%waitingForTx\r
74\r
75%endmacro\r
76\r
77%macro outToSerialPort 2\r
78 mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1)\r
79 mov al, %2\r
80 out dx, al\r
81%endmacro\r
82\r
83%macro debugShowCharacter 1\r
84 waitForSerialTxReady\r
85 outToSerialPort 0, %1\r
86%endmacro\r
87\r
88%macro debugShowHexDigit 1\r
89 %if (%1 < 0xa)\r
90 debugShowCharacter BYTE ('0' + (%1))\r
91 %else\r
92 debugShowCharacter BYTE ('a' + ((%1) - 0xa))\r
93 %endif\r
94%endmacro\r
95\r
96%macro debugNewline 0\r
97 debugShowCharacter `\r`\r
98 debugShowCharacter `\n`\r
99%endmacro\r
100\r
101%macro debugShowPostCode 1\r
102 debugShowHexDigit (((%1) >> 4) & 0xf)\r
103 debugShowHexDigit ((%1) & 0xf)\r
104 debugNewline\r
105%endmacro\r
106\r
107BITS 16\r
108\r
109%macro debugInitialize 0\r
110 jmp real16InitDebug\r
111real16InitDebugReturn:\r
112%endmacro\r
113\r
114real16InitDebug:\r
115 ;\r
116 ; Set communications format\r
117 ;\r
118 outToSerialPort LCR_OFFSET, ((DLAB << 7) | SERIAL_DEFAULT_LCR)\r
119\r
120 ;\r
121 ; Configure baud rate\r
122 ;\r
123 outToSerialPort BAUD_HIGH_OFFSET, ((115200 / DEFAULT_BPS) >> 8)\r
124 outToSerialPort BAUD_LOW_OFFSET, ((115200 / DEFAULT_BPS) & 0xff)\r
125\r
126 ;\r
127 ; Switch back to bank 0\r
128 ;\r
129 outToSerialPort LCR_OFFSET, SERIAL_DEFAULT_LCR\r
130\r
131 jmp real16InitDebugReturn\r
132\r