[mirror_edk2.git] / UnixPkg / Library / UnixBaseLib / X64 / Thunk16.S

#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution.  The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php.\r
#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
# Module Name:\r
#\r
#   Thunk16.S\r
#\r
# Abstract:\r
#\r
#   Real mode thunk\r
#\r
#------------------------------------------------------------------------------\r
\r
#include <Library/BaseLib.h>\r
\r
ASM_GLOBAL ASM_PFX(m16Start)\r
ASM_GLOBAL ASM_PFX(m16Size)\r
ASM_GLOBAL ASM_PFX(mThunk16Attr)\r
ASM_GLOBAL ASM_PFX(m16Gdt)\r
ASM_GLOBAL ASM_PFX(m16GdtrBase)\r
ASM_GLOBAL ASM_PFX(mTransition)\r
ASM_GLOBAL ASM_PFX(InternalAsmThunk16)\r
\r
# define the structure of IA32_REGS\r
#define  _EDI  0       // size 4\r
#define  _ESI  4       // size 4\r
#define  _EBP  8       // size 4\r
#define  _ESP  12      // size 4\r
#define  _EBX  16      // size 4\r
#define  _EDX  20      // size 4\r
#define  _ECX  24      // size 4\r
#define  _EAX  28      // size 4\r
#define  _DS   32      // size 2\r
#define  _ES   34      // size 2\r
#define  _FS   36      // size 2\r
#define  _GS   38      // size 2\r
#define  _EFLAGS  40   // size 8\r
#define  _EIP  48      // size 4\r
#define  _CS  52       // size 2\r
#define  _SS  54       // size 2\r
#define  IA32_REGS_SIZE  56\r
\r
    .data\r
\r
.set L_m16SizeSym,      ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)\r
.set L_mThunk16AttrSym, _ThunkAttr - ASM_PFX(m16Start)\r
.set L_m16GdtSym,       ASM_PFX(NullSeg) - ASM_PFX(m16Start)\r
.set L_m16GdtrBaseSym,  _16GdtrBase - ASM_PFX(m16Start)\r
.set L_mTransitionSym,  _EntryPoint - ASM_PFX(m16Start)\r
\r
ASM_PFX(m16Size):         .word      L_m16SizeSym\r
ASM_PFX(mThunk16Attr):    .word      L_mThunk16AttrSym\r
ASM_PFX(m16Gdt):          .word      L_m16GdtSym\r
ASM_PFX(m16GdtrBase):     .word      L_m16GdtrBaseSym\r
ASM_PFX(mTransition):     .word      L_mTransitionSym\r
\r
    .text\r
\r
ASM_PFX(m16Start):\r
\r
SavedGdt:    .space 10\r
\r
#------------------------------------------------------------------------------\r
# _BackFromUserCode() takes control in real mode after 'retf' has been executed\r
# by user code. It will be shadowed to somewhere in memory below 1MB.\r
#------------------------------------------------------------------------------\r
ASM_GLOBAL ASM_PFX(BackFromUserCode)\r
ASM_PFX(BackFromUserCode):\r
    #\r
    # The order of saved registers on the stack matches the order they appears\r
    # in IA32_REGS structure. This facilitates wrapper function to extract them\r
    # into that structure.\r
    #\r
    # Some instructions for manipulation of segment registers have to be written\r
    # in opcode since 64-bit MASM prevents accesses to those registers.\r
    #\r
    .byte 0x16                          # push ss\r
    .byte 0xe                           # push cs\r
    .byte 0x66\r
    call    L_Base                       # push eip\r
L_Base: \r
    .byte 0x66\r
    pushq   $0                          # reserved high order 32 bits of EFlags\r
    .byte 0x66, 0x9c                    # pushfd actually\r
    cli                                 # disable interrupts\r
    push    %gs\r
    push    %fs\r
    .byte 6                             # push es\r
    .byte 0x1e                          # push ds\r
    .byte 0x66,0x60                     # pushad\r
    .byte 0x66,0xba                     # mov edx, imm32\r
_ThunkAttr:  .space  4\r
    testb   $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl\r
    jz      L_1\r
    movl    $0x15cd2401,%eax            # mov ax, 2401h & int 15h\r
    cli                                 # disable interrupts\r
    jnc     L_2\r
L_1: \r
    testb   $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl\r
    jz      L_2\r
    inb     $0x92,%al\r
    orb     $2,%al\r
    outb    %al, $0x92                   # deactivate A20M#\r
L_2: \r
    movw    %ss,%ax\r
    lea     IA32_REGS_SIZE(%esp), %bp\r
    #\r
    # rsi in the following 2 instructions is indeed bp in 16-bit code\r
    #\r
    movw    %bp, (_ESP - IA32_REGS_SIZE)(%rsi)\r
    .byte 0x66\r
    movl    (_EIP - IA32_REGS_SIZE)(%rsi), %ebx\r
    shlw    $4,%ax                      # shl eax, 4\r
    addw    %ax,%bp                     # add ebp, eax\r
    movw    %cs,%ax\r
    shlw    $4,%ax\r
    lea     (L_64BitCode - L_Base)(%ebx, %eax), %ax\r
    .byte 0x66,0x2e,0x89,0x87           # mov cs:[bx + (L_64Eip - L_Base)], eax\r
.set EipOffset,  L_64Eip - L_Base\r
    .word   EipOffset\r
    .byte 0x66,0xb8                     # mov eax, imm32\r
SavedCr4:   .space  4\r
    movq    %rax, %cr4\r
    #\r
    # rdi in the instruction below is indeed bx in 16-bit code\r
    #\r
    .byte 0x66,0x2e                     # 2eh is "cs:" segment override\r
    lgdt    (SavedGdt - L_Base)(%rdi)\r
    .byte 0x66\r
    movl    $0xc0000080,%ecx\r
    rdmsr\r
    orb     $1,%ah\r
    wrmsr\r
    .byte 0x66,0xb8                     # mov eax, imm32\r
SavedCr0:    .space      4\r
    movq    %rax, %cr0\r
    .byte 0x66,0xea                     # jmp far cs:L_64Bit\r
L_64Eip:     .space      4\r
SavedCs:     .space      2\r
L_64BitCode: \r
    .byte   0x90\r
    .byte   0x67,0xbc                  # mov esp, imm32\r
SavedSp:    .space 4                   # restore stack\r
    nop\r
    ret\r
\r
_EntryPoint: .long      ASM_PFX(ToUserCode) - ASM_PFX(m16Start)\r
             .word      CODE16\r
_16Gdtr:     .word      L_GDT_SIZE - 1\r
_16GdtrBase: .quad      ASM_PFX(NullSeg)\r
_16Idtr:     .word      0x3ff\r
             .long      0\r
\r
#------------------------------------------------------------------------------\r
# _ToUserCode() takes control in real mode before passing control to user code.\r
# It will be shadowed to somewhere in memory below 1MB.\r
#------------------------------------------------------------------------------\r
ASM_GLOBAL ASM_PFX(ToUserCode)\r
ASM_PFX(ToUserCode):\r
    movl    %edx,%ss                    # set new segment selectors\r
    movl    %edx,%ds\r
    movl    %edx,%es\r
    movl    %edx,%fs\r
    movl    %edx,%gs\r
    .byte 0x66\r
    movl    $0xc0000080,%ecx\r
    movq    %rax, %cr0\r
    rdmsr\r
    andb    $0xfe, %ah                  # $0b11111110\r
    wrmsr\r
    movq    %rbp, %cr4\r
    movl    %esi,%ss                    # set up 16-bit stack segment\r
    movw    %bx,%sp                     # set up 16-bit stack pointer\r
    .byte 0x66                          # make the following call 32-bit\r
    call    L_Base1                       # push eip\r
L_Base1: \r
    popw    %bp                         # ebp <- address of L_Base1\r
    pushq   (IA32_REGS_SIZE + 2)(%esp)\r
    lea     0x0c(%rsi), %eax\r
    pushq   %rax\r
    lret                                # execution begins at next instruction\r
L_RealMode: \r
    .byte 0x66,0x2e                     # CS and operand size override\r
    lidt    (_16Idtr - L_Base1)(%rsi)\r
    .byte 0x66,0x61                     # popad\r
    .byte 0x1f                          # pop ds\r
    .byte 0x7                           # pop es\r
    .byte 0x0f, 0xa1                    # pop fs\r
    .byte 0x0f, 0xa9                    # pop gs\r
    .byte 0x66, 0x9d                    # popfd\r
    leaw    4(%esp),%sp                 # skip high order 32 bits of EFlags\r
    .byte 0x66                          # make the following retf 32-bit\r
    lret                                # transfer control to user code\r
\r
.set  CODE16,  ASM_PFX(_16Code) - .\r
.set  DATA16,  ASM_PFX(_16Data) - .\r
.set  DATA32,  ASM_PFX(_32Data) - .\r
\r
ASM_PFX(NullSeg):   .quad      0\r
ASM_PFX(_16Code):\r
            .word -1\r
            .word 0\r
            .byte 0\r
            .byte 0x9b\r
            .byte 0x8f                  # 16-bit segment, 4GB limit\r
            .byte 0\r
ASM_PFX(_16Data):\r
            .word -1\r
            .word 0\r
            .byte 0\r
            .byte 0x93\r
            .byte 0x8f                  # 16-bit segment, 4GB limit\r
            .byte 0\r
ASM_PFX(_32Data):\r
            .word -1\r
            .word 0\r
            .byte 0\r
            .byte 0x93\r
            .byte 0xcf                  # 16-bit segment, 4GB limit\r
            .byte 0\r
\r
.set  L_GDT_SIZE, . - ASM_PFX(NullSeg)\r
\r
#------------------------------------------------------------------------------\r
# IA32_REGISTER_SET *\r
# EFIAPI\r
# InternalAsmThunk16 (\r
#   IN      IA32_REGISTER_SET         *RegisterSet,\r
#   IN OUT  VOID                      *Transition\r
#   );\r
#------------------------------------------------------------------------------\r
\r
ASM_GLOBAL ASM_PFX(InternalAsmThunk16)\r
ASM_PFX(InternalAsmThunk16):\r
    pushq   %rbp\r
    pushq   %rbx\r
    pushq   %rsi\r
    pushq   %rdi\r
    \r
    movl    %ds, %ebx\r
    pushq   %rbx      # Save ds segment register on the stack\r
    movl    %es, %ebx\r
    pushq   %rbx      # Save es segment register on the stack\r
    movl    %ss, %ebx\r
    pushq   %rbx      # Save ss segment register on the stack\r
\r
    .byte   0x0f, 0xa0                  #push   fs\r
    .byte   0x0f, 0xa8                  #push   gs\r
    movq    %rcx, %rsi\r
    movzwl  _SS(%rsi), %r8d\r
    movl    _ESP(%rsi), %edi\r
    lea     -(IA32_REGS_SIZE + 4)(%edi), %rdi\r
    imul    $16, %r8d, %eax \r
    movl    %edi,%ebx                   # ebx <- stack for 16-bit code\r
    pushq   $(IA32_REGS_SIZE / 4)\r
    addl    %eax,%edi                   # edi <- linear address of 16-bit stack\r
    popq    %rcx\r
    rep\r
    movsl                               # copy RegSet\r
    lea     (SavedCr4 - ASM_PFX(m16Start))(%rdx), %ecx\r
    movl    %edx,%eax                   # eax <- transition code address\r
    andl    $0xf,%edx\r
    shll    $12,%eax                    # segment address in high order 16 bits\r
    lea     (ASM_PFX(BackFromUserCode) - ASM_PFX(m16Start))(%rdx), %ax\r
    stosl                               # [edi] <- return address of user code\r
    sgdt    0x60(%rsp)                  # save GDT stack in argument space\r
    movzwq  0x60(%rsp), %r10            # r10 <- GDT limit \r
    lea     ((ASM_PFX(InternalAsmThunk16) - SavedCr4) + 0xf)(%rcx), %r11 \r
    andq    $0xfffffffffffffff0, %r11   # r11 <- 16-byte aligned shadowed GDT table in real mode buffer      \r
    \r
    movw    %r10w, (SavedGdt - SavedCr4)(%rcx)       # save the limit of shadowed GDT table\r
    movq    %r11, (SavedGdt - SavedCr4 + 0x2)(%rcx)  # save the base address of shadowed GDT table\r
    \r
    movq    0x62(%rsp) ,%rsi            # rsi <- the original GDT base address\r
    xchg   %r10, %rcx                   # save rcx to r10 and initialize rcx to be the limit of GDT table \r
    incq   %rcx                         # rcx <- the size of memory to copy\r
    xchg   %r11, %rdi                   # save rdi to r11 and initialize rdi to the base address of shadowed GDT table\r
    rep\r
    movsb                               # perform memory copy to shadow GDT table\r
    movq   %r10, %rcx                   # restore the orignal rcx before memory copy\r
    movq   %r11, %rdi                   # restore the original rdi before memory copy\r
       \r
    sidt    0x50(%rsp)\r
    movq    %cr0, %rax\r
    movl    %eax, (SavedCr0 - SavedCr4)(%rcx)\r
    andl    $0x7ffffffe,%eax            # clear PE, PG bits\r
    movq    %cr4, %rbp\r
    movl    %ebp, (%rcx)                # save CR4 in SavedCr4\r
    andl    $0x300,%ebp                 # clear all but PCE and OSFXSR bits\r
    movl    %r8d, %esi                  # esi <- 16-bit stack segment\r
    .byte      0x6a, DATA32\r
    popq    %rdx\r
    lgdt    (_16Gdtr - SavedCr4)(%rcx)\r
    movl    %edx,%ss\r
    pushfq\r
    lea     -8(%rdx), %edx\r
    lea     L_RetFromRealMode(%rip), %r8\r
    pushq   %r8\r
    movl    %cs, %r8d\r
    movw    %r8w, (SavedCs - SavedCr4)(%rcx)\r
    movl    %esp, (SavedSp - SavedCr4)(%rcx)\r
    .byte   0xff, 0x69                  #  jmp (_EntryPoint - SavedCr4)(%rcx)\r
.set EntryPointSavedCr4Offset, _EntryPoint - SavedCr4\r
    .byte   EntryPointSavedCr4Offset\r
L_RetFromRealMode: \r
    popfq\r
    lgdt    0x60(%rsp)                  # restore protected mode GDTR\r
    lidt    0x50(%rsp)                  # restore protected mode IDTR\r
    lea     -IA32_REGS_SIZE(%rbp), %eax\r
    .byte 0x0f, 0xa9                    # pop gs\r
    .byte 0x0f, 0xa1                    # pop fs\r
    \r
    popq     %rbx\r
    movl     %ebx, %ss\r
    popq     %rbx\r
    movl     %ebx, %es\r
    popq     %rbx\r
    movl     %ebx, %ds\r
    \r
    popq    %rdi\r
    popq    %rsi\r
    popq    %rbx\r
    popq    %rbp\r
\r
    ret\r
Commit	Line	Data
5fc3b5d6	1	#------------------------------------------------------------------------------\r
5fc3b5d6	2	#\r
13f06a56	3	# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
5fc3b5d6	4	# This program and the accompanying materials\r
	5	# are licensed and made available under the terms and conditions of the BSD License\r
	6	# which accompanies this distribution. The full text of the license may be found at\r
	7	# http://opensource.org/licenses/bsd-license.php.\r
	8	#\r
	9	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	10	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	11	#\r
	12	# Module Name:\r
	13	#\r
	14	# Thunk16.S\r
	15	#\r
	16	# Abstract:\r
	17	#\r
	18	# Real mode thunk\r
	19	#\r
	20	#------------------------------------------------------------------------------\r
	21	\r
	22	#include <Library/BaseLib.h>\r
	23	\r
	24	ASM_GLOBAL ASM_PFX(m16Start)\r
	25	ASM_GLOBAL ASM_PFX(m16Size)\r
	26	ASM_GLOBAL ASM_PFX(mThunk16Attr)\r
	27	ASM_GLOBAL ASM_PFX(m16Gdt)\r
	28	ASM_GLOBAL ASM_PFX(m16GdtrBase)\r
	29	ASM_GLOBAL ASM_PFX(mTransition)\r
	30	ASM_GLOBAL ASM_PFX(InternalAsmThunk16)\r
	31	\r
	32	# define the structure of IA32_REGS\r
d0c3acd4	33	#define _EDI 0 // size 4\r
	34	#define _ESI 4 // size 4\r
	35	#define _EBP 8 // size 4\r
	36	#define _ESP 12 // size 4\r
	37	#define _EBX 16 // size 4\r
	38	#define _EDX 20 // size 4\r
	39	#define _ECX 24 // size 4\r
	40	#define _EAX 28 // size 4\r
	41	#define _DS 32 // size 2\r
	42	#define _ES 34 // size 2\r
	43	#define _FS 36 // size 2\r
	44	#define _GS 38 // size 2\r
	45	#define _EFLAGS 40 // size 8\r
	46	#define _EIP 48 // size 4\r
	47	#define _CS 52 // size 2\r
	48	#define _SS 54 // size 2\r
	49	#define IA32_REGS_SIZE 56\r
5fc3b5d6	50	\r
	51	.data\r
	52	\r
d0c3acd4	53	.set L_m16SizeSym, ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)\r
	54	.set L_mThunk16AttrSym, _ThunkAttr - ASM_PFX(m16Start)\r
	55	.set L_m16GdtSym, ASM_PFX(NullSeg) - ASM_PFX(m16Start)\r
	56	.set L_m16GdtrBaseSym, _16GdtrBase - ASM_PFX(m16Start)\r
	57	.set L_mTransitionSym, _EntryPoint - ASM_PFX(m16Start)\r
	58	\r
	59	ASM_PFX(m16Size): .word L_m16SizeSym\r
	60	ASM_PFX(mThunk16Attr): .word L_mThunk16AttrSym\r
	61	ASM_PFX(m16Gdt): .word L_m16GdtSym\r
	62	ASM_PFX(m16GdtrBase): .word L_m16GdtrBaseSym\r
	63	ASM_PFX(mTransition): .word L_mTransitionSym\r
5fc3b5d6	64	\r
	65	.text\r
	66	\r
	67	ASM_PFX(m16Start):\r
	68	\r
	69	SavedGdt: .space 10\r
	70	\r
	71	#------------------------------------------------------------------------------\r
	72	# _BackFromUserCode() takes control in real mode after 'retf' has been executed\r
	73	# by user code. It will be shadowed to somewhere in memory below 1MB.\r
	74	#------------------------------------------------------------------------------\r
	75	ASM_GLOBAL ASM_PFX(BackFromUserCode)\r
	76	ASM_PFX(BackFromUserCode):\r
	77	#\r
	78	# The order of saved registers on the stack matches the order they appears\r
	79	# in IA32_REGS structure. This facilitates wrapper function to extract them\r
	80	# into that structure.\r
	81	#\r
	82	# Some instructions for manipulation of segment registers have to be written\r
	83	# in opcode since 64-bit MASM prevents accesses to those registers.\r
	84	#\r
	85	.byte 0x16 # push ss\r
	86	.byte 0xe # push cs\r
	87	.byte 0x66\r
	88	call L_Base # push eip\r
	89	L_Base: \r
	90	.byte 0x66\r
	91	pushq $0 # reserved high order 32 bits of EFlags\r
	92	.byte 0x66, 0x9c # pushfd actually\r
	93	cli # disable interrupts\r
	94	push %gs\r
	95	push %fs\r
	96	.byte 6 # push es\r
	97	.byte 0x1e # push ds\r
	98	.byte 0x66,0x60 # pushad\r
	99	.byte 0x66,0xba # mov edx, imm32\r
	100	_ThunkAttr: .space 4\r
	101	testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl\r
	102	jz L_1\r
	103	movl $0x15cd2401,%eax # mov ax, 2401h & int 15h\r
	104	cli # disable interrupts\r
	105	jnc L_2\r
	106	L_1: \r
	107	testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl\r
	108	jz L_2\r
	109	inb $0x92,%al\r
	110	orb $2,%al\r
	111	outb %al, $0x92 # deactivate A20M#\r
	112	L_2: \r
13f06a56	113	movw %ss,%ax\r
5fc3b5d6	114	lea IA32_REGS_SIZE(%esp), %bp\r
	115	#\r
	116	# rsi in the following 2 instructions is indeed bp in 16-bit code\r
	117	#\r
	118	movw %bp, (_ESP - IA32_REGS_SIZE)(%rsi)\r
	119	.byte 0x66\r
	120	movl (_EIP - IA32_REGS_SIZE)(%rsi), %ebx\r
	121	shlw $4,%ax # shl eax, 4\r
	122	addw %ax,%bp # add ebp, eax\r
	123	movw %cs,%ax\r
	124	shlw $4,%ax\r
	125	lea (L_64BitCode - L_Base)(%ebx, %eax), %ax\r
	126	.byte 0x66,0x2e,0x89,0x87 # mov cs:[bx + (L_64Eip - L_Base)], eax\r
d0c3acd4	127	.set EipOffset, L_64Eip - L_Base\r
d0c3acd4	128	.word EipOffset\r
5fc3b5d6	129	.byte 0x66,0xb8 # mov eax, imm32\r
	130	SavedCr4: .space 4\r
	131	movq %rax, %cr4\r
	132	#\r
	133	# rdi in the instruction below is indeed bx in 16-bit code\r
	134	#\r
	135	.byte 0x66,0x2e # 2eh is "cs:" segment override\r
	136	lgdt (SavedGdt - L_Base)(%rdi)\r
	137	.byte 0x66\r
	138	movl $0xc0000080,%ecx\r
	139	rdmsr\r
	140	orb $1,%ah\r
	141	wrmsr\r
	142	.byte 0x66,0xb8 # mov eax, imm32\r
	143	SavedCr0: .space 4\r
	144	movq %rax, %cr0\r
	145	.byte 0x66,0xea # jmp far cs:L_64Bit\r
	146	L_64Eip: .space 4\r
	147	SavedCs: .space 2\r
	148	L_64BitCode: \r
	149	.byte 0x90\r
	150	.byte 0x67,0xbc # mov esp, imm32\r
	151	SavedSp: .space 4 # restore stack\r
	152	nop\r
	153	ret\r
	154	\r
	155	_EntryPoint: .long ASM_PFX(ToUserCode) - ASM_PFX(m16Start)\r
	156	.word CODE16\r
d0c3acd4	157	_16Gdtr: .word L_GDT_SIZE - 1\r
5fc3b5d6	158	_16GdtrBase: .quad ASM_PFX(NullSeg)\r
	159	_16Idtr: .word 0x3ff\r
	160	.long 0\r
	161	\r
	162	#------------------------------------------------------------------------------\r
	163	# _ToUserCode() takes control in real mode before passing control to user code.\r
	164	# It will be shadowed to somewhere in memory below 1MB.\r
	165	#------------------------------------------------------------------------------\r
	166	ASM_GLOBAL ASM_PFX(ToUserCode)\r
	167	ASM_PFX(ToUserCode):\r
	168	movl %edx,%ss # set new segment selectors\r
	169	movl %edx,%ds\r
	170	movl %edx,%es\r
	171	movl %edx,%fs\r
	172	movl %edx,%gs\r
	173	.byte 0x66\r
	174	movl $0xc0000080,%ecx\r
	175	movq %rax, %cr0\r
	176	rdmsr\r
	177	andb $0xfe, %ah # $0b11111110\r
	178	wrmsr\r
	179	movq %rbp, %cr4\r
	180	movl %esi,%ss # set up 16-bit stack segment\r
	181	movw %bx,%sp # set up 16-bit stack pointer\r
	182	.byte 0x66 # make the following call 32-bit\r
	183	call L_Base1 # push eip\r
	184	L_Base1: \r
	185	popw %bp # ebp <- address of L_Base1\r
	186	pushq (IA32_REGS_SIZE + 2)(%esp)\r
	187	lea 0x0c(%rsi), %eax\r
	188	pushq %rax\r
	189	lret # execution begins at next instruction\r
	190	L_RealMode: \r
	191	.byte 0x66,0x2e # CS and operand size override\r
	192	lidt (_16Idtr - L_Base1)(%rsi)\r
	193	.byte 0x66,0x61 # popad\r
	194	.byte 0x1f # pop ds\r
	195	.byte 0x7 # pop es\r
	196	.byte 0x0f, 0xa1 # pop fs\r
	197	.byte 0x0f, 0xa9 # pop gs\r
	198	.byte 0x66, 0x9d # popfd\r
	199	leaw 4(%esp),%sp # skip high order 32 bits of EFlags\r
	200	.byte 0x66 # make the following retf 32-bit\r
	201	lret # transfer control to user code\r
	202	\r
	203	.set CODE16, ASM_PFX(_16Code) - .\r
	204	.set DATA16, ASM_PFX(_16Data) - .\r
	205	.set DATA32, ASM_PFX(_32Data) - .\r
	206	\r
	207	ASM_PFX(NullSeg): .quad 0\r
	208	ASM_PFX(_16Code):\r
	209	.word -1\r
	210	.word 0\r
	211	.byte 0\r
	212	.byte 0x9b\r
	213	.byte 0x8f # 16-bit segment, 4GB limit\r
	214	.byte 0\r
	215	ASM_PFX(_16Data):\r
	216	.word -1\r
	217	.word 0\r
	218	.byte 0\r
	219	.byte 0x93\r
	220	.byte 0x8f # 16-bit segment, 4GB limit\r
	221	.byte 0\r
222	ASM_PFX(_32Data):\r
223	.word -1\r
224	.word 0\r
225	.byte 0\r
226	.byte 0x93\r
227	.byte 0xcf # 16-bit segment, 4GB limit\r
228	.byte 0\r
229	\r
d0c3acd4	230	.set L_GDT_SIZE, . - ASM_PFX(NullSeg)\r
5fc3b5d6	231	\r
	232	#------------------------------------------------------------------------------\r
	233	# IA32_REGISTER_SET *\r
	234	# EFIAPI\r
	235	# InternalAsmThunk16 (\r
	236	# IN IA32_REGISTER_SET *RegisterSet,\r
	237	# IN OUT VOID *Transition\r
	238	# );\r
	239	#------------------------------------------------------------------------------\r
	240	\r
	241	ASM_GLOBAL ASM_PFX(InternalAsmThunk16)\r
	242	ASM_PFX(InternalAsmThunk16):\r
	243	pushq %rbp\r
	244	pushq %rbx\r
	245	pushq %rsi\r
	246	pushq %rdi\r
	247	\r
	248	movl %ds, %ebx\r
	249	pushq %rbx # Save ds segment register on the stack\r
	250	movl %es, %ebx\r
	251	pushq %rbx # Save es segment register on the stack\r
	252	movl %ss, %ebx\r
	253	pushq %rbx # Save ss segment register on the stack\r
	254	\r
	255	.byte 0x0f, 0xa0 #push fs\r
	256	.byte 0x0f, 0xa8 #push gs\r
	257	movq %rcx, %rsi\r
	258	movzwl _SS(%rsi), %r8d\r
	259	movl _ESP(%rsi), %edi\r
	260	lea -(IA32_REGS_SIZE + 4)(%edi), %rdi\r
	261	imul $16, %r8d, %eax \r
	262	movl %edi,%ebx # ebx <- stack for 16-bit code\r
	263	pushq $(IA32_REGS_SIZE / 4)\r
	264	addl %eax,%edi # edi <- linear address of 16-bit stack\r
	265	popq %rcx\r
	266	rep\r
	267	movsl # copy RegSet\r
	268	lea (SavedCr4 - ASM_PFX(m16Start))(%rdx), %ecx\r
	269	movl %edx,%eax # eax <- transition code address\r
	270	andl $0xf,%edx\r
	271	shll $12,%eax # segment address in high order 16 bits\r
	272	lea (ASM_PFX(BackFromUserCode) - ASM_PFX(m16Start))(%rdx), %ax\r
	273	stosl # [edi] <- return address of user code\r
	274	sgdt 0x60(%rsp) # save GDT stack in argument space\r
	275	movzwq 0x60(%rsp), %r10 # r10 <- GDT limit \r
	276	lea ((ASM_PFX(InternalAsmThunk16) - SavedCr4) + 0xf)(%rcx), %r11 \r
	277	andq $0xfffffffffffffff0, %r11 # r11 <- 16-byte aligned shadowed GDT table in real mode buffer \r
	278	\r
	279	movw %r10w, (SavedGdt - SavedCr4)(%rcx) # save the limit of shadowed GDT table\r
	280	movq %r11, (SavedGdt - SavedCr4 + 0x2)(%rcx) # save the base address of shadowed GDT table\r
	281	\r
	282	movq 0x62(%rsp) ,%rsi # rsi <- the original GDT base address\r
	283	xchg %r10, %rcx # save rcx to r10 and initialize rcx to be the limit of GDT table \r
	284	incq %rcx # rcx <- the size of memory to copy\r
	285	xchg %r11, %rdi # save rdi to r11 and initialize rdi to the base address of shadowed GDT table\r
	286	rep\r
	287	movsb # perform memory copy to shadow GDT table\r
	288	movq %r10, %rcx # restore the orignal rcx before memory copy\r
	289	movq %r11, %rdi # restore the original rdi before memory copy\r
	290	\r
	291	sidt 0x50(%rsp)\r
	292	movq %cr0, %rax\r
	293	movl %eax, (SavedCr0 - SavedCr4)(%rcx)\r
	294	andl $0x7ffffffe,%eax # clear PE, PG bits\r
295	movq %cr4, %rbp\r
296	movl %ebp, (%rcx) # save CR4 in SavedCr4\r
297	andl $0x300,%ebp # clear all but PCE and OSFXSR bits\r
298	movl %r8d, %esi # esi <- 16-bit stack segment\r
299	.byte 0x6a, DATA32\r
300	popq %rdx\r
301	lgdt (_16Gdtr - SavedCr4)(%rcx)\r
302	movl %edx,%ss\r
303	pushfq\r
304	lea -8(%rdx), %edx\r
305	lea L_RetFromRealMode(%rip), %r8\r
306	pushq %r8\r
307	movl %cs, %r8d\r
308	movw %r8w, (SavedCs - SavedCr4)(%rcx)\r
309	movl %esp, (SavedSp - SavedCr4)(%rcx)\r
310	.byte 0xff, 0x69 # jmp (_EntryPoint - SavedCr4)(%rcx)\r
d0c3acd4	311	.set EntryPointSavedCr4Offset, _EntryPoint - SavedCr4\r
d0c3acd4	312	.byte EntryPointSavedCr4Offset\r
5fc3b5d6	313	L_RetFromRealMode: \r
	314	popfq\r
	315	lgdt 0x60(%rsp) # restore protected mode GDTR\r
	316	lidt 0x50(%rsp) # restore protected mode IDTR\r
	317	lea -IA32_REGS_SIZE(%rbp), %eax\r
	318	.byte 0x0f, 0xa9 # pop gs\r
	319	.byte 0x0f, 0xa1 # pop fs\r
	320	\r
	321	popq %rbx\r
	322	movl %ebx, %ss\r
	323	popq %rbx\r
	324	movl %ebx, %es\r
	325	popq %rbx\r
	326	movl %ebx, %ds\r
	327	\r
	328	popq %rdi\r
	329	popq %rsi\r
	330	popq %rbx\r
	331	popq %rbp\r
	332	\r
	333	ret\r