projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /**************************************************************************;\r |
| 2 | ;* *;\r | |
| 3 | ;* *;\r | |
| 4 | ;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r | |
| 5 | ;* Family of Customer Reference Boards. *;\r | |
| 6 | ;* *;\r | |
| 7 | ;* *;\r | |
| 8 | ;* Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved *;\r | |
| 9 | ;\r | |
| 7ede8060 | 10 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
11 | ;\r |
| 12 | ;* *;\r | |
| 13 | ;* *;\r | |
| 14 | ;**************************************************************************/\r | |
| 15 | \r | |
| 16 | \r | |
| 17 | \r | |
| 18 | // NOTE: The _PDC Implementation is out of the scope of this\r | |
| 19 | // reference code. Please see the latest Hyper-Threading Technology\r | |
| 20 | // Reference Code for complete implementation details.\r | |
| 21 | \r | |
| 22 | Scope(\_PR)\r | |
| 23 | {\r | |
| 24 | Processor(CPU0, // Unique name for Processor 0.\r | |
| 25 | 1, // Unique ID for Processor 0.\r | |
| 26 | 0x00, // CPU0 ACPI P_BLK address = ACPIBASE + 10h.\r | |
| 27 | 0) // CPU0 P_BLK length = 6 bytes.\r | |
| 28 | {}\r | |
| 29 | \r | |
| 30 | Processor(CPU1, // Unique name for Processor 1.\r | |
| 31 | 2, // Unique ID for Processor 1.\r | |
| 32 | 0x00,\r | |
| 33 | 0) // CPU1 P_BLK length = 6 bytes.\r | |
| 34 | {}\r | |
| 35 | \r | |
| 36 | Processor(CPU2, // Unique name for Processor 2.\r | |
| 37 | 3, // Unique ID for Processor 2.\r | |
| 38 | 0x00,\r | |
| 39 | 0) // CPU2 P_BLK length = 6 bytes.\r | |
| 40 | {}\r | |
| 41 | \r | |
| 42 | Processor(CPU3, // Unique name for Processor 3.\r | |
| 43 | 4, // Unique ID for Processor 3.\r | |
| 44 | 0x00,\r | |
| 45 | 0) // CPU3 P_BLK length = 6 bytes.\r | |
| 46 | {}\r | |
| 47 | } // End _PR\r | |
| 48 | \r | |
| 49 | \r |