[mirror_edk2.git] / Vlv2DeviceRefCodePkg / AcpiTablesPCAT / Facp / Facp.aslc

/*++\r
\r
Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
\r
\r
Module Name:\r
\r
  Facp.c\r
\r
\r
Abstract: The fixed ACPI description Table (FADT) Structure\r
\r
\r
--*/\r
#ifdef ECP_FLAG\r
#include "EDKIIGlueDxe.h"\r
#else\r
#include <PiDxe.h>\r
#endif\r
#include <IndustryStandard/Acpi50.h>\r
#include "AcpiTablePlatform.h"\r
\r
EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {\r
  {\r
    EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
    sizeof (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
    EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
    0,                                                                                    // to make sum of entire table == 0\r
    EFI_ACPI_OEM_ID,         // OEMID is a 6 bytes long field\r
    EFI_ACPI_OEM_TABLE_ID,      // OEM table identification(8 bytes long)\r
    EFI_ACPI_OEM_REVISION,      // OEM revision number\r
    EFI_ACPI_CREATOR_ID,        // ASL compiler vendor ID\r
    EFI_ACPI_CREATOR_REVISION   // ASL compiler revision number\r
  },\r
  0,                                                                                    // Physical addesss of FACS\r
  0,                                                                                    // Physical address of DSDT\r
  INT_MODEL,                                                                                    // System Interrupt Model (ignored in 2k and later, must be 0 for 98)\r
  PM_PROFILE,                                                                                   // Preferred PM Profile\r
  SCI_INT_VECTOR,                                                                       // System vector of SCI interrupt\r
  SMI_CMD_IO_PORT,                                                                      // Port address of SMI command port\r
  ACPI_ENABLE,                                                                          // value to write to port smi_cmd to enable ACPI\r
  ACPI_DISABLE,                                                                         // value to write to port smi_cmd to disable ACPI\r
  S4BIOS_REQ,                                                                           // Value to write to SMI CMD port to enter the S4BIOS state\r
  PSTATE_CNT,       // PState control\r
  PM1a_EVT_BLK,                                                                         // Port address of Power Mgt 1a Event Reg Blk\r
  PM1b_EVT_BLK,                                                                         // Port address of Power Mgt 1b Event Reg Blk\r
  PM1a_CNT_BLK,                                                                         // Port address of Power Mgt 1a Ctrl Reg Blk\r
  PM1b_CNT_BLK,                                                                         // Port address of Power Mgt 1b Ctrl Reg Blk\r
  PM2_CNT_BLK,                                                                          // Port address of Power Mgt 2  Ctrl Reg Blk\r
  PM_TMR_BLK,                                                                           // Port address of Power Mgt Timer Ctrl Reg Blk\r
  GPE0_BLK,                                                                             // Port addr of General Purpose Event 0 Reg Blk\r
  GPE1_BLK,                                                                             // Port addr of General Purpose Event 1 Reg Blk\r
  PM1_EVT_LEN,                                                                          // Byte Length of ports at pm1X_evt_blk\r
  PM1_CNT_LEN,                                                                          // Byte Length of ports at pm1X_cnt_blk\r
  PM2_CNT_LEN,                                                                          // Byte Length of ports at pm2_cnt_blk\r
  PM_TM_LEN,                                                                            // Byte Length of ports at pm_tm_blk\r
  GPE0_BLK_LEN,                                                                         // Byte Length of ports at gpe0_blk\r
  GPE1_BLK_LEN,                                                                         // Byte Length of ports at gpe1_blk\r
  GPE1_BASE,                                                                            // offset in gpe model where gpe1 events start\r
  CST_CNT,          // _CST support\r
  P_LVL2_LAT,                                                                           // worst case HW latency to enter/exit C2 state\r
  P_LVL3_LAT,                                                                           // worst case HW latency to enter/exit C3 state\r
  FLUSH_SIZE,                                                                           // Size of area read to flush caches\r
  FLUSH_STRIDE,                                                                         // Stride used in flushing caches\r
  DUTY_OFFSET,                                                                          // bit location of duty cycle field in p_cnt reg\r
  DUTY_WIDTH,                                                                           // bit width of duty cycle field in p_cnt reg\r
  DAY_ALRM,                                                                             // index to day-of-month alarm in RTC CMOS RAM\r
  MON_ALRM,                                                                             // index to month-of-year alarm in RTC CMOS RAM\r
  CENTURY,                                                                              // index to century in RTC CMOS RAM\r
  IAPC_BOOT_ARCH,                                                                       // IA-PCI Boot Architecture Flag\r
  RESERVED,                                                                             // reserved\r
  FLAG,\r
  {\r
    EFI_ACPI_5_0_SYSTEM_IO,\r
    8,\r
    0,\r
    0,\r
    0xCF9\r
  },\r
  0x0E,             // Hardware reset value\r
  0, 0, 0,          // Reserved\r
  0,                // XFirmwareCtrl\r
  0,                // XDsdt\r
  //\r
  // X_PM1a Event Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x20,\r
  0x00,\r
  EFI_ACPI_3_0_DWORD,\r
  PM1a_EVT_BLK,\r
\r
  //\r
  // X_PM1b Event Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x00,\r
  0x00,\r
  EFI_ACPI_RESERVED_BYTE,\r
  PM1b_EVT_BLK,\r
\r
  //\r
  // X_PM1a Control Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x10,\r
  0x00,\r
  EFI_ACPI_3_0_WORD,\r
  PM1a_CNT_BLK,\r
\r
  //\r
  // X_PM1b Control Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x00,\r
  0x00,\r
  EFI_ACPI_RESERVED_BYTE,\r
  PM1b_CNT_BLK,\r
\r
  //\r
  // X_PM2 Control Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x08,\r
  0x00,\r
  EFI_ACPI_3_0_BYTE,\r
  PM2_CNT_BLK,\r
\r
  //\r
  // X_PM Timer Control Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x20,\r
  0x00,\r
  EFI_ACPI_3_0_DWORD,\r
  PM_TMR_BLK,\r
\r
  //\r
  // X_General Purpose Event 0 Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x80,\r
  0x00,\r
  EFI_ACPI_RESERVED_BYTE,\r
  GPE0_BLK,\r
\r
  //\r
  // X_General Purpose Event 1 Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x00,\r
  0x00,\r
  EFI_ACPI_RESERVED_BYTE,\r
  GPE1_BLK,\r
\r
  //\r
  // Sleep Control Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x08,\r
  0x00,\r
  EFI_ACPI_RESERVED_BYTE,\r
  0,\r
\r
  //\r
  // Sleep Status Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x08,\r
  0x00,\r
  EFI_ACPI_RESERVED_BYTE,\r
  0,\r
};\r
\r
VOID*\r
ReferenceAcpiTable (\r
  VOID\r
  )\r
{\r
  //\r
  // Reference the table being generated to prevent the optimizer from\r
  // removing the data structure from the executable\r
  //\r
  return (VOID*)&FACP;\r
}\r
Commit	Line	Data
3cbfba02 DW	1	/*++\r
	2	\r
	3	Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
	4	\r
7ede8060	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
3cbfba02 DW	6	\r
	7	\r
	8	\r
	9	Module Name:\r
	10	\r
	11	Facp.c\r
	12	\r
	13	\r
	14	Abstract: The fixed ACPI description Table (FADT) Structure\r
	15	\r
	16	\r
	17	--*/\r
	18	#ifdef ECP_FLAG\r
	19	#include "EDKIIGlueDxe.h"\r
	20	#else\r
	21	#include <PiDxe.h>\r
	22	#endif\r
	23	#include <IndustryStandard/Acpi50.h>\r
	24	#include "AcpiTablePlatform.h"\r
	25	\r
	26	EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {\r
	27	{\r
	28	EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
	29	sizeof (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
	30	EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
	31	0, // to make sum of entire table == 0\r
	32	EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field\r
	33	EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)\r
	34	EFI_ACPI_OEM_REVISION, // OEM revision number\r
	35	EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID\r
	36	EFI_ACPI_CREATOR_REVISION // ASL compiler revision number\r
	37	},\r
	38	0, // Physical addesss of FACS\r
	39	0, // Physical address of DSDT\r
	40	INT_MODEL, // System Interrupt Model (ignored in 2k and later, must be 0 for 98)\r
	41	PM_PROFILE, // Preferred PM Profile\r
	42	SCI_INT_VECTOR, // System vector of SCI interrupt\r
	43	SMI_CMD_IO_PORT, // Port address of SMI command port\r
	44	ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI\r
	45	ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI\r
	46	S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state\r
	47	PSTATE_CNT, // PState control\r
	48	PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk\r
	49	PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk\r
	50	PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk\r
	51	PM1b_CNT_BLK, // Port address of Power Mgt 1b Ctrl Reg Blk\r
	52	PM2_CNT_BLK, // Port address of Power Mgt 2 Ctrl Reg Blk\r
	53	PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk\r
	54	GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk\r
	55	GPE1_BLK, // Port addr of General Purpose Event 1 Reg Blk\r
	56	PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk\r
	57	PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk\r
	58	PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk\r
	59	PM_TM_LEN, // Byte Length of ports at pm_tm_blk\r
	60	GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk\r
	61	GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk\r
	62	GPE1_BASE, // offset in gpe model where gpe1 events start\r
	63	CST_CNT, // _CST support\r
	64	P_LVL2_LAT, // worst case HW latency to enter/exit C2 state\r
	65	P_LVL3_LAT, // worst case HW latency to enter/exit C3 state\r
	66	FLUSH_SIZE, // Size of area read to flush caches\r
	67	FLUSH_STRIDE, // Stride used in flushing caches\r
	68	DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg\r
	69	DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg\r
70	DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM\r
71	MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM\r
72	CENTURY, // index to century in RTC CMOS RAM\r
73	IAPC_BOOT_ARCH, // IA-PCI Boot Architecture Flag\r
74	RESERVED, // reserved\r
75	FLAG,\r
76	{\r
77	EFI_ACPI_5_0_SYSTEM_IO,\r
78	8,\r
79	0,\r
80	0,\r
81	0xCF9\r
82	},\r
1c32ee1c	83	0x0E, // Hardware reset value\r
3cbfba02 DW	84	0, 0, 0, // Reserved\r
	85	0, // XFirmwareCtrl\r
	86	0, // XDsdt\r
	87	//\r
	88	// X_PM1a Event Register Block\r
	89	//\r
	90	EFI_ACPI_5_0_SYSTEM_IO,\r
	91	0x20,\r
	92	0x00,\r
	93	EFI_ACPI_3_0_DWORD,\r
	94	PM1a_EVT_BLK,\r
	95	\r
	96	//\r
	97	// X_PM1b Event Register Block\r
	98	//\r
	99	EFI_ACPI_5_0_SYSTEM_IO,\r
	100	0x00,\r
	101	0x00,\r
	102	EFI_ACPI_RESERVED_BYTE,\r
	103	PM1b_EVT_BLK,\r
	104	\r
	105	//\r
	106	// X_PM1a Control Register Block\r
	107	//\r
	108	EFI_ACPI_5_0_SYSTEM_IO,\r
	109	0x10,\r
	110	0x00,\r
	111	EFI_ACPI_3_0_WORD,\r
	112	PM1a_CNT_BLK,\r
	113	\r
	114	//\r
	115	// X_PM1b Control Register Block\r
	116	//\r
	117	EFI_ACPI_5_0_SYSTEM_IO,\r
	118	0x00,\r
	119	0x00,\r
	120	EFI_ACPI_RESERVED_BYTE,\r
	121	PM1b_CNT_BLK,\r
	122	\r
	123	//\r
	124	// X_PM2 Control Register Block\r
	125	//\r
	126	EFI_ACPI_5_0_SYSTEM_IO,\r
	127	0x08,\r
	128	0x00,\r
	129	EFI_ACPI_3_0_BYTE,\r
	130	PM2_CNT_BLK,\r
	131	\r
	132	//\r
	133	// X_PM Timer Control Register Block\r
	134	//\r
	135	EFI_ACPI_5_0_SYSTEM_IO,\r
	136	0x20,\r
	137	0x00,\r
	138	EFI_ACPI_3_0_DWORD,\r
	139	PM_TMR_BLK,\r
	140	\r
	141	//\r
	142	// X_General Purpose Event 0 Register Block\r
	143	//\r
	144	EFI_ACPI_5_0_SYSTEM_IO,\r
	145	0x80,\r
	146	0x00,\r
	147	EFI_ACPI_RESERVED_BYTE,\r
148	GPE0_BLK,\r
149	\r
150	//\r
151	// X_General Purpose Event 1 Register Block\r
152	//\r
153	EFI_ACPI_5_0_SYSTEM_IO,\r
154	0x00,\r
155	0x00,\r
156	EFI_ACPI_RESERVED_BYTE,\r
157	GPE1_BLK,\r
158	\r
159	//\r
160	// Sleep Control Register Block\r
161	//\r
162	EFI_ACPI_5_0_SYSTEM_IO,\r
163	0x08,\r
164	0x00,\r
165	EFI_ACPI_RESERVED_BYTE,\r
166	0,\r
167	\r
168	//\r
169	// Sleep Status Register Block\r
170	//\r
171	EFI_ACPI_5_0_SYSTEM_IO,\r
172	0x08,\r
173	0x00,\r
174	EFI_ACPI_RESERVED_BYTE,\r
175	0,\r
176	};\r
177	\r
178	VOID*\r
179	ReferenceAcpiTable (\r
180	VOID\r
181	)\r
182	{\r
183	//\r
184	// Reference the table being generated to prevent the optimizer from\r
185	// removing the data structure from the executable\r
186	//\r
187	return (VOID*)&FACP;\r
188	}\r