[mirror_edk2.git] / Vlv2DeviceRefCodePkg / AcpiTablesPCAT / IgdOpRn.ASL

/*++\r
\r
Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
\r
\r
Module Name:\r
\r
  IgdOpRn.ASL\r
\r
Abstract:\r
\r
  IGD OpRegion/Software SCI Reference Code for the Baytrail Family.\r
  This file contains the interrupt handler code for the Integrated\r
  Graphics Device (IGD) OpRegion/Software SCI mechanism.\r
\r
--*/\r
\r
\r
//NOTES:\r
//\r
// (1)  The code contained in this file inherits the scope in which it\r
//      was included.  So BIOS developers must be sure to include this\r
//      file in the scope associated with the graphics device\r
//      (ex. \_SB.PCI0.GFX0).\r
// (2)  Create a _L06 method under the GPE scope to handle the event\r
//      generated by the graphics driver.  The _L06 method must call\r
//      the GSCI method in this file.\r
// (3)  The MCHP operation region assumes that _ADR and _BBN names\r
//      corresponding to bus 0, device0, function 0 have been declared\r
//      under the PCI0 scope.\r
// (4)  Before the first execution of the GSCI method, the base address\r
//      of the GMCH SCI OpRegion must be programmed where the driver can\r
//      access it. A 32bit scratch register at 0xFC in the IGD PCI\r
//      configuration space (B0/D2/F0/R0FCh) is used for this purpose.\r
\r
//  Define an OperationRegion to cover the GMCH PCI configuration space as\r
//  described in the IGD OpRegion specificiation.\r
\r
//  Define an OperationRegion to cover the IGD PCI configuration space as\r
//  described in the IGD OpRegion specificiation.\r
\r
OperationRegion(IGDP, PCI_Config,0x00,0x100)\r
Field(IGDP, AnyAcc, NoLock, Preserve)\r
{\r
  Offset(0x10),  // GTTMMADR\r
  MADR,   32,\r
  Offset(0x50),  // GMCH Graphics Control Register\r
  ,   1,\r
  GIVD,   1,     // IGD VGA disable bit\r
  ,   1,\r
  GUMA,   5,     // Stolen memory size\r
  ,   8,\r
  Offset(0x54),\r
  ,   4,\r
  GMFN,   1,     // Gfx function 1 enable\r
  ,   27,\r
  Offset(0x5C),  // Stolen Memory Base Address\r
  GSTM,   32,\r
  Offset(0xE0),  // Reg 0xE8, SWSCI control register\r
  GSSE,   1,     // Graphics SCI event (1=event pending)\r
  GSSB,   14,    // Graphics SCI scratchpad bits\r
  GSES,   1,     // Graphics event select (1=SCI)\r
  Offset(0xE4),\r
  ASLE,   8,     // Reg 0xE4, ASLE interrupt register\r
  ,   24,    // Only use first byte of ASLE reg\r
  Offset(0xFC),\r
  ASLS,   32,    // Reg 0xFC, Address of the IGD OpRegion\r
}\r
\r
Method (MCHK, 0, Serialized)\r
{\r
\r
  If (LNotEqual (MADR, 0xFFFFFFFF))\r
  {\r
    OperationRegion(IGMM,SystemMemory,MADR,0x3000)\r
    Field(IGMM,AnyAcc, NoLock, Preserve)\r
    {\r
      Offset(0X20C8),\r
      ,    4,\r
      DCFE,    4,                     // DISPLAY_CLOCK_FREQUENCY_ENCODING\r
    }\r
  }\r
}\r
\r
\r
//  Define an OperationRegion to cover the IGD OpRegion layout.\r
\r
OperationRegion(IGDM, SystemMemory, ASLB, 0x2000)\r
Field(IGDM, AnyAcc, NoLock, Preserve)\r
{\r
\r
  // OpRegion Header\r
\r
  SIGN,   128,                    // Signature-"IntelGraphicsMem"\r
  SIZE,   32,                     // OpRegion Size\r
  OVER,   32,                     // OpRegion Version\r
  SVER,   256,                    // System BIOS Version\r
  VVER,   128,                    // VBIOS Version\r
  GVER,   128,                    // Driver version\r
  MBOX,   32,                     // Mailboxes supported\r
  DMOD,   32,                     // Driver Model\r
  PCON,   32,                     // 96, Platform Configuration\r
\r
  // OpRegion Mailbox 1 (Public ACPI Methods)\r
  // Note: Mailbox 1 is normally reserved for desktop platforms.\r
\r
  Offset(0x100),\r
  DRDY,   32,                     // Driver readiness (ACPI notification)\r
  CSTS,   32,                     // Notification status\r
  CEVT,   32,                     // Current event\r
  Offset(0x120),\r
  DIDL,   32,                     // Supported display device ID list\r
  DDL2,   32,                     // Allows for 8 devices\r
  DDL3,   32,\r
  DDL4,   32,\r
  DDL5,   32,\r
  DDL6,   32,\r
  DDL7,   32,\r
  DDL8,   32,\r
  CPDL,   32,                     // Currently present display list\r
  CPL2,   32,                     // Allows for 8 devices\r
  CPL3,   32,\r
  CPL4,   32,\r
  CPL5,   32,\r
  CPL6,   32,\r
  CPL7,   32,\r
  CPL8,   32,\r
  CAD1,   32,                     // Currently active display list\r
  CAL2,   32,                     // Allows for 8 devices\r
  CAL3,   32,\r
  CAL4,   32,\r
  CAL5,   32,\r
  CAL6,   32,\r
  CAL7,   32,\r
  CAL8,   32,\r
  NADL,   32,                     // Next active display list\r
  NDL2,   32,                     // Allows for 8 devices\r
  NDL3,   32,\r
  NDL4,   32,\r
  NDL5,   32,\r
  NDL6,   32,\r
  NDL7,   32,\r
  NDL8,   32,\r
  ASLP,   32,                     // ASL sleep timeout\r
  TIDX,   32,                     // Toggle table index\r
  CHPD,   32,                     // Current hot plug enable indicator\r
  CLID,   32,                     // Current lid state indicator\r
  CDCK,   32,                     // Current docking state indicator\r
  SXSW,   32,                     // Display switch notify on resume\r
  EVTS,   32,                     // Events supported by ASL (diag only)\r
  CNOT,   32,                     // Current OS notifications (diag only)\r
  NRDY,   32,\r
\r
  // OpRegion Mailbox 2 (Software SCI Interface)\r
\r
  Offset(0x200),                  // SCIC\r
  SCIE,   1,                      // SCI entry bit (1=call unserviced)\r
  GEFC,   4,                      // Entry function code\r
  GXFC,   3,                      // Exit result\r
  GESF,   8,                      // Entry/exit sub-function/parameter\r
  ,   16,                     // SCIC[31:16] reserved\r
  Offset(0x204),                  // PARM\r
  PARM,   32,                     // PARM register (extra parameters)\r
  DSLP,   32,                     // Driver sleep time out\r
\r
  // OpRegion Mailbox 3 (BIOS to Driver Notification)\r
  // Note: Mailbox 3 is normally reserved for desktop platforms.\r
\r
  Offset(0x300),\r
  ARDY,   32,                     // Driver readiness (power conservation)\r
  ASLC,   32,                     // ASLE interrupt command/status\r
  TCHE,   32,                     // Technology enabled indicator\r
  ALSI,   32,                     // Current ALS illuminance reading\r
  BCLP,   32,                     // Backlight brightness\r
  PFIT,   32,                     // Panel fitting state or request\r
  CBLV,   32,                     // Current brightness level\r
  BCLM,   320,                    // Backlight brightness level duty cycle mapping table\r
  CPFM,   32,                     // Current panel fitting mode\r
  EPFM,   32,                     // Enabled panel fitting modes\r
  PLUT,   592,                    // Optional. 74-byte Panel LUT Table\r
  PFMB,   32,                     // Optional. PWM Frequency and Minimum Brightness\r
  CCDV,   32,                     // Optional. Gamma, Brightness, Contrast values.\r
  PCFT,   32,                     // Optional. Power Conservation Features\r
\r
  Offset(0x3B6),\r
  STAT,   32,                     // Status register\r
\r
  // OpRegion Mailbox 4 (VBT)\r
\r
  Offset(0x400),\r
  GVD1,   0xC000,                 // 6K bytes maximum VBT image\r
\r
  // OpRegion Mailbox 5 (BIOS to Driver Notification Extension)\r
\r
  Offset(0x1C00),\r
  PHED,   32,                     // Panel Header\r
  BDDC,   2048,                   // Panel EDID (Max 256 bytes)\r
\r
}\r
\r
\r
\r
// Convert boot display type into a port mask.\r
\r
Name (DBTB, Package()\r
{\r
  0x0000,                         // Automatic\r
  0x0007,                         // Port-0 : Integrated CRT\r
  0x0038,                         // Port-1 : DVO-A, or Integrated LVDS\r
  0x01C0,                         // Port-2 : SDVO-B, or SDVO-B/C\r
  0x0E00,                         // Port-3 : SDVO-C\r
  0x003F,                         // [CRT + DVO-A / Integrated LVDS]\r
  0x01C7,                         // [CRT + SDVO-B] or [CRT + SDVO-B/C]\r
  0x0E07,                         // [CRT + SDVO-C]\r
  0x01F8,                         // [DVO-A / Integrated LVDS + SDVO-B]\r
  0x0E38,                         // [DVO-A / Integrated LVDS + SDVO-C]\r
  0x0FC0,                         // [SDVO-B + SDVO-C]\r
  0x0000,                         // Reserved\r
  0x0000,                         // Reserved\r
  0x0000,                         // Reserved\r
  0x0000,                         // Reserved\r
  0x0000,                         // Reserved\r
  0x7000,                         // Port-4: Integrated TV\r
  0x7007,                         // [Integrated TV + CRT]\r
  0x7038,                         // [Integrated TV + LVDS]\r
  0x71C0,                         // [Integrated TV + DVOB]\r
  0x7E00                          // [Integrated TV + DVOC]\r
})\r
\r
// Core display clock value table.\r
\r
Name (CDCT, Package()\r
{\r
  Package() {160},\r
  Package() {200},\r
  Package() {267},\r
  Package() {320},\r
  Package() {356},\r
  Package() {400},\r
})\r
\r
// Defined exit result values:\r
\r
Name (SUCC, 1)                          // Exit result: Success\r
Name (NVLD, 2)                          // Exit result: Invalid parameter\r
Name (CRIT, 4)                          // Exit result: Critical failure\r
Name (NCRT, 6)                          // Exit result: Non-critical failure\r
\r
\r
/************************************************************************;\r
;*\r
;* Name: GSCI\r
;*\r
;* Description: Handles an SCI generated by the graphics driver.  The\r
;*              PARM and SCIC input fields are parsed to determine the\r
;*              functionality requested by the driver.  GBDA or SBCB\r
;*              is called based on the input data in SCIC.\r
;*\r
;* Usage:       The method must be called in response to a GPE 06 event\r
;*              which will be generated by the graphics driver.\r
;*              Ex: Method(\_GPE._L06) {Return(\_SB.PCI0.GFX0.GSCI())}\r
;*\r
;* Input:       PARM and SCIC are indirect inputs\r
;*\r
;* Output:      PARM and SIC are indirect outputs\r
;*\r
;* References:  GBDA (Get BIOS Data method), SBCB (System BIOS Callback\r
;*              method)\r
;*\r
;************************************************************************/\r
\r
Method (GSCI, 0, Serialized)\r
{\r
  Include("IgdOGBDA.ASL") // "Get BIOS Data" Functions\r
  Include("IgdOSBCB.ASL") // "System BIOS CallBacks"\r
\r
  If (LEqual(GEFC, 4))\r
  {\r
    Store(GBDA(), GXFC)     // Process Get BIOS Data functions\r
  }\r
\r
  If (LEqual(GEFC, 6))\r
  {\r
    Store(SBCB(), GXFC)     // Process BIOS Callback functions\r
  }\r
\r
  Store(0, GEFC)                  // Wipe out the entry function code\r
  Store(1, SCIS)                  // Clear the GUNIT SCI status bit in PCH ACPI I/O space.\r
  Store(0, GSSE)                  // Clear the SCI generation bit in PCI space.\r
  Store(0, SCIE)                  // Clr SCI serviced bit to signal completion\r
\r
  Return(Zero)\r
}\r
\r
// Include MOBLFEAT.ASL for mobile systems only.  Remove for desktop.\r
Include("IgdOMOBF.ASL")     // IGD SCI mobile features\r
Commit	Line	Data
3cbfba02 DW	1	/*++\r
	2	\r
	3	Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
	4	\r
7ede8060	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
3cbfba02 DW	6	\r
	7	\r
	8	\r
	9	Module Name:\r
	10	\r
	11	IgdOpRn.ASL\r
	12	\r
	13	Abstract:\r
	14	\r
	15	IGD OpRegion/Software SCI Reference Code for the Baytrail Family.\r
	16	This file contains the interrupt handler code for the Integrated\r
	17	Graphics Device (IGD) OpRegion/Software SCI mechanism.\r
	18	\r
	19	--*/\r
	20	\r
	21	\r
	22	//NOTES:\r
	23	//\r
	24	// (1) The code contained in this file inherits the scope in which it\r
	25	// was included. So BIOS developers must be sure to include this\r
	26	// file in the scope associated with the graphics device\r
	27	// (ex. \_SB.PCI0.GFX0).\r
	28	// (2) Create a _L06 method under the GPE scope to handle the event\r
	29	// generated by the graphics driver. The _L06 method must call\r
	30	// the GSCI method in this file.\r
	31	// (3) The MCHP operation region assumes that _ADR and _BBN names\r
	32	// corresponding to bus 0, device0, function 0 have been declared\r
	33	// under the PCI0 scope.\r
	34	// (4) Before the first execution of the GSCI method, the base address\r
	35	// of the GMCH SCI OpRegion must be programmed where the driver can\r
	36	// access it. A 32bit scratch register at 0xFC in the IGD PCI\r
	37	// configuration space (B0/D2/F0/R0FCh) is used for this purpose.\r
	38	\r
	39	// Define an OperationRegion to cover the GMCH PCI configuration space as\r
	40	// described in the IGD OpRegion specificiation.\r
	41	\r
	42	// Define an OperationRegion to cover the IGD PCI configuration space as\r
	43	// described in the IGD OpRegion specificiation.\r
	44	\r
	45	OperationRegion(IGDP, PCI_Config,0x00,0x100)\r
	46	Field(IGDP, AnyAcc, NoLock, Preserve)\r
	47	{\r
	48	Offset(0x10), // GTTMMADR\r
	49	MADR, 32,\r
	50	Offset(0x50), // GMCH Graphics Control Register\r
	51	, 1,\r
	52	GIVD, 1, // IGD VGA disable bit\r
	53	, 1,\r
	54	GUMA, 5, // Stolen memory size\r
	55	, 8,\r
	56	Offset(0x54),\r
	57	, 4,\r
	58	GMFN, 1, // Gfx function 1 enable\r
	59	, 27,\r
	60	Offset(0x5C), // Stolen Memory Base Address\r
	61	GSTM, 32,\r
	62	Offset(0xE0), // Reg 0xE8, SWSCI control register\r
	63	GSSE, 1, // Graphics SCI event (1=event pending)\r
	64	GSSB, 14, // Graphics SCI scratchpad bits\r
	65	GSES, 1, // Graphics event select (1=SCI)\r
	66	Offset(0xE4),\r
	67	ASLE, 8, // Reg 0xE4, ASLE interrupt register\r
	68	, 24, // Only use first byte of ASLE reg\r
	69	Offset(0xFC),\r
70	ASLS, 32, // Reg 0xFC, Address of the IGD OpRegion\r
71	}\r
72	\r
73	Method (MCHK, 0, Serialized)\r
74	{\r
75	\r
76	If (LNotEqual (MADR, 0xFFFFFFFF))\r
77	{\r
78	OperationRegion(IGMM,SystemMemory,MADR,0x3000)\r
79	Field(IGMM,AnyAcc, NoLock, Preserve)\r
80	{\r
81	Offset(0X20C8),\r
82	, 4,\r
83	DCFE, 4, // DISPLAY_CLOCK_FREQUENCY_ENCODING\r
84	}\r
85	}\r
86	}\r
87	\r
88	\r
89	// Define an OperationRegion to cover the IGD OpRegion layout.\r
90	\r
91	OperationRegion(IGDM, SystemMemory, ASLB, 0x2000)\r
92	Field(IGDM, AnyAcc, NoLock, Preserve)\r
93	{\r
94	\r
95	// OpRegion Header\r
96	\r
97	SIGN, 128, // Signature-"IntelGraphicsMem"\r
98	SIZE, 32, // OpRegion Size\r
99	OVER, 32, // OpRegion Version\r
100	SVER, 256, // System BIOS Version\r
101	VVER, 128, // VBIOS Version\r
102	GVER, 128, // Driver version\r
103	MBOX, 32, // Mailboxes supported\r
104	DMOD, 32, // Driver Model\r
105	PCON, 32, // 96, Platform Configuration\r
106	\r
107	// OpRegion Mailbox 1 (Public ACPI Methods)\r
108	// Note: Mailbox 1 is normally reserved for desktop platforms.\r
109	\r
110	Offset(0x100),\r
111	DRDY, 32, // Driver readiness (ACPI notification)\r
112	CSTS, 32, // Notification status\r
113	CEVT, 32, // Current event\r
114	Offset(0x120),\r
115	DIDL, 32, // Supported display device ID list\r
116	DDL2, 32, // Allows for 8 devices\r
117	DDL3, 32,\r
118	DDL4, 32,\r
119	DDL5, 32,\r
120	DDL6, 32,\r
121	DDL7, 32,\r
122	DDL8, 32,\r
123	CPDL, 32, // Currently present display list\r
124	CPL2, 32, // Allows for 8 devices\r
125	CPL3, 32,\r
126	CPL4, 32,\r
127	CPL5, 32,\r
128	CPL6, 32,\r
129	CPL7, 32,\r
130	CPL8, 32,\r
131	CAD1, 32, // Currently active display list\r
132	CAL2, 32, // Allows for 8 devices\r
133	CAL3, 32,\r
134	CAL4, 32,\r
135	CAL5, 32,\r
136	CAL6, 32,\r
137	CAL7, 32,\r
138	CAL8, 32,\r
139	NADL, 32, // Next active display list\r
140	NDL2, 32, // Allows for 8 devices\r
141	NDL3, 32,\r
142	NDL4, 32,\r
143	NDL5, 32,\r
144	NDL6, 32,\r
145	NDL7, 32,\r
146	NDL8, 32,\r
147	ASLP, 32, // ASL sleep timeout\r
148	TIDX, 32, // Toggle table index\r
149	CHPD, 32, // Current hot plug enable indicator\r
150	CLID, 32, // Current lid state indicator\r
151	CDCK, 32, // Current docking state indicator\r
152	SXSW, 32, // Display switch notify on resume\r
153	EVTS, 32, // Events supported by ASL (diag only)\r
154	CNOT, 32, // Current OS notifications (diag only)\r
155	NRDY, 32,\r
156	\r
157	// OpRegion Mailbox 2 (Software SCI Interface)\r
158	\r
159	Offset(0x200), // SCIC\r
160	SCIE, 1, // SCI entry bit (1=call unserviced)\r
161	GEFC, 4, // Entry function code\r
162	GXFC, 3, // Exit result\r
163	GESF, 8, // Entry/exit sub-function/parameter\r
164	, 16, // SCIC[31:16] reserved\r
165	Offset(0x204), // PARM\r
166	PARM, 32, // PARM register (extra parameters)\r
167	DSLP, 32, // Driver sleep time out\r
168	\r
169	// OpRegion Mailbox 3 (BIOS to Driver Notification)\r
170	// Note: Mailbox 3 is normally reserved for desktop platforms.\r
171	\r
172	Offset(0x300),\r
173	ARDY, 32, // Driver readiness (power conservation)\r
174	ASLC, 32, // ASLE interrupt command/status\r
175	TCHE, 32, // Technology enabled indicator\r
176	ALSI, 32, // Current ALS illuminance reading\r
177	BCLP, 32, // Backlight brightness\r
178	PFIT, 32, // Panel fitting state or request\r
179	CBLV, 32, // Current brightness level\r
180	BCLM, 320, // Backlight brightness level duty cycle mapping table\r
181	CPFM, 32, // Current panel fitting mode\r
182	EPFM, 32, // Enabled panel fitting modes\r
183	PLUT, 592, // Optional. 74-byte Panel LUT Table\r
184	PFMB, 32, // Optional. PWM Frequency and Minimum Brightness\r
185	CCDV, 32, // Optional. Gamma, Brightness, Contrast values.\r
186	PCFT, 32, // Optional. Power Conservation Features\r
187	\r
188	Offset(0x3B6),\r
189	STAT, 32, // Status register\r
190	\r
191	// OpRegion Mailbox 4 (VBT)\r
192	\r
193	Offset(0x400),\r
194	GVD1, 0xC000, // 6K bytes maximum VBT image\r
195	\r
196	// OpRegion Mailbox 5 (BIOS to Driver Notification Extension)\r
197	\r
198	Offset(0x1C00),\r
199	PHED, 32, // Panel Header\r
200	BDDC, 2048, // Panel EDID (Max 256 bytes)\r
201	\r
202	}\r
203	\r
204	\r
205	\r
206	// Convert boot display type into a port mask.\r
207	\r
208	Name (DBTB, Package()\r
209	{\r
210	0x0000, // Automatic\r
211	0x0007, // Port-0 : Integrated CRT\r
212	0x0038, // Port-1 : DVO-A, or Integrated LVDS\r
213	0x01C0, // Port-2 : SDVO-B, or SDVO-B/C\r
214	0x0E00, // Port-3 : SDVO-C\r
215	0x003F, // [CRT + DVO-A / Integrated LVDS]\r
216	0x01C7, // [CRT + SDVO-B] or [CRT + SDVO-B/C]\r
217	0x0E07, // [CRT + SDVO-C]\r
218	0x01F8, // [DVO-A / Integrated LVDS + SDVO-B]\r
219	0x0E38, // [DVO-A / Integrated LVDS + SDVO-C]\r
220	0x0FC0, // [SDVO-B + SDVO-C]\r
221	0x0000, // Reserved\r
222	0x0000, // Reserved\r
223	0x0000, // Reserved\r
224	0x0000, // Reserved\r
225	0x0000, // Reserved\r
226	0x7000, // Port-4: Integrated TV\r
227	0x7007, // [Integrated TV + CRT]\r
228	0x7038, // [Integrated TV + LVDS]\r
229	0x71C0, // [Integrated TV + DVOB]\r
230	0x7E00 // [Integrated TV + DVOC]\r
231	})\r
232	\r
233	// Core display clock value table.\r
234	\r
235	Name (CDCT, Package()\r
236	{\r
237	Package() {160},\r
238	Package() {200},\r
239	Package() {267},\r
240	Package() {320},\r
241	Package() {356},\r
242	Package() {400},\r
243	})\r
244	\r
245	// Defined exit result values:\r
246	\r
247	Name (SUCC, 1) // Exit result: Success\r
248	Name (NVLD, 2) // Exit result: Invalid parameter\r
249	Name (CRIT, 4) // Exit result: Critical failure\r
250	Name (NCRT, 6) // Exit result: Non-critical failure\r
251	\r
252	\r
253	/************************************************************************;\r
254	;*\r
255	;* Name: GSCI\r
256	;*\r
257	;* Description: Handles an SCI generated by the graphics driver. The\r
258	;* PARM and SCIC input fields are parsed to determine the\r
259	;* functionality requested by the driver. GBDA or SBCB\r
260	;* is called based on the input data in SCIC.\r
261	;*\r
262	;* Usage: The method must be called in response to a GPE 06 event\r
263	;* which will be generated by the graphics driver.\r
264	;* Ex: Method(\_GPE._L06) {Return(\_SB.PCI0.GFX0.GSCI())}\r
265	;*\r
266	;* Input: PARM and SCIC are indirect inputs\r
267	;*\r
268	;* Output: PARM and SIC are indirect outputs\r
269	;*\r
270	;* References: GBDA (Get BIOS Data method), SBCB (System BIOS Callback\r
271	;* method)\r
272	;*\r
273	;************************************************************************/\r
274	\r
275	Method (GSCI, 0, Serialized)\r
276	{\r
277	Include("IgdOGBDA.ASL") // "Get BIOS Data" Functions\r
278	Include("IgdOSBCB.ASL") // "System BIOS CallBacks"\r
279	\r
280	If (LEqual(GEFC, 4))\r
281	{\r
282	Store(GBDA(), GXFC) // Process Get BIOS Data functions\r
283	}\r
284	\r
285	If (LEqual(GEFC, 6))\r
286	{\r
287	Store(SBCB(), GXFC) // Process BIOS Callback functions\r
288	}\r
289	\r
290	Store(0, GEFC) // Wipe out the entry function code\r
291	Store(1, SCIS) // Clear the GUNIT SCI status bit in PCH ACPI I/O space.\r
292	Store(0, GSSE) // Clear the SCI generation bit in PCI space.\r
293	Store(0, SCIE) // Clr SCI serviced bit to signal completion\r
294	\r
295	Return(Zero)\r
296	}\r
297	\r
298	// Include MOBLFEAT.ASL for mobile systems only. Remove for desktop.\r
299	Include("IgdOMOBF.ASL") // IGD SCI mobile features\r