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3cbfba02 DW |
1 | /** @file\r |
2 | Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r | |
7ede8060 | 3 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
3cbfba02 DW |
4 | \r |
5 | **/\r | |
6 | \r | |
7 | Device(IOTD) { \r | |
8 | Name(_HID, "MSFT8000")\r | |
9 | Name(_CID, "MSFT8000")\r | |
10 | \r | |
11 | Name(_CRS, ResourceTemplate() { \r | |
12 | // Index 0 \r | |
13 | SPISerialBus( // Pin 5, 7, 9 , 11 of JP1 for SIO_SPI\r | |
14 | 1, // Device selection\r | |
15 | PolarityLow, // Device selection polarity\r | |
16 | FourWireMode, // wiremode\r | |
17 | 8, // databit len\r | |
18 | ControllerInitiated, // slave mode\r | |
19 | 8000000, // Connection speed\r | |
20 | ClockPolarityLow, // Clock polarity\r | |
21 | ClockPhaseSecond, // clock phase\r | |
22 | "\\_SB.SPI1", // ResourceSource: SPI bus controller name\r | |
23 | 0, // ResourceSourceIndex\r | |
24 | ResourceConsumer, // Resource usage\r | |
25 | JSPI, // DescriptorName: creates name for offset of resource descriptor\r | |
26 | ) // Vendor Data \r | |
27 | \r | |
28 | // Index 1 \r | |
29 | I2CSerialBus( // Pin 13, 15 of JP1, for SIO_I2C5 (signal)\r | |
30 | 0x00, // SlaveAddress: bus address (TBD)\r | |
31 | , // SlaveMode: default to ControllerInitiated\r | |
32 | 400000, // ConnectionSpeed: in Hz\r | |
33 | , // Addressing Mode: default to 7 bit\r | |
34 | "\\_SB.I2C6", // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I2C5(0-based) is reported as ACPI I2C6(1-based))\r | |
35 | ,\r | |
36 | ,\r | |
37 | JI2C, // Descriptor Name: creates name for offset of resource descriptor\r | |
38 | ) // VendorData\r | |
39 | \r | |
40 | // Index 2\r | |
41 | UARTSerialBus( // Pin 17, 19 of JP1, for SIO_UART2\r | |
42 | 115200, // InitialBaudRate: in bits ber second\r | |
43 | , // BitsPerByte: default to 8 bits\r | |
44 | , // StopBits: Defaults to one bit\r | |
45 | 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled\r | |
46 | , // IsBigEndian: default to LittleEndian\r | |
47 | , // Parity: Defaults to no parity\r | |
48 | , // FlowControl: Defaults to no flow control\r | |
49 | 32, // ReceiveBufferSize\r | |
50 | 32, // TransmitBufferSize\r | |
51 | "\\_SB.URT2", // ResourceSource: UART bus controller name\r | |
52 | ,\r | |
53 | ,\r | |
54 | UAR2, // DescriptorName: creates name for offset of resource descriptor\r | |
55 | ) \r | |
56 | \r | |
57 | // Index 3\r | |
58 | GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {0} // Pin 21 of JP1 (GPIO_S5[00])\r | |
59 | // Index 4\r | |
60 | GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {0} \r | |
61 | \r | |
62 | // Index 5\r | |
63 | GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {1} // Pin 23 of JP1 (GPIO_S5[01])\r | |
64 | // Index 6\r | |
65 | GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {1}\r | |
66 | \r | |
67 | // Index 7\r | |
68 | GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {2} // Pin 25 of JP1 (GPIO_S5[02])\r | |
69 | // Index 8\r | |
70 | GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {2} \r | |
71 | \r | |
72 | // Index 9\r | |
73 | UARTSerialBus( // Pin 6, 8, 10, 12 of JP1, for SIO_UART1\r | |
74 | 115200, // InitialBaudRate: in bits ber second\r | |
75 | , // BitsPerByte: default to 8 bits\r | |
76 | , // StopBits: Defaults to one bit\r | |
77 | 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled\r | |
78 | , // IsBigEndian: default to LittleEndian\r | |
79 | , // Parity: Defaults to no parity\r | |
80 | FlowControlHardware, // FlowControl: Defaults to no flow control\r | |
81 | 32, // ReceiveBufferSize\r | |
82 | 32, // TransmitBufferSize\r | |
83 | "\\_SB.URT1", // ResourceSource: UART bus controller name\r | |
84 | ,\r | |
85 | ,\r | |
86 | UAR1, // DescriptorName: creates name for offset of resource descriptor\r | |
87 | ) \r | |
88 | \r | |
89 | // Index 10\r | |
90 | GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {62} // Pin 14 of JP1 (GPIO_SC[62])\r | |
91 | // Index 11\r | |
92 | GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {62} \r | |
93 | \r | |
94 | // Index 12\r | |
95 | GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {63} // Pin 16 of JP1 (GPIO_SC[63])\r | |
96 | // Index 13\r | |
97 | GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {63} \r | |
98 | \r | |
99 | // Index 14\r | |
100 | GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {65} // Pin 18 of JP1 (GPIO_SC[65])\r | |
101 | // Index 15\r | |
102 | GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {65} \r | |
103 | \r | |
104 | // Index 16\r | |
105 | GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {64} // Pin 20 of JP1 (GPIO_SC[64])\r | |
106 | // Index 17\r | |
107 | GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {64} \r | |
108 | \r | |
109 | // Index 18\r | |
110 | GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {94} // Pin 22 of JP1 (GPIO_SC[94])\r | |
111 | // Index 19\r | |
112 | GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {94} \r | |
113 | \r | |
114 | // Index 20\r | |
115 | GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {95} // Pin 24 of JP1 (GPIO_SC[95])\r | |
116 | // Index 21\r | |
117 | GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {95} \r | |
118 | \r | |
119 | // Index 22\r | |
120 | GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {54} // Pin 26 of JP1 (GPIO_SC[54])\r | |
121 | // Index 23\r | |
122 | GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {54}\r | |
123 | })\r | |
124 | \r | |
125 | Name(_DSD, Package() {\r | |
126 | ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),\r | |
127 | Package(1) { // Just one Property for IOT (at this time) \r | |
128 |