projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /**************************************************************************;\r |
| 2 | ;* *;\r | |
| 3 | ;* *;\r | |
| 4 | ;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r | |
| 5 | ;* Family of Customer Reference Boards. *;\r | |
| 6 | ;* *;\r | |
| 7 | ;* *;\r | |
| 8 | ;* Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved *;\r | |
| 9 | ;\r | |
| 7ede8060 | 10 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
11 | ;\r |
| 12 | ;* *;\r | |
| 13 | ;* *;\r | |
| 14 | ;**************************************************************************/\r | |
| 15 | \r | |
| 16 | \r | |
| 17 | // Define various SMBus PCI Configuration Space Registers.\r | |
| 18 | \r | |
| 19 | OperationRegion(SMBP,PCI_Config,0x40,0xC0)\r | |
| 20 | Field(SMBP,DWordAcc,NoLock,Preserve)\r | |
| 21 | {\r | |
| 22 | , 2,\r | |
| 23 | I2CE, 1\r | |
| 24 | }\r | |
| 25 | \r | |
| 26 | // SMBus Send Byte - This function will write a single byte of\r | |
| 27 | // data to a specific Slave Device per SMBus Send Byte Protocol.\r | |
| 28 | // Arg0 = Address\r | |
| 29 | // Arg1 = Data\r | |
| 30 | // Return: Success = 1\r | |
| 31 | // Failure = 0\r | |
| 32 | \r | |
| 33 | Method(SSXB,2,Serialized)\r | |
| 34 | {\r | |
| 35 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 36 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 37 | {\r | |
| 38 | , 5,\r | |
| 39 | SBAR, 11\r | |
| 40 | }\r | |
| 41 | \r | |
| 42 | // Define various SMBus IO Mapped Registers.\r | |
| 43 | \r | |
| 44 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 45 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 46 | {\r | |
| 47 | HSTS, 8, // 0 - Host Status Register\r | |
| 48 | Offset(0x02),\r | |
| 49 | HCON, 8, // 2 - Host Control\r | |
| 50 | HCOM, 8, // 3 - Host Command\r | |
| 51 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 52 | DAT0, 8, // 5 - Host Data 0\r | |
| 53 | DAT1, 8, // 6 - Host Data 1\r | |
| 54 | HBDR, 8, // 7 - Host Block Data\r | |
| 55 | PECR, 8, // 8 - Packer Error Check\r | |
| 56 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 57 | SDAT, 16, // A - Slave Data\r | |
| 58 | }\r | |
| 59 | \r | |
| 60 | // Step 1: Confirm the ICHx SMBus is ready to perform\r | |
| 61 | // communication.\r | |
| 62 | \r | |
| 63 | If(STRT())\r | |
| 64 | {\r | |
| 65 | Return(0)\r | |
| 66 | }\r | |
| 67 | \r | |
| 68 | // Step 2: Initiate a Send Byte.\r | |
| 69 | \r | |
| 70 | Store(0,I2CE) // Ensure SMbus Mode.\r | |
| 71 | Store(0xBF,HSTS) // Clear all but INUSE_STS.\r | |
| 72 | Store(Arg0,TXSA) // Write Address in TXSA.\r | |
| 73 | Store(Arg1,HCOM) // Data in HCOM.\r | |
| 74 | \r | |
| 75 | // Set the SMBus Host control register to 0x48.\r | |
| 76 | // Bit 7: = 0 = reserved\r | |
| 77 | // Bit 6: = 1 = start\r | |
| 78 | // Bit 5: = 0 = disregard, I2C related bit\r | |
| 79 | // Bits 4:2: = 001 = Byte Protocol\r | |
| 80 | // Bit 1: = 0 = Normal Function\r | |
| 81 | // Bit 0: = 0 = Disable interrupt generation\r | |
| 82 | \r | |
| 83 | Store(0x48,HCON)\r | |
| 84 | \r | |
| 85 | // Step 3: Exit the Method correctly.\r | |
| 86 | \r | |
| 87 | If(COMP)\r | |
| 88 | {\r | |
| 89 | Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others..\r | |
| 90 | Return(1) // Return Success.\r | |
| 91 | }\r | |
| 92 | \r | |
| 93 | Return(0)\r | |
| 94 | }\r | |
| 95 | \r | |
| 96 | // SMBus Receive Byte - This function will write a single byte\r | |
| 97 | // of data to a specific Slave Device per SMBus Receive Byte\r | |
| 98 | // Protocol.\r | |
| 99 | // Arg0 = Address\r | |
| 100 | // Return: Success = Byte-Size Value\r | |
| 101 | // Failure = Word-Size Value = FFFFh.\r | |
| 102 | \r | |
| 103 | Method(SRXB,1,Serialized)\r | |
| 104 | {\r | |
| 105 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 106 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 107 | {\r | |
| 108 | , 5,\r | |
| 109 | SBAR, 11\r | |
| 110 | }\r | |
| 111 | \r | |
| 112 | // Define various SMBus IO Mapped Registers.\r | |
| 113 | \r | |
| 114 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 115 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 116 | {\r | |
| 117 | HSTS, 8, // 0 - Host Status Register\r | |
| 118 | Offset(0x02),\r | |
| 119 | HCON, 8, // 2 - Host Control\r | |
| 120 | HCOM, 8, // 3 - Host Command\r | |
| 121 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 122 | DAT0, 8, // 5 - Host Data 0\r | |
| 123 | DAT1, 8, // 6 - Host Data 1\r | |
| 124 | HBDR, 8, // 7 - Host Block Data\r | |
| 125 | PECR, 8, // 8 - Packer Error Check\r | |
| 126 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 127 | SDAT, 16, // A - Slave Data\r | |
| 128 | }\r | |
| 129 | // Step 1: Confirm the ICHx SMBus is ready to perform\r | |
| 130 | // communication.\r | |
| 131 | \r | |
| 132 | If(STRT())\r | |
| 133 | {\r | |
| 134 | Return(0xFFFF)\r | |
| 135 | }\r | |
| 136 | \r | |
| 137 | // Step 2: Initiate a Receive Byte.\r | |
| 138 | \r | |
| 139 | Store(0,I2CE) // Ensure SMbus Mode.\r | |
| 140 | Store(0xBF,HSTS) // Clear all but INUSE_STS.\r | |
| 141 | Store(Or(Arg0,1),TXSA) // Read Address in TXSA.\r | |
| 142 | \r | |
| 143 | // Set the SMBus Host control register to 0x48.\r | |
| 144 | // Bit 7: = 0 = reserved\r | |
| 145 | // Bit 6: = 1 = start\r | |
| 146 | // Bit 5: = 0 = disregard, I2C related bit\r | |
| 147 | // Bits 4:2: = 001 = Byte Protocol\r | |
| 148 | // Bit 1: = 0 = Normal Function\r | |
| 149 | // Bit 0: = 0 = Disable interrupt generation\r | |
| 150 | \r | |
| 151 | Store(0x44,HCON)\r | |
| 152 | \r | |
| 153 | // Step 3: Exit the Method correctly.\r | |
| 154 | \r | |
| 155 | If(COMP)\r | |
| 156 | {\r | |
| 157 | Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others..\r | |
| 158 | Return(DAT0) // Return Success.\r | |
| 159 | }\r | |
| 160 | \r | |
| 161 | Return(0xFFFF) // Return Failure.\r | |
| 162 | }\r | |
| 163 | \r | |
| 164 | // SMBus Write Byte - This function will write a single byte\r | |
| 165 | // of data to a specific Slave Device per SMBus Write Byte\r | |
| 166 | // Protocol.\r | |
| 167 | // Arg0 = Address\r | |
| 168 | // Arg1 = Command\r | |
| 169 | // Arg2 = Data\r | |
| 170 | // Return: Success = 1\r | |
| 171 | // Failure = 0\r | |
| 172 | \r | |
| 173 | Method(SWRB,3,Serialized)\r | |
| 174 | {\r | |
| 175 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 176 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 177 | {\r | |
| 178 | , 5,\r | |
| 179 | SBAR, 11\r | |
| 180 | }\r | |
| 181 | \r | |
| 182 | // Define various SMBus IO Mapped Registers.\r | |
| 183 | \r | |
| 184 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 185 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 186 | {\r | |
| 187 | HSTS, 8, // 0 - Host Status Register\r | |
| 188 | Offset(0x02),\r | |
| 189 | HCON, 8, // 2 - Host Control\r | |
| 190 | HCOM, 8, // 3 - Host Command\r | |
| 191 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 192 | DAT0, 8, // 5 - Host Data 0\r | |
| 193 | DAT1, 8, // 6 - Host Data 1\r | |
| 194 | HBDR, 8, // 7 - Host Block Data\r | |
| 195 | PECR, 8, // 8 - Packer Error Check\r | |
| 196 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 197 | SDAT, 16, // A - Slave Data\r | |
| 198 | }\r | |
| 199 | // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r | |
| 200 | \r | |
| 201 | If(STRT())\r | |
| 202 | {\r | |
| 203 | Return(0)\r | |
| 204 | }\r | |
| 205 | \r | |
| 206 | // Step 2: Initiate a Write Byte.\r | |
| 207 | \r | |
| 208 | Store(0,I2CE) // Ensure SMbus Mode.\r | |
| 209 | Store(0xBF,HSTS) // Clear all but INUSE_STS.\r | |
| 210 | Store(Arg0,TXSA) // Write Address in TXSA.\r | |
| 211 | Store(Arg1,HCOM) // Command in HCOM.\r | |
| 212 | Store(Arg2,DAT0) // Data in DAT0.\r | |
| 213 | \r | |
| 214 | // Set the SMBus Host control register to 0x48.\r | |
| 215 | // Bit 7: = 0 = reserved\r | |
| 216 | // Bit 6: = 1 = start\r | |
| 217 | // Bit 5: = 0 = disregard, I2C related bit\r | |
| 218 | // Bits 4:2: = 010 = Byte Data Protocol\r | |
| 219 | // Bit 1: = 0 = Normal Function\r | |
| 220 | // Bit 0: = 0 = Disable interrupt generation\r | |
| 221 | \r | |
| 222 | Store(0x48,HCON)\r | |
| 223 | \r | |
| 224 | // Step 3: Exit the Method correctly.\r | |
| 225 | \r | |
| 226 | If(COMP)\r | |
| 227 | {\r | |
| 228 | Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others..\r | |
| 229 | Return(1) // Return Success.\r | |
| 230 | }\r | |
| 231 | \r | |
| 232 | Return(0) // Return Failure.\r | |
| 233 | }\r | |
| 234 | \r | |
| 235 | // SMBus Read Byte - This function will read a single byte of data\r | |
| 236 | // from a specific slave device per SMBus Read Byte Protocol.\r | |
| 237 | // Arg0 = Address\r | |
| 238 | // Arg1 = Command\r | |
| 239 | // Return: Success = Byte-Size Value\r | |
| 240 | // Failure = Word-Size Value\r | |
| 241 | \r | |
| 242 | Method(SRDB,2,Serialized)\r | |
| 243 | {\r | |
| 244 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 245 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 246 | {\r | |
| 247 | , 5,\r | |
| 248 | SBAR, 11\r | |
| 249 | }\r | |
| 250 | \r | |
| 251 | // Define various SMBus IO Mapped Registers.\r | |
| 252 | \r | |
| 253 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 254 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 255 | {\r | |
| 256 | HSTS, 8, // 0 - Host Status Register\r | |
| 257 | Offset(0x02),\r | |
| 258 | HCON, 8, // 2 - Host Control\r | |
| 259 | HCOM, 8, // 3 - Host Command\r | |
| 260 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 261 | DAT0, 8, // 5 - Host Data 0\r | |
| 262 | DAT1, 8, // 6 - Host Data 1\r | |
| 263 | HBDR, 8, // 7 - Host Block Data\r | |
| 264 | PECR, 8, // 8 - Packer Error Check\r | |
| 265 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 266 | SDAT, 16, // A - Slave Data\r | |
| 267 | }\r | |
| 268 | // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r | |
| 269 | \r | |
| 270 | If(STRT())\r | |
| 271 | {\r | |
| 272 | Return(0xFFFF)\r | |
| 273 | }\r | |
| 274 | \r | |
| 275 | // Step 2: Initiate a Read Byte.\r | |
| 276 | \r | |
| 277 | Store(0,I2CE) // Ensure SMbus Mode.\r | |
| 278 | Store(0xBF,HSTS) // Clear all but INUSE_STS.\r | |
| 279 | Store(Or(Arg0,1),TXSA) // Read Address in TXSA.\r | |
| 280 | Store(Arg1,HCOM) // Command in HCOM.\r | |
| 281 | \r | |
| 282 | // Set the SMBus Host control register to 0x48.\r | |
| 283 | // Bit 7: = 0 = reserved\r | |
| 284 | // Bit 6: = 1 = start\r | |
| 285 | // Bit 5: = 0 = disregard, I2C related bit\r | |
| 286 | // Bits 4:2: = 010 = Byte Data Protocol\r | |
| 287 | // Bit 1: = 0 = Normal Function\r | |
| 288 | // Bit 0: = 0 = Disable interrupt generation\r | |
| 289 | \r | |
| 290 | Store(0x48,HCON)\r | |
| 291 | \r | |
| 292 | // Step 3: Exit the Method correctly.\r | |
| 293 | \r | |
| 294 | If(COMP)\r | |
| 295 | {\r | |
| 296 | Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others..\r | |
| 297 | Return(DAT0) // Return Success.\r | |
| 298 | }\r | |
| 299 | \r | |
| 300 | Return(0xFFFF) // Return Failure.\r | |
| 301 | }\r | |
| 302 | \r | |
| 303 | // SMBus Write Word - This function will write a single word\r | |
| 304 | // of data to a specific Slave Device per SMBus Write Word\r | |
| 305 | // Protocol.\r | |
| 306 | // Arg0 = Address\r | |
| 307 | // Arg1 = Command\r | |
| 308 | // Arg2 = Data (16 bits in size)\r | |
| 309 | // Return: Success = 1\r | |
| 310 | // Failure = 0\r | |
| 311 | \r | |
| 312 | Method(SWRW,3,Serialized)\r | |
| 313 | {\r | |
| 314 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 315 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 316 | {\r | |
| 317 | , 5,\r | |
| 318 | SBAR, 11\r | |
| 319 | }\r | |
| 320 | \r | |
| 321 | // Define various SMBus IO Mapped Registers.\r | |
| 322 | \r | |
| 323 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 324 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 325 | {\r | |
| 326 | HSTS, 8, // 0 - Host Status Register\r | |
| 327 | Offset(0x02),\r | |
| 328 | HCON, 8, // 2 - Host Control\r | |
| 329 | HCOM, 8, // 3 - Host Command\r | |
| 330 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 331 | DAT0, 8, // 5 - Host Data 0\r | |
| 332 | DAT1, 8, // 6 - Host Data 1\r | |
| 333 | HBDR, 8, // 7 - Host Block Data\r | |
| 334 | PECR, 8, // 8 - Packer Error Check\r | |
| 335 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 336 | SDAT, 16, // A - Slave Data\r | |
| 337 | }\r | |
| 338 | // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r | |
| 339 | \r | |
| 340 | If(STRT())\r | |
| 341 | {\r | |
| 342 | Return(0)\r | |
| 343 | }\r | |
| 344 | \r | |
| 345 | // Step 2: Initiate a Write Word.\r | |
| 346 | \r | |
| 347 | Store(0,I2CE) // Ensure SMbus Mode.\r | |
| 348 | Store(0xBF,HSTS) // Clear all but INUSE_STS.\r | |
| 349 | Store(Arg0,TXSA) // Write Address in TXSA.\r | |
| 350 | Store(Arg1,HCOM) // Command in HCOM.\r | |
| 351 | And(Arg2,0xFF,DAT1) // Low byte Data in DAT1.\r | |
| 352 | And(ShiftRight(Arg2,8),0xFF,DAT0) // High byte Data in DAT0.\r | |
| 353 | \r | |
| 354 | // Set the SMBus Host control register to 0x4C.\r | |
| 355 | // Bit 7: = 0 = reserved\r | |
| 356 | // Bit 6: = 1 = start\r | |
| 357 | // Bit 5: = 0 = disregard, I2C related bit\r | |
| 358 | // Bits 4:2: = 011 = Word Data Protocol\r | |
| 359 | // Bit 1: = 0 = Normal Function\r | |
| 360 | // Bit 0: = 0 = Disable interrupt generation\r | |
| 361 | \r | |
| 362 | Store(0x4C,HCON)\r | |
| 363 | \r | |
| 364 | // Step 3: Exit the Method correctly.\r | |
| 365 | \r | |
| 366 | If(COMP())\r | |
| 367 | {\r | |
| 368 | Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.\r | |
| 369 | Return(1) // Return Success.\r | |
| 370 | }\r | |
| 371 | \r | |
| 372 | Return(0) // Return Failure.\r | |
| 373 | }\r | |
| 374 | \r | |
| 375 | // SMBus Read Word - This function will read a single byte of data\r | |
| 376 | // from a specific slave device per SMBus Read Word Protocol.\r | |
| 377 | // Arg0 = Address\r | |
| 378 | // Arg1 = Command\r | |
| 379 | // Return: Success = Word-Size Value\r | |
| 380 | // Failure = Dword-Size Value\r | |
| 381 | \r | |
| 382 | Method(SRDW,2,Serialized)\r | |
| 383 | {\r | |
| 384 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 385 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 386 | {\r | |
| 387 | , 5,\r | |
| 388 | SBAR, 11\r | |
| 389 | }\r | |
| 390 | \r | |
| 391 | // Define various SMBus IO Mapped Registers.\r | |
| 392 | \r | |
| 393 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 394 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 395 | {\r | |
| 396 | HSTS, 8, // 0 - Host Status Register\r | |
| 397 | Offset(0x02),\r | |
| 398 | HCON, 8, // 2 - Host Control\r | |
| 399 | HCOM, 8, // 3 - Host Command\r | |
| 400 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 401 | DAT0, 8, // 5 - Host Data 0\r | |
| 402 | DAT1, 8, // 6 - Host Data 1\r | |
| 403 | HBDR, 8, // 7 - Host Block Data\r | |
| 404 | PECR, 8, // 8 - Packer Error Check\r | |
| 405 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 406 | SDAT, 16, // A - Slave Data\r | |
| 407 | }\r | |
| 408 | // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r | |
| 409 | \r | |
| 410 | If(STRT())\r | |
| 411 | {\r | |
| 412 | Return(0xFFFF)\r | |
| 413 | }\r | |
| 414 | \r | |
| 415 | // Step 2: Initiate a Read Word.\r | |
| 416 | \r | |
| 417 | Store(0,I2CE) // Ensure SMbus Mode.\r | |
| 418 | Store(0xBF,HSTS) // Clear all but INUSE_STS.\r | |
| 419 | Store(Or(Arg0,1),TXSA) // Read Address in TXSA.\r | |
| 420 | Store(Arg1,HCOM) // Command in HCOM.\r | |
| 421 | \r | |
| 422 | // Set the SMBus Host control register to 0x4C.\r | |
| 423 | // Bit 7: = 0 = reserved\r | |
| 424 | // Bit 6: = 1 = start\r | |
| 425 | // Bit 5: = 0 = disregard, I2C related bit\r | |
| 426 | // Bits 4:2: = 011 = Word Data Protocol\r | |
| 427 | // Bit 1: = 0 = Normal Function\r | |
| 428 | // Bit 0: = 0 = Disable interrupt generation\r | |
| 429 | \r | |
| 430 | Store(0x4C,HCON)\r | |
| 431 | \r | |
| 432 | // Step 3: Exit the Method correctly.\r | |
| 433 | \r | |
| 434 | If(COMP())\r | |
| 435 | {\r | |
| 436 | Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.\r | |
| 437 | Return(Or(ShiftLeft(DAT0,8),DAT1)) // Return Success.\r | |
| 438 | }\r | |
| 439 | \r | |
| 440 | Return(0xFFFFFFFF) // Return Failure.\r | |
| 441 | }\r | |
| 442 | \r | |
| 443 | // SMBus Block Write - This function will write an entire block of data\r | |
| 444 | // to a specific slave device per SMBus Block Write Protocol.\r | |
| 445 | // Arg0 = Address\r | |
| 446 | // Arg1 = Command\r | |
| 447 | // Arg2 = Buffer of Data to Write\r | |
| 448 | // Arg3 = 1 = I2C Block Write, 0 = SMBus Block Write\r | |
| 449 | // Return: Success = 1\r | |
| 450 | // Failure = 0\r | |
| 451 | \r | |
| 452 | Method(SBLW,4,Serialized)\r | |
| 453 | {\r | |
| 454 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 455 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 456 | {\r | |
| 457 | , 5,\r | |
| 458 | SBAR, 11\r | |
| 459 | }\r | |
| 460 | \r | |
| 461 | // Define various SMBus IO Mapped Registers.\r | |
| 462 | \r | |
| 463 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 464 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 465 | {\r | |
| 466 | HSTS, 8, // 0 - Host Status Register\r | |
| 467 | Offset(0x02),\r | |
| 468 | HCON, 8, // 2 - Host Control\r | |
| 469 | HCOM, 8, // 3 - Host Command\r | |
| 470 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 471 | DAT0, 8, // 5 - Host Data 0\r | |
| 472 | DAT1, 8, // 6 - Host Data 1\r | |
| 473 | HBDR, 8, // 7 - Host Block Data\r | |
| 474 | PECR, 8, // 8 - Packer Error Check\r | |
| 475 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 476 | SDAT, 16, // A - Slave Data\r | |
| 477 | }\r | |
| 478 | // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r | |
| 479 | \r | |
| 480 | If(STRT())\r | |
| 481 | {\r | |
| 482 | Return(0)\r | |
| 483 | }\r | |
| 484 | \r | |
| 485 | // Step 2: Initiate a Block Write.\r | |
| 486 | \r | |
| 487 | Store(Arg3,I2CE) // Select the proper protocol.\r | |
| 488 | Store(0xBF,HSTS) // Clear all but INUSE_STS.\r | |
| 489 | Store(Arg0,TXSA) // Write Address in TXSA.\r | |
| 490 | Store(Arg1,HCOM) // Command in HCOM.\r | |
| 491 | Store(Sizeof(Arg2),DAT0) // Count in DAT0.\r | |
| 492 | Store(0,Local1) // Init Pointer to Buffer.\r | |
| 493 | Store(DerefOf(Index(Arg2,0)),HBDR) // First Byte in HBD Register.\r | |
| 494 | \r | |
| 495 | // Set the SMBus Host control register to 0x48.\r | |
| 496 | // Bit 7: = 0 = reserved\r | |
| 497 | // Bit 6: = 1 = start\r | |
| 498 | // Bit 5: = 0 = disregard, I2C related bit\r | |
| 499 | // Bits 4:2: = 101 = Block Protocol\r | |
| 500 | // Bit 1: = 0 = Normal Function\r | |
| 501 | // Bit 0: = 0 = Disable interrupt generation\r | |
| 502 | \r | |
| 503 | Store(0x54,HCON)\r | |
| 504 | \r | |
| 505 | // Step 3: Send the entire Block of Data.\r | |
| 506 | \r | |
| 507 | While(LGreater(Sizeof(Arg2),Local1))\r | |
| 508 | {\r | |
| 509 | // Wait up to 200ms for Host Status to get set.\r | |
| 510 | \r | |
| 511 | Store(4000,Local0) // 4000 * 50us = 200ms.\r | |
| 512 | \r | |
| 513 | While(LAnd(LNot(And(HSTS,0x80)),Local0))\r | |
| 514 | {\r | |
| 515 | Decrement(Local0) // Decrement Count.\r | |
| 516 | Stall(50) // Delay = 50us.\r | |
| 517 | }\r | |
| 518 | \r | |
| 519 | If(LNot(Local0)) // Timeout?\r | |
| 520 | {\r | |
| 521 | KILL() // Yes. Kill Communication.\r | |
| 522 | Return(0) // Return failure.\r | |
| 523 | }\r | |
| 524 | \r | |
| 525 | Store(0x80,HSTS) // Clear Host Status.\r | |
| 526 | Increment(Local1) // Point to Next Byte.\r | |
| 527 | \r | |
| 528 | // Place next byte in HBDR if last byte has not been sent.\r | |
| 529 | \r | |
| 530 | If(LGreater(Sizeof(Arg2),Local1))\r | |
| 531 | {\r | |
| 532 | Store(DerefOf(Index(Arg2,Local1)),HBDR)\r | |
| 533 | }\r | |
| 534 | }\r | |
| 535 | \r | |
| 536 | // Step 4: Exit the Method correctly.\r | |
| 537 | \r | |
| 538 | If(COMP())\r | |
| 539 | {\r | |
| 540 | Or(HSTS,0xFF,HSTS) // Clear all status bits.\r | |
| 541 | Return(1) // Return Success.\r | |
| 542 | }\r | |
| 543 | \r | |
| 544 | Return(0) // Return Failure.\r | |
| 545 | }\r | |
| 546 | \r | |
| 547 | // SMBus Block Read - This function will read a block of data from\r | |
| 548 | // a specific slave device per SMBus Block Read Protocol.\r | |
| 549 | // Arg0 = Address\r | |
| 550 | // Arg1 = Command\r | |
| 551 | // Arg2 = 1 = I2C Block Write, 0 = SMBus Block Write\r | |
| 552 | // Return: Success = Data Buffer (First Byte = length)\r | |
| 553 | // Failure = 0\r | |
| 554 | \r | |
| 555 | Method(SBLR,3,Serialized)\r | |
| 556 | {\r | |
| 557 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 558 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 559 | {\r | |
| 560 | , 5,\r | |
| 561 | SBAR, 11\r | |
| 562 | }\r | |
| 563 | \r | |
| 564 | // Define various SMBus IO Mapped Registers.\r | |
| 565 | \r | |
| 566 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 567 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 568 | {\r | |
| 569 | HSTS, 8, // 0 - Host Status Register\r | |
| 570 | Offset(0x02),\r | |
| 571 | HCON, 8, // 2 - Host Control\r | |
| 572 | HCOM, 8, // 3 - Host Command\r | |
| 573 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 574 | DAT0, 8, // 5 - Host Data 0\r | |
| 575 | DAT1, 8, // 6 - Host Data 1\r | |
| 576 | HBDR, 8, // 7 - Host Block Data\r | |
| 577 | PECR, 8, // 8 - Packer Error Check\r | |
| 578 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 579 | SDAT, 16, // A - Slave Data\r | |
| 580 | }\r | |
| 581 | Name(TBUF, Buffer(256) {})\r | |
| 582 | \r | |
| 583 | // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r | |
| 584 | \r | |
| 585 | If(STRT())\r | |
| 586 | {\r | |
| 587 | Return(0)\r | |
| 588 | }\r | |
| 589 | \r | |
| 590 | // Step 2: Initiate a Block Read.\r | |
| 591 | \r | |
| 592 | Store(Arg2,I2CE) // Select the proper protocol.\r | |
| 593 | Store(0xBF,HSTS) // Clear all but INUSE_STS.\r | |
| 594 | Store(Or(Arg0,1),TXSA) // Read Address in TXSA.\r | |
| 595 | Store(Arg1,HCOM) // Command in HCOM.\r | |
| 596 | \r | |
| 597 | // Set the SMBus Host control register to 0x48.\r | |
| 598 | // Bit 7: = 0 = reserved\r | |
| 599 | // Bit 6: = 1 = start\r | |
| 600 | // Bit 5: = 0 = disregard, I2C related bit\r | |
| 601 | // Bits 4:2: = 101 = Block Protocol\r | |
| 602 | // Bit 1: = 0 = Normal Function\r | |
| 603 | // Bit 0: = 0 = Disable interrupt generation\r | |
| 604 | \r | |
| 605 | Store(0x54,HCON)\r | |
| 606 | \r | |
| 607 | // Step 3: Wait up to 200ms to get the Data Count.\r | |
| 608 | \r | |
| 609 | Store(4000,Local0) // 4000 * 50us = 200ms.\r | |
| 610 | \r | |
| 611 | While(LAnd(LNot(And(HSTS,0x80)),Local0))\r | |
| 612 | {\r | |
| 613 | Decrement(Local0) // Decrement Count.\r | |
| 614 | Stall(50) // Delay = 50us.\r | |
| 615 | }\r | |
| 616 | \r | |
| 617 | If(LNot(Local0)) // Timeout?\r | |
| 618 | {\r | |
| 619 | KILL() // Yes. Kill Communication.\r | |
| 620 | Return(0) // Return failure.\r | |
| 621 | }\r | |
| 622 | \r | |
| 623 | Store(DAT0,Index(TBUF,0)) // Get the Data Count.\r | |
| 624 | Store(0x80,HSTS) // Clear Host Status.\r | |
| 625 | Store(1,Local1) // Local1 = Buffer Pointer.\r | |
| 626 | \r | |
| 627 | // Step 4: Get the Block Data and store it.\r | |
| 628 | \r | |
| 629 | While(LLess(Local1,DerefOf(Index(TBUF,0))))\r | |
| 630 | {\r | |
| 631 | // Wait up to 200ms for Host Status to get set.\r | |
| 632 | \r | |
| 633 | Store(4000,Local0) // 4000 * 50us = 200ms.\r | |
| 634 | \r | |
| 635 | While(LAnd(LNot(And(HSTS,0x80)),Local0))\r | |
| 636 | {\r | |
| 637 | Decrement(Local0) // Decrement Count.\r | |
| 638 | Stall(50) // Delay = 50us.\r | |
| 639 | }\r | |
| 640 | \r | |
| 641 | If(LNot(Local0)) // Timeout?\r | |
| 642 | {\r | |
| 643 | KILL() // Yes. Kill Communication.\r | |
| 644 | Return(0) // Return failure.\r | |
| 645 | }\r | |
| 646 | \r | |
| 647 | Store(HBDR,Index(TBUF,Local1)) // Place into Buffer.\r | |
| 648 | Store(0x80,HSTS) // Clear Host Status.\r | |
| 649 | Increment(Local1)\r | |
| 650 | }\r | |
| 651 | \r | |
| 652 | // Step 5: Exit the Method correctly.\r | |
| 653 | \r | |
| 654 | If(COMP())\r | |
| 655 | {\r | |
| 656 | Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.\r | |
| 657 | Return(TBUF) // Return Success.\r | |
| 658 | }\r | |
| 659 | \r | |
| 660 | Return(0) // Return Failure.\r | |
| 661 | }\r | |
| 662 | \r | |
| 663 | \r | |
| 664 | // SMBus Start Check\r | |
| 665 | // Return: Success = 0\r | |
| 666 | // Failure = 1\r | |
| 667 | \r | |
| 668 | Method(STRT,0,Serialized)\r | |
| 669 | {\r | |
| 670 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 671 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 672 | {\r | |
| 673 | , 5,\r | |
| 674 | SBAR, 11\r | |
| 675 | }\r | |
| 676 | \r | |
| 677 | // Define various SMBus IO Mapped Registers.\r | |
| 678 | \r | |
| 679 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 680 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 681 | {\r | |
| 682 | HSTS, 8, // 0 - Host Status Register\r | |
| 683 | Offset(0x02),\r | |
| 684 | HCON, 8, // 2 - Host Control\r | |
| 685 | HCOM, 8, // 3 - Host Command\r | |
| 686 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 687 | DAT0, 8, // 5 - Host Data 0\r | |
| 688 | DAT1, 8, // 6 - Host Data 1\r | |
| 689 | HBDR, 8, // 7 - Host Block Data\r | |
| 690 | PECR, 8, // 8 - Packer Error Check\r | |
| 691 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 692 | SDAT, 16, // A - Slave Data\r | |
| 693 | }\r | |
| 694 | // Wait up to 200ms to confirm the SMBus Semaphore has been\r | |
| 695 | // released (In Use Status = 0). Note that the Sleep time may take\r | |
| 696 | // longer as the This function will yield the Processor such that it\r | |
| 697 | // may perform different tasks during the delay.\r | |
| 698 | \r | |
| 699 | Store(200,Local0) // 200 * 1ms = 200ms.\r | |
| 700 | \r | |
| 701 | While(Local0)\r | |
| 702 | {\r | |
| 703 | If(And(HSTS,0x40)) // In Use Set?\r | |
| 704 | {\r | |
| 705 | Decrement(Local0) // Yes. Decrement Count.\r | |
| 706 | Sleep(1) // Delay = 1ms.\r | |
| 707 | If(LEqual(Local0,0)) // Count = 0?\r | |
| 708 | {\r | |
| 709 | Return(1) // Return failure.\r | |
| 710 | }\r | |
| 711 | }\r | |
| 712 | Else\r | |
| 713 | {\r | |
| 714 | Store(0,Local0) // In Use Clear. Continue.\r | |
| 715 | }\r | |
| 716 | }\r | |
| 717 | \r | |
| 718 | // In Use Status = 0 during last read, which will make subsequent\r | |
| 719 | // reads return In Use Status = 1 until software clears it. All\r | |
| 720 | // software using ICHx SMBus should check this bit before initiating\r | |
| 721 | // any SMBus communication.\r | |
| 722 | \r | |
| 723 | // Wait up to 200ms to confirm the Host Interface is\r | |
| 724 | // not processing a command.\r | |
| 725 | \r | |
| 726 | Store(4000,Local0) // 4000 * 50us = 200ms.\r | |
| 727 | \r | |
| 728 | While(Local0)\r | |
| 729 | {\r | |
| 730 | If(And(HSTS,0x01)) // Host Busy Set?\r | |
| 731 | {\r | |
| 732 | Decrement(Local0) // Decrement Count.\r | |
| 733 | Stall(50) // Delay = 50us.\r | |
| 734 | If(LEqual(Local0,0)) // Count = 0?\r | |
| 735 | {\r | |
| 736 | KILL() // Yes. Kill Communication.\r | |
| 737 | }\r | |
| 738 | }\r | |
| 739 | Else\r | |
| 740 | {\r | |
| 741 | Return(0)\r | |
| 742 | }\r | |
| 743 | }\r | |
| 744 | \r | |
| 745 | Return(1) // Timeout. Return failure.\r | |
| 746 | }\r | |
| 747 | \r | |
| 748 | // SMBus Completion Check\r | |
| 749 | // Return: Success = 1\r | |
| 750 | // Failure = 0\r | |
| 751 | \r | |
| 752 | Method(COMP,0,Serialized)\r | |
| 753 | {\r | |
| 754 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 755 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 756 | {\r | |
| 757 | , 5,\r | |
| 758 | SBAR, 11\r | |
| 759 | }\r | |
| 760 | \r | |
| 761 | // Define various SMBus IO Mapped Registers.\r | |
| 762 | \r | |
| 763 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 764 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 765 | {\r | |
| 766 | HSTS, 8, // 0 - Host Status Register\r | |
| 767 | Offset(0x02),\r | |
| 768 | HCON, 8, // 2 - Host Control\r | |
| 769 | HCOM, 8, // 3 - Host Command\r | |
| 770 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 771 | DAT0, 8, // 5 - Host Data 0\r | |
| 772 | DAT1, 8, // 6 - Host Data 1\r | |
| 773 | HBDR, 8, // 7 - Host Block Data\r | |
| 774 | PECR, 8, // 8 - Packer Error Check\r | |
| 775 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 776 | SDAT, 16, // A - Slave Data\r | |
| 777 | }\r | |
| 778 | // Wait for up to 200ms for the Completion Command\r | |
| 779 | // Status to get set.\r | |
| 780 | \r | |
| 781 | Store(4000,Local0) // 4000 * 50us = 200ms.\r | |
| 782 | \r | |
| 783 | While(Local0)\r | |
| 784 | {\r | |
| 785 | If(And(HSTS,0x02)) // Completion Status Set?\r | |
| 786 | {\r | |
| 787 | Return(1) // Yes. We are done.\r | |
| 788 | }\r | |
| 789 | Else\r | |
| 790 | {\r | |
| 791 | Decrement(Local0) // Decrement Count.\r | |
| 792 | Stall(50) // Delay 50us.\r | |
| 793 | If(LEqual(Local0,0)) // Count = 0?\r | |
| 794 | {\r | |
| 795 | KILL() // Yes. Kill Communication.\r | |
| 796 | }\r | |
| 797 | }\r | |
| 798 | }\r | |
| 799 | \r | |
| 800 | Return(0) // Timeout. Return Failure.\r | |
| 801 | }\r | |
| 802 | \r | |
| 803 | // SMBus Kill Command\r | |
| 804 | \r | |
| 805 | Method(KILL,0,Serialized)\r | |
| 806 | {\r | |
| 807 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 808 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 809 | {\r | |
| 810 | , 5,\r | |
| 811 | SBAR, 11\r | |
| 812 | }\r | |
| 813 | \r | |
| 814 | // Define various SMBus IO Mapped Registers.\r | |
| 815 | \r | |
| 816 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 817 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 818 | {\r | |
| 819 | HSTS, 8, // 0 - Host Status Register\r | |
| 820 | Offset(0x02),\r | |
| 821 | HCON, 8, // 2 - Host Control\r | |
| 822 | HCOM, 8, // 3 - Host Command\r | |
| 823 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 824 | DAT0, 8, // 5 - Host Data 0\r | |
| 825 | DAT1, 8, // 6 - Host Data 1\r | |
| 826 | HBDR, 8, // 7 - Host Block Data\r | |
| 827 | PECR, 8, // 8 - Packer Error Check\r | |
| 828 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 829 | SDAT, 16, // A - Slave Data\r | |
| 830 | }\r | |
| 831 | Or(HCON,0x02,HCON) // Yes. Send Kill command.\r | |
| 832 | Or(HSTS,0xFF,HSTS) // Clear all status.\r | |
| 833 | }\r |