projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /**************************************************************************;\r |
| 2 | ;* *;\r | |
| 3 | ;* *;\r | |
| 4 | ;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r | |
| 5 | ;* Family of Customer Reference Boards. *;\r | |
| 6 | ;* *;\r | |
| 7 | ;* *;\r | |
| 8 | ;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;\r | |
| 9 | ;\r | |
| 7ede8060 | 10 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
11 | ;\r |
| 12 | ;* *;\r | |
| 13 | ;* *;\r | |
| 14 | ;**************************************************************************/\r | |
| 15 | DefinitionBlock (\r | |
| 16 | "Rtd3.aml",\r | |
| 17 | "SSDT",\r | |
| 18 | 1,\r | |
| 19 | "AcpiRef",\r | |
| 20 | "Msg_Rtd3",\r | |
| 21 | 0x1000\r | |
| 22 | )\r | |
| 23 | {\r | |
| 24 | External(RTD3) //flag if RTD3 is enabled\r | |
| 25 | \r | |
| 26 | If(LEqual(RTD3,1))\r | |
| 27 | {\r | |
| 28 | Scope (\_SB)\r | |
| 29 | {\r | |
| 30 | Name(OSCI, 0) // \_SB._OSC DWORD2 input\r | |
| 31 | Name(OSCO, 0) // \_SB._OSC DWORD2 output\r | |
| 32 | \r | |
| 33 | //Arg0 -- A buffer containing UUID\r | |
| 34 | //Arg1 -- An Interger containing a Revision ID of the buffer format\r | |
| 35 | //Arg2 -- An interger containing a count of entries in Arg3\r | |
| 36 | //Arg3 -- A buffer containing a list of DWORD capacities\r | |
| 37 | Method(_OSC, 4, NotSerialized)\r | |
| 38 | {\r | |
| 39 | // Check for proper UUID\r | |
| 40 | If(LEqual(Arg0, ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")))\r | |
| 41 | {\r | |
| 42 | CreateDWordField(Arg3,0,CDW1) //bit1,2 is always clear\r | |
| 43 | CreateDWordField(Arg3,4,CDW2) //Table 6-147 from ACPI spec\r | |
| 44 | \r | |
| 45 | Store(CDW2, OSCI) // Save DWord2\r | |
| 46 | Or(OSCI, 0x4, OSCO) // Only allow _PR3 support\r | |
| 47 | \r | |
| 48 | If(LNotEqual(Arg1,One))\r | |
| 49 | {\r | |
| 50 | Or(CDW1,0x08,CDW1) // Unknown revision\r | |
| 51 | }\r | |
| 52 | \r | |
| 53 | If(LNotEqual(OSCI, OSCO))\r | |
| 54 | {\r | |
| 55 | Or(CDW1,0x10,CDW1) // Capabilities bits were masked\r | |
| 56 | }\r | |
| 57 | \r | |
| 58 | Store(OSCO, CDW2) // Replace DWord2\r | |
| 59 | Return(Arg3)\r | |
| 60 | } Else\r | |
| 61 | {\r | |
| 62 | Or(CDW1,4,CDW1) // Unrecognized UUID\r | |
| 63 | Return(Arg3)\r | |
| 64 | }\r | |
| 65 | }// End _OSC\r | |
| 66 | }\r | |
| 67 | }//end of RTD3 condition\r | |
| 68 | \r | |
| 69 | \r | |
| 70 | //USB RTD3 code\r | |
| 71 | If(LEqual(RTD3,1))\r | |
| 72 | {\r | |
| 73 | Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR13)\r | |
| 74 | {\r | |
| 75 | Name(_PR0, Package() {\PR34})\r | |
| 76 | Name(_PR3, Package() {\PR34})\r | |
| 77 | \r | |
| 78 | Method(_S0W, 0)\r | |
| 79 | {\r | |
| 80 | If(And(\_SB.OSCO, 0x04)) // PMEs can be genrated from D3cold\r | |
| 81 | {\r | |
| 82 | Return(4) // OS comprehends D3cold, as described via \_SB._OSC\r | |
| 83 | } Else\r | |
| 84 | {\r | |
| 85 | Return(3)\r | |
| 86 | }\r | |
| 87 | } // End _S0W\r | |
| 88 | }\r | |
| 89 | \r | |
| 90 | Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR14)\r | |
| 91 | {\r | |
| 92 | Name(_PR0, Package() {\PR34})\r | |
| 93 | Name(_PR3, Package() {\PR34})\r | |
| 94 | \r | |
| 95 | Method(_S0W, 0)\r | |
| 96 | {\r | |
| 97 | If(And(\_SB.OSCO, 0x04))\r | |
| 98 | {\r | |
| 99 | Return(4)\r | |
| 100 | } Else\r | |
| 101 | {\r | |
| 102 | Return(3)\r | |
| 103 | }\r | |
| 104 | } // End _S0W\r | |
| 105 | }\r | |
| 106 | \r | |
| 107 | \r | |
| 108 | Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR15)\r | |
| 109 | {\r | |
| 110 | Name(_PR0, Package() {\PR56})\r | |
| 111 | Name(_PR3, Package() {\PR56})\r | |
| 112 | \r | |
| 113 | Method(_S0W, 0)\r | |
| 114 | {\r | |
| 115 | If(And(\_SB.OSCO, 0x04))\r | |
| 116 | {\r | |
| 117 | Return(4)\r | |
| 118 | } Else\r | |
| 119 | {\r | |
| 120 | Return(3)\r | |
| 121 | }\r | |
| 122 | } // End _S0W\r | |
| 123 | }\r | |
| 124 | \r | |
| 125 | Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR16)\r | |
| 126 | {\r | |
| 127 | Name(_PR0, Package() {\PR56})\r | |
| 128 | Name(_PR3, Package() {\PR56})\r | |
| 129 | \r | |
| 130 | Method(_S0W, 0)\r | |
| 131 | {\r | |
| 132 | If(And(\_SB.OSCO, 0x04))\r | |
| 133 | {\r | |
| 134 | Return(4)\r | |
| 135 | } Else\r | |
| 136 | {\r | |
| 137 | Return(3)\r | |
| 138 | }\r | |
| 139 | } // End _S0W\r | |
| 140 | }\r | |
| 141 | \r | |
| 142 | Scope(\_SB.PCI0.XHC1) // XHCI host only controller\r | |
| 143 | {\r | |
| 144 | \r | |
| 145 | Method(_PS0,0,Serialized) // set device into D0 state\r | |
| 146 | {\r | |
| 147 | }\r | |
| 148 | \r | |
| 149 | Method(_PS3,0,Serialized) // place device into D3H state\r | |
| 150 | {\r | |
| 151 | //write to PMCSR\r | |
| 152 | }\r | |
| 153 | \r | |
| 154 | Method(_DSW, 3,Serialized) // enable or disable the device’s ability to wake a sleeping system.\r | |
| 155 | {\r | |
| 156 | }\r | |
| 157 | }\r | |
| 158 | \r | |
| 159 | Scope(\_SB.PCI0.XHC1.RHUB.HS01)\r | |
| 160 | {\r | |
| 161 | \r | |
| 162 | }\r | |
| 163 | \r | |
| 164 | Scope(\_SB.PCI0.XHC1.RHUB.SSP1)\r | |
| 165 | {\r | |
| 166 | \r | |
| 167 | }\r | |
| 168 | \r | |
| 169 | Scope(\_SB.PCI0.XHC2) // OTG\r | |
| 170 | {\r | |
| 171 | \r | |
| 172 | Method(_PS0,0,Serialized) // set device into D0 state\r | |
| 173 | {\r | |
| 174 | }\r | |
| 175 | \r | |
| 176 | Method(_PS3,0,Serialized) // place device into D3H state\r | |
| 177 | {\r | |
| 178 | //write to PMCSR\r | |
| 179 | }\r | |
| 180 | \r | |
| 181 | Method(_DSW, 3,Serialized) // enable or disable the device’s ability to wake a sleeping system.\r | |
| 182 | {\r | |
| 183 | }\r | |
| 184 | }\r | |
| 185 | \r | |
| 186 | Scope(\_SB.PCI0.XHC2.RHUB.HS01)\r | |
| 187 | {\r | |
| 188 | \r | |
| 189 | }\r | |
| 190 | \r | |
| 191 | Scope(\_SB.PCI0.XHC2.RHUB.SSP1)\r | |
| 192 | {\r | |
| 193 | \r | |
| 194 | }\r | |
| 195 | } //If(LEqual(RTD3,1)) USB\r | |
| 196 | \r | |
| 197 | }//end of SSDT\r |