projects / mirror_edk2.git / blame
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|---|---|---|
| 3cbfba02 DW |
1 | /** \r |
| 2 | Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>\r | |
| 3 | This program and the accompanying materials\r | |
| 4 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 5 | which accompanies this distribution. The full text of the license may be found at\r | |
| 6 | http://opensource.org/licenses/bsd-license.php\r | |
| 7 | \r | |
| 8 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 9 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 10 | \r | |
| 11 | **/\r | |
| 12 | /*++\r | |
| 13 | \r | |
| 14 | Module Name:\r | |
| 15 | \r | |
| 16 | PpmPlatformPolicy.h\r | |
| 17 | \r | |
| 18 | Abstract:\r | |
| 19 | \r | |
| 20 | Interface definition details between PPM and platform drivers during DXE phase.\r | |
| 21 | \r | |
| 22 | --*/\r | |
| 23 | #ifndef _PPM_PLATFORM_POLICY_H_\r | |
| 24 | #define _PPM_PLATFORM_POLICY_H_\r | |
| 25 | \r | |
| 26 | //\r | |
| 27 | // PPM policy provided by platform for DXE phase {DDABFEAC-EF63-452c-8F39-ED7FAED8265E}\r | |
| 28 | //\r | |
| 29 | #define PPM_PLATFORM_POLICY_PROTOCOL_GUID \\r | |
| 30 | {0xddabfeac, 0xef63, 0x452c, 0x8f, 0x39, 0xed, 0x7f, 0xae, 0xd8, 0x26, 0x5e}\r | |
| 31 | \r | |
| 32 | //\r | |
| 33 | // Extern the GUID for protocol users.\r | |
| 34 | //\r | |
| 35 | extern EFI_GUID gPpmPlatformPolicyProtocolGuid;\r | |
| 36 | \r | |
| 37 | //\r | |
| 38 | // Forward reference for ANSI C compatibility\r | |
| 39 | //\r | |
| 40 | typedef struct _PPM_PLATFORM_POLICY_PROTOCOL PPM_PLATFORM_POLICY_PROTOCOL;\r | |
| 41 | \r | |
| 42 | //\r | |
| 43 | // Protocol revision number\r | |
| 44 | // Any backwards compatible changes to this protocol will result in an update in the revision number\r | |
| 45 | // Major changes will require publication of a new protocol\r | |
| 46 | //\r | |
| 47 | // Revision 1: Original version\r | |
| 48 | // Revision 2: Added T-states field to the PPM_FUNCTION_ENABLES structure, Renamed unused fields - CxPopUpEnable, CxPopDownEnable, FastC4ExitEnable\r | |
| 49 | // Revision 3: Extended VidCpuid to 32 bits for extended CPUID support (Penryn)\r | |
| 50 | // Revision 4: Added support for extended C6 residency enabling\r | |
| 51 | //\r | |
| 52 | #define PPM_PLATFORM_POLICY_PROTOCOL_REVISION 1\r | |
| 53 | #define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_2 2\r | |
| 54 | #define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_3 3\r | |
| 55 | #define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_4 4\r | |
| 56 | \r | |
| 57 | //\r | |
| 58 | // Define maximum number of custom VID states supported\r | |
| 59 | //\r | |
| 60 | #ifndef MAX_CUSTOM_VID_TABLE_STATES\r | |
| 61 | #define MAX_CUSTOM_VID_TABLE_STATES 6\r | |
| 62 | #endif\r | |
| 63 | //\r | |
| 64 | // Custom VID table\r | |
| 65 | //\r | |
| 66 | typedef struct {\r | |
| 67 | UINT8 VidNumber;\r | |
| 68 | UINT32 VidCpuid;\r | |
| 69 | UINT16 VidMaxRatio;\r | |
| 70 | UINT16 VidMaxVid;\r | |
| 71 | UINT16 StateRatio[MAX_CUSTOM_VID_TABLE_STATES];\r | |
| 72 | UINT16 StateVid[MAX_CUSTOM_VID_TABLE_STATES];\r | |
| 73 | } PPM_CUSTOM_VID_TABLE;\r | |
| 74 | \r | |
| 75 | //\r | |
| 76 | // PPM functional enables\r | |
| 77 | //\r | |
| 78 | typedef struct {\r | |
| 79 | UINT8 EnableGv :1; // 0: Disabled; 1: Enabled\r | |
| 80 | UINT8 EnableCx :1;\r | |
| 81 | UINT8 EnableCxe :1;\r | |
| 82 | UINT8 EnableC4 :1;\r | |
| 83 | UINT8 EnableC6 :1;\r | |
| 84 | UINT8 EnableC7 :1;\r | |
| 85 | UINT8 EnableTm :1;\r | |
| 86 | UINT8 Reserve00 :1;\r | |
| 87 | UINT8 Reserve01 :1;\r | |
| 88 | UINT8 EnableTurboMode :1;\r | |
| 89 | UINT8 PowerLimit2 :1;\r | |
| 90 | UINT8 EnableProcHot :1;\r | |
| 91 | UINT8 Reserve02 :1;\r | |
| 92 | UINT8 EnableCMP :1;\r | |
| 93 | UINT8 TStatesEnable :1;\r | |
| 94 | UINT8 Reserve03 :1;\r | |
| 95 | UINT8 Reserve04 ;\r | |
| 96 | \r | |
| 97 | } PPM_FUNCTION_ENABLES;\r | |
| 98 | \r | |
| 99 | \r | |
| 100 | //\r | |
| 101 | // PPM Turbo settings\r | |
| 102 | //\r | |
| 103 | typedef struct _PPM_TURBO_SETTINGS {\r | |
| 104 | UINT16 PowerLimit1;\r | |
| 105 | UINT32 PowerLimit1Time;\r | |
| 106 | UINT16 PowerLimit2;\r | |
| 107 | UINT8 TurboPowerLimitLock;\r | |
| 108 | } PPM_TURBO_SETTINGS;\r | |
| 109 | \r | |
| 110 | //\r | |
| 111 | // Platform Policy\r | |
| 112 | //\r | |
| 113 | typedef struct _PPM_PLATFORM_POLICY_PROTOCOL {\r | |
| 114 | UINT8 Revision;\r | |
| 115 | PPM_FUNCTION_ENABLES FunctionEnables;\r | |
| 116 | PPM_CUSTOM_VID_TABLE CustomVidTable;\r | |
| 117 | PPM_TURBO_SETTINGS TurboSettings;\r | |
| 118 | \r | |
| 119 | UINT8 Reserve00;\r | |
| 120 | UINT8 Reserve01;\r | |
| 121 | UINT8 Reserve02;\r | |
| 122 | UINT8 Reserve03;\r | |
| 123 | UINT8 Reserve04;\r | |
| 124 | UINT8 Reserve05;\r | |
| 125 | UINT8 Reserve06;\r | |
| 126 | \r | |
| 127 | UINT8 S3RestoreMsrSwSmiNumber;\r | |
| 128 | UINT8 Reserve07;\r | |
| 129 | UINT32 Reserve08;\r | |
| 130 | UINT8 Reserve09;\r | |
| 131 | //\r | |
| 132 | // Primary and Secondary Plane Current Limits\r | |
| 133 | //\r | |
| 134 | UINT16 Reserve10;\r | |
| 135 | UINT8 Reserve11;\r | |
| 136 | } PPM_PLATFORM_POLICY_PROTOCOL;\r | |
| 137 | \r | |
| 138 | #endif\r |