projects / mirror_edk2.git / blame
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| 3cbfba02 DW |
1 | /*-----------------------------------------------------------------------------\r |
| 2 | \r | |
| 3 | \r | |
| 4 | Intel Silvermont Processor Power Management BIOS Reference Code\r | |
| 5 | \r | |
| 6 | Copyright (c) 2006 - 2014, Intel Corporation\r | |
| 7 | \r | |
| 7ede8060 | 8 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
9 | \r |
| 10 | \r | |
| 11 | Filename: CPUPM.ASL\r | |
| 12 | \r | |
| 13 | Revision: Refer to Readme\r | |
| 14 | \r | |
| 15 | Date: Refer to Readme\r | |
| 16 | -------------------------------------------------------------------------------\r | |
| 17 | \r | |
| 18 | This Processor Power Management BIOS Source Code is furnished under license\r | |
| 19 | and may only be used or copied in accordance with the terms of the license.\r | |
| 20 | The information in this document is furnished for informational use only, is\r | |
| 21 | subject to change without notice, and should not be construed as a commitment\r | |
| 22 | by Intel Corporation. Intel Corporation assumes no responsibility or liability\r | |
| 23 | for any errors or inaccuracies that may appear in this document or any\r | |
| 24 | software that may be provided in association with this document.\r | |
| 25 | \r | |
| 26 | Except as permitted by such license, no part of this document may be\r | |
| 27 | reproduced, stored in a retrieval system, or transmitted in any form or by\r | |
| 28 | any means without the express written consent of Intel Corporation.\r | |
| 29 | \r | |
| 30 | WARNING: You are authorized and licensed to install and use this BIOS code\r | |
| 31 | ONLY on an IST PC. This utility may damage any system that does not\r | |
| 32 | meet these requirements.\r | |
| 33 | \r | |
| 34 | An IST PC is a computer which\r | |
| 35 | (1) Is capable of seamlessly and automatically transitioning among\r | |
| 36 | multiple performance states (potentially operating at different\r | |
| 37 | efficiency ratings) based upon power source changes, END user\r | |
| 38 | preference, processor performance demand, and thermal conditions; and\r | |
| 39 | (2) Includes an Intel Pentium II processors, Intel Pentium III\r | |
| 40 | processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r | |
| 41 | Processor-M, Intel Pentium M Processor, or any other future Intel\r | |
| 42 | processors that incorporates the capability to transition between\r | |
| 43 | different performance states by altering some, or any combination of,\r | |
| 44 | the following processor attributes: core voltage, core frequency, bus\r | |
| 45 | frequency, number of processor cores available, or any other attribute\r | |
| 46 | that changes the efficiency (instructions/unit time-power) at which the\r | |
| 47 | processor operates.\r | |
| 48 | -------------------------------------------------------------------------------\r | |
| 49 | \r | |
| 50 | NOTES:\r | |
| 51 | (1) <TODO> - Except for the SSDT package, the objects in this ASL code\r | |
| 52 | may be moved to the DSDT. It is kept separate in this reference package\r | |
| 53 | for ease of distribution only.\r | |
| 54 | ------------------------------------------------------------------------------*/\r | |
| 55 | \r | |
| 56 | DefinitionBlock (\r | |
| 57 | "CPUPM.aml",\r | |
| 58 | "SSDT",\r | |
| 59 | 0x01,\r | |
| 60 | "PmRef",\r | |
| 61 | "CpuPm",\r | |
| 62 | 0x3000\r | |
| 63 | )\r | |
| 64 | {\r | |
| 65 | External(\_PR.CPU0, DeviceObj)\r | |
| 66 | External(\_PR.CPU1, DeviceObj)\r | |
| 67 | External(\_PR.CPU2, DeviceObj)\r | |
| 68 | External(\_PR.CPU3, DeviceObj)\r | |
| 69 | External(SMIF)\r | |
| 70 | \r | |
| 71 | Scope(\)\r | |
| 72 | {\r | |
| 73 | \r | |
| 74 | // Package of pointers to SSDT's\r | |
| 75 | //\r | |
| 76 | // First column is SSDT name, used for debug only.\r | |
| 77 | // (First column must be EXACTLY eight characters.)\r | |
| 78 | // Second column is physical address.\r | |
| 79 | // Third column is table length.\r | |
| 80 | //\r | |
| 81 | // IF modifying this file, see warnings listed in ppminit.asm.\r | |
| 82 | //\r | |
| 83 | Name(SSDT,Package()\r | |
| 84 | {\r | |
| 85 | "CPU0IST ", 0x80000000, 0x80000000,\r | |
| 86 | "APIST ", 0x80000000, 0x80000000,\r | |
| 87 | "CPU0CST ", 0x80000000, 0x80000000,\r | |
| 88 | "APCST ", 0x80000000, 0x80000000\r | |
| 89 | })\r | |
| 90 | \r | |
| 91 | //\r | |
| 92 | // Note: See PpmBiosInit in PPMINIT.ASM for a definition of\r | |
| 93 | // the PpmFlags mirrored in CFGD.\r | |
| 94 | //\r | |
| 95 | Name(CFGD, 0x80000000)\r | |
| 96 | \r | |
| 97 | Name(\PDC0,0x80000000) // CPU0 _PDC Flags.\r | |
| 98 | Name(\PDC1,0x80000000) // CPU1 _PDC Flags.\r | |
| 99 | Name(\PDC2,0x80000000) // CPU2 _PDC Flags.\r | |
| 100 | Name(\PDC3,0x80000000) // CPU3 _PDC Flags.\r | |
| 101 | Name(\SDTL,0x00) // Loaded SSDT Flags.\r | |
| 102 | }\r | |
| 103 | \r | |
| 104 | Scope(\_PR.CPU0)\r | |
| 105 | {\r | |
| 106 | //\r | |
| 107 | // Define handles for opregions (used by load.)\r | |
| 108 | //\r | |
| 109 | Name(HI0,0) // Handle to CPU0IST\r | |
| 110 | Name(HC0,0) // Handle to CPU0CST\r | |
| 111 | \r | |
| 112 | Method(_PDC,1)\r | |
| 113 | {\r | |
| 114 | //\r | |
| 115 | // Check and extract the _PDC information.\r | |
| 116 | //\r | |
| 117 | Store(CPDC(Arg0), Local0)\r | |
| 118 | //\r | |
| 119 | // Save the capability information and load tables as needed.\r | |
| 120 | //\r | |
| 121 | GCAP(Local0)\r | |
| 122 | //\r | |
| 123 | // Return status.\r | |
| 124 | //\r | |
| 125 | //Return (Local0)\r | |
| 126 | }\r | |
| 127 | \r | |
| 128 | Method(_OSC, 4)\r | |
| 129 | {\r | |
| 130 | //\r | |
| 131 | // Check and extract the _OSC information.\r | |
| 132 | //\r | |
| 133 | Store(COSC(Arg0, Arg1, Arg2, Arg3), Local0)\r | |
| 134 | //\r | |
| 135 | // Save the capability information and load tables as needed.\r | |
| 136 | //\r | |
| 137 | GCAP(Local0)\r | |
| 138 | //\r | |
| 139 | // Return status.\r | |
| 140 | //\r | |
| 141 | Return (Local0)\r | |
| 142 | }\r | |
| 143 | \r | |
| 144 | //\r | |
| 145 | // Implement a generic Method to check _PDC information which may be called\r | |
| 146 | // by any of the processor scopes. (The use of _PDC is deprecated in ACPI 3.\r | |
| 147 | // in favor of _OSC. However, for backwards compatibility, _PDC may be\r | |
| 148 | // implemented using _OSC as follows:)\r | |
| 149 | //\r | |
| 150 | Method(CPDC,1)\r | |
| 151 | {\r | |
| 152 | CreateDwordField (Arg0, 0, REVS)\r | |
| 153 | CreateDwordField (Arg0, 4, SIZE)\r | |
| 154 | \r | |
| 155 | //\r | |
| 156 | // Local0 = Number of bytes for Arg0\r | |
| 157 | //\r | |
| 158 | Store (SizeOf (Arg0), Local0)\r | |
| 159 | \r | |
| 160 | //\r | |
| 161 | // Local1 = Number of Capabilities bytes in Arg0\r | |
| 162 | //\r | |
| 163 | Store (Subtract (Local0, 8), Local1)\r | |
| 164 | \r | |
| 165 | //\r | |
| 166 | // TEMP = Temporary field holding Capability DWORDs\r | |
| 167 | //\r | |
| 168 | CreateField (Arg0, 64, Multiply (Local1, 8), TEMP)\r | |
| 169 | \r | |
| 170 | //\r | |
| 171 | // Create the Status (STAT) buffer with the first DWORD = 0\r | |
| 172 | // This is required as per ACPI 3.0 Spec which says the\r | |
| 173 | // first DWORD is used to return errors defined by _OSC.\r | |
| 174 | //\r | |
| 175 | Name (STS0, Buffer () {0x00, 0x00, 0x00, 0x00})\r | |
| 176 | \r | |
| 177 | //\r | |
| 178 | // Concatenate the _PDC capabilities bytes to the STS0 Buffer\r | |
| 179 | // and store them in a local variable for calling OSC\r | |
| 180 | //\r | |
| 181 | Concatenate (STS0, TEMP, Local2)\r | |
| 182 | \r | |
| 183 | Return(COSC (ToUUID("4077A616-290C-47BE-9EBD-D87058713953"), REVS, SIZE, Local2))\r | |
| 184 | }\r | |
| 185 | \r | |
| 186 | //\r | |
| 187 | // Implement a generic Method to check _OSC information which may be called\r | |
| 188 | // by any of the processor scopes.\r | |
| 189 | //\r | |
| 190 | Method(COSC, 4)\r | |
| 191 | {\r | |
| 192 | //\r | |
| 193 | // Point to Status DWORD in the Arg3 buffer (STATUS)\r | |
| 194 | //\r | |
| 195 | CreateDWordField(Arg3, 0, STS0)\r | |
| 196 | //\r | |
| 197 | // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES)\r | |
| 198 | //\r | |
| 199 | CreateDwordField(Arg3, 4, CAP0)\r | |
| 200 | \r | |
| 201 | //\r | |
| 202 | // _OSC needs to validate the UUID and Revision.\r | |
| 203 | //\r | |
| 204 | // IF Unrecognized UUID\r | |
| 205 | // Return Unrecognized UUID _OSC Failure\r | |
| 206 | // IF Unsupported Revision\r | |
| 207 | // Return Unsupported Revision _OSC Failure\r | |
| 208 | //\r | |
| 209 | // STS0[0] = Reserved\r | |
| 210 | // STS0[1] = _OSC Failure\r | |
| 211 | // STS0[2] = Unrecognized UUID\r | |
| 212 | // STS0[3] = Unsupported Revision\r | |
| 213 | // STS0[4] = Capabilities masked\r | |
| 214 | //\r | |
| 215 | // Note: The comparison method used is necessary due to\r | |
| 216 | // limitations of certain OSes which cannot perform direct\r | |
| 217 | // buffer comparisons.\r | |
| 218 | //\r | |
| 219 | // Create a set of "Input" UUID fields.\r | |
| 220 | //\r | |
| 221 | CreateDwordField(Arg0, 0x0, IID0)\r | |
| 222 | CreateDwordField(Arg0, 0x4, IID1)\r | |
| 223 | CreateDwordField(Arg0, 0x8, IID2)\r | |
| 224 | CreateDwordField(Arg0, 0xC, IID3)\r | |
| 225 | //\r | |
| 226 | // Create a set of "Expected" UUID fields.\r | |
| 227 | //\r | |
| 228 | Name(UID0, ToUUID("4077A616-290C-47BE-9EBD-D87058713953"))\r | |
| 229 | CreateDwordField(UID0, 0x0, EID0)\r | |
| 230 | CreateDwordField(UID0, 0x4, EID1)\r | |
| 231 | CreateDwordField(UID0, 0x8, EID2)\r | |
| 232 | CreateDwordField(UID0, 0xC, EID3)\r | |
| 233 | //\r | |
| 234 | // Verify the input UUID matches the expected UUID.\r | |
| 235 | //\r | |
| 236 | If(LNot(LAnd(LAnd(LEqual(IID0, EID0),LEqual(IID1, EID1)),LAnd(LEqual(IID2, EID2),LEqual(IID3, EID3)))))\r | |
| 237 | {\r | |
| 238 | //\r | |
| 239 | // Return Unrecognized UUID _OSC Failure\r | |
| 240 | //\r | |
| 241 | Store (0x6, STS0)\r | |
| 242 | Return (Arg3)\r | |
| 243 | }\r | |
| 244 | \r | |
| 245 | If(LNot(LEqual(Arg1,1)))\r | |
| 246 | {\r | |
| 247 | //\r | |
| 248 | // Return Unsupported Revision _OSC Failure\r | |
| 249 | //\r | |
| 250 | Store (0xA, STS0)\r | |
| 251 | Return (Arg3)\r | |
| 252 | }\r | |
| 253 | \r | |
| 254 | Return (Arg3)\r | |
| 255 | }\r | |
| 256 | \r | |
| 257 | //\r | |
| 258 | // Get the capability information and load appropriate tables as needed.\r | |
| 259 | //\r | |
| 260 | Method(GCAP, 1)\r | |
| 261 | {\r | |
| 262 | \r | |
| 263 | // Point to Status DWORD in the Arg0 buffer (STATUS)\r | |
| 264 | CreateDWordField(Arg0, 0, STS0)\r | |
| 265 | \r | |
| 266 | // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)\r | |
| 267 | CreateDwordField(Arg0, 4, CAP0)\r | |
| 268 | \r | |
| 269 | //\r | |
| 270 | // If the UUID was unrecognized or the _OSC revision was unsupported,\r | |
| 271 | // return without updating capabilities.\r | |
| 272 | //\r | |
| 273 | If(LOr(LEqual(STS0,0x6),LEqual(STS0,0xA)))\r | |
| 274 | {\r | |
| 275 | Return()\r | |
| 276 | }\r | |
| 277 | \r | |
| 278 | //\r | |
| 279 | // Check if this is a query (BIT0 of Status = 1).\r | |
| 280 | // If so, mask off the bits we support and return.\r | |
| 281 | //\r | |
| 282 | if (And(STS0, 1))\r | |
| 283 | {\r | |
| 284 | And(CAP0, 0xBFF, CAP0)\r | |
| 285 | Return()\r | |
| 286 | }\r | |
| 287 | \r | |
| 288 | //\r | |
| 289 | // Store result of PDC. (We clear out the MSB, which was just\r | |
| 290 | // used as a placeholder for the compiler; and then "OR" the\r | |
| 291 | // value in case we get multiple calls, each of which only\r | |
| 292 | // reports partial support.)\r | |
| 293 | //\r | |
| 294 | Or(And(PDC0, 0x7FFFFFFF), CAP0, PDC0)\r | |
| 295 | \r | |
| 296 | //\r | |
| 297 | // Check IF the IST SSDTs should be loaded.\r | |
| 298 | //\r | |
| 299 | // CFGD[0] = GV3 Capable/Enabled\r | |
| 300 | //\r | |
| 301 | If(And(CFGD,0x01))\r | |
| 302 | {\r | |
| 303 | //\r | |
| 304 | // Load the IST SSDTs if:\r | |
| 305 | // (1) CMP capable and enabled.\r | |
| 306 | // (2) Driver supports P-States in MP configurations\r | |
| 307 | // (3) Driver supports direct HW P-State control\r | |
| 308 | // (4) SSDT is not already loaded\r | |
| 309 | //\r | |
| 310 | // CFGD[24] = Two or more cores enabled\r | |
| 311 | // PDCx[3] = OS supports C1 and P-states in MP systems\r | |
| 312 | // PDCx[0] = OS supports direct access of the perf MSR\r | |
| 313 | // SDTL[0] = CPU0 IST SSDT Loaded\r | |
| 314 | //\r | |
| 315 | If(LAnd(LAnd(And(CFGD,0x01000000),LEqual(And(PDC0, 0x0009), 0x0009)),LNot(And(SDTL,0x01))))\r | |
| 316 | {\r | |
| 317 | //\r | |
| 318 | // Flag the IST SSDT as loaded for CPU0\r | |
| 319 | //\r | |
| 320 | Or(SDTL, 0x01, SDTL)\r | |
| 321 | \r | |
| 322 | OperationRegion(IST0,SystemMemory,DeRefOf(Index(SSDT,1)),DeRefOf(Index(SSDT,2)))\r | |
| 323 | Load(IST0, HI0) // Dynamically load the CPU0IST SSDT\r | |
| 324 | }\r | |
| 325 | }\r | |
| 326 | \r | |
| 327 | //\r | |
| 328 | // Check IF the CST SSDTs should be loaded.\r | |
| 329 | //\r | |
| 330 | // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled\r | |
| 331 | //\r | |
| 332 | If(And(CFGD,0x82))\r | |
| 333 | {\r | |
| 334 | //\r | |
| 335 | // Load the CST SSDTs if:\r | |
| 336 | // (1) CMP capable/enabled\r | |
| 337 | // (2) Driver supports multi-processor configurations\r | |
| 338 | // (3) CPU0 CST ISDT is not already loaded\r | |
| 339 | //\r | |
| 340 | // CFGD[24] = Two or more cores enabled\r | |
| 341 | // PDCx[3] = OS supports C1 and P-states in MP systems\r | |
| 342 | // PDCx[4] = OS supports ind. C2/C3 in MP systems\r | |
| 343 | // SDTL[1] = CPU0 CST SSDT Loaded\r | |
| 344 | //\r | |
| 345 | If(LAnd(LAnd(And(CFGD,0x01000000),And(PDC0,0x0018)),LNot(And(SDTL,0x02))))\r | |
| 346 | {\r | |
| 347 | //\r | |
| 348 | // Flag the CST SSDT as loaded for CPU0\r | |
| 349 | //\r | |
| 350 | Or(SDTL, 0x02, SDTL)\r | |
| 351 | \r | |
| 352 | OperationRegion(CST0,SystemMemory,DeRefOf(Index(SSDT,7)),DeRefOf(Index(SSDT,8)))\r | |
| 353 | Load(CST0, HC0) // Dynamically load the CPU0CST SSDT\r | |
| 354 | }\r | |
| 355 | }\r | |
| 356 | \r | |
| 357 | Return ()\r | |
| 358 | }\r | |
| 359 | }\r | |
| 360 | \r | |
| 361 | \r | |
| 362 | Scope(\_PR.CPU1)\r | |
| 363 | {\r | |
| 364 | //\r | |
| 365 | // Define handles for opregions (used by load.)\r | |
| 366 | //\r | |
| 367 | Name(HI1,0) // Handle to APIST\r | |
| 368 | Name(HC1,0) // Handle to APCST\r | |
| 369 | \r | |
| 370 | Method(_PDC,1)\r | |
| 371 | {\r | |
| 372 | //\r | |
| 373 | // Refer to \_PR.CPU0._PDC for description.\r | |
| 374 | //\r | |
| 375 | Store(\_PR.CPU0.CPDC(Arg0), Local0)\r | |
| 376 | GCAP(Local0)\r | |
| 377 | //Return (Local0)\r | |
| 378 | }\r | |
| 379 | \r | |
| 380 | Method(_OSC, 4)\r | |
| 381 | {\r | |
| 382 | //\r | |
| 383 | // Refer to \_PR.CPU0._OSC for description.\r | |
| 384 | //\r | |
| 385 | Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)\r | |
| 386 | GCAP(Local0)\r | |
| 387 | Return (Local0)\r | |
| 388 | }\r | |
| 389 | \r | |
| 390 | //\r | |
| 391 | // Get the capability information and load appropriate tables as needed.\r | |
| 392 | //\r | |
| 393 | Method(GCAP, 1)\r | |
| 394 | {\r | |
| 395 | //\r | |
| 396 | // Point to Status DWORD in the Arg0 buffer (STATUS)\r | |
| 397 | //\r | |
| 398 | CreateDWordField(Arg0, 0, STS1)\r | |
| 399 | //\r | |
| 400 | // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)\r | |
| 401 | //\r | |
| 402 | CreateDwordField(Arg0, 4, CAP1)\r | |
| 403 | //\r | |
| 404 | // If the UUID was unrecognized or the _OSC revision was unsupported,\r | |
| 405 | // return without updating capabilities.\r | |
| 406 | //\r | |
| 407 | If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))\r | |
| 408 | {\r | |
| 409 | Return()\r | |
| 410 | }\r | |
| 411 | \r | |
| 412 | //\r | |
| 413 | // Check if this is a query (BIT0 of Status = 1).\r | |
| 414 | // If so, mask off the bits we support and return.\r | |
| 415 | //\r | |
| 416 | if (And(STS1, 1))\r | |
| 417 | {\r | |
| 418 | And(CAP1, 0xBFF, CAP1)\r | |
| 419 | Return()\r | |
| 420 | }\r | |
| 421 | \r | |
| 422 | //\r | |
| 423 | // Store result of PDC. (We clear out the MSB, which was just\r | |
| 424 | // used as a placeholder for the compiler; and then "OR" the\r | |
| 425 | // value in case we get multiple calls, each of which only\r | |
| 426 | // reports partial support.)\r | |
| 427 | //\r | |
| 428 | Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)\r | |
| 429 | \r | |
| 430 | //\r | |
| 431 | // Attempt to dynamically load the IST SSDTs if:\r | |
| 432 | // (1) Driver supports P-States in MP configurations\r | |
| 433 | // (2) Driver supports direct HW P-State control\r | |
| 434 | //\r | |
| 435 | // PDCx[3] = OS supports C1 and P-states in MP systems\r | |
| 436 | // PDCx[0] = OS supports direct access of the perf MSR\r | |
| 437 | //\r | |
| 438 | If(LEqual(And(PDC0, 0x0009), 0x0009))\r | |
| 439 | {\r | |
| 440 | APPT()\r | |
| 441 | }\r | |
| 442 | \r | |
| 443 | //\r | |
| 444 | // Load the CST SSDTs if:\r | |
| 445 | // (1) Driver supports multi-processor configurations\r | |
| 446 | //\r | |
| 447 | // PDCx[3] = OS supports C1 and P-states in MP systems\r | |
| 448 | // PDCx[4] = OS supports ind. C2/C3 in MP systems\r | |
| 449 | //\r | |
| 450 | If(And(PDC0,0x0018))\r | |
| 451 | {\r | |
| 452 | APCT()\r | |
| 453 | }\r | |
| 454 | \r | |
| 455 | Return()\r | |
| 456 | }\r | |
| 457 | \r | |
| 458 | //\r | |
| 459 | // Dynamically load the CST SSDTs if:\r | |
| 460 | // (1) C-States are enabled\r | |
| 461 | // (2) SSDT is not already loaded\r | |
| 462 | //\r | |
| 463 | // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled\r | |
| 464 | // SDTL[5] = AP CST SSDT Loaded\r | |
| 465 | //\r | |
| 466 | Method(APCT,0)\r | |
| 467 | {\r | |
| 468 | If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))\r | |
| 469 | {\r | |
| 470 | //\r | |
| 471 | // Flag the CST SSDT as loaded for the AP's\r | |
| 472 | //\r | |
| 473 | Or(SDTL, 0x20, SDTL)\r | |
| 474 | //\r | |
| 475 | // Dynamically load the APCST SSDT\r | |
| 476 | //\r | |
| 477 | OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))\r | |
| 478 | Load(CST1, HC1)\r | |
| 479 | }\r | |
| 480 | }\r | |
| 481 | \r | |
| 482 | //\r | |
| 483 | // Dynamically load the IST SSDTs if:\r | |
| 484 | // (1) If GV3 capable and enabled\r | |
| 485 | // (2) SSDT is not already loaded\r | |
| 486 | //\r | |
| 487 | // CFGD[0] = GV3 Capable/Enabled\r | |
| 488 | // SDTL[4] = AP IST SSDT Loaded\r | |
| 489 | //\r | |
| 490 | Method(APPT,0)\r | |
| 491 | {\r | |
| 492 | If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))\r | |
| 493 | {\r | |
| 494 | //\r | |
| 495 | // Flag the IST SSDT as loaded for CPU0\r | |
| 496 | //\r | |
| 497 | Or(SDTL, 0x10, SDTL)\r | |
| 498 | \r | |
| 499 | OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))\r | |
| 500 | Load(IST1, HI1) // Dynamically load the CPU1IST SSDT\r | |
| 501 | }\r | |
| 502 | }\r | |
| 503 | } // End CPU1\r | |
| 504 | \r | |
| 505 | Scope(\_PR.CPU2)\r | |
| 506 | {\r | |
| 507 | //\r | |
| 508 | // Define handles for opregions (used by load.)\r | |
| 509 | //\r | |
| 510 | Name(HI1,0) // Handle to APIST\r | |
| 511 | Name(HC1,0) // Handle to APCST\r | |
| 512 | \r | |
| 513 | Method(_PDC,1)\r | |
| 514 | {\r | |
| 515 | //\r | |
| 516 | // Refer to \_PR.CPU0._PDC for description.\r | |
| 517 | //\r | |
| 518 | Store(\_PR.CPU0.CPDC(Arg0), Local0)\r | |
| 519 | GCAP(Local0)\r | |
| 520 | //Return (Local0)\r | |
| 521 | }\r | |
| 522 | \r | |
| 523 | Method(_OSC, 4)\r | |
| 524 | {\r | |
| 525 | //\r | |
| 526 | // Refer to \_PR.CPU0._OSC for description.\r | |
| 527 | //\r | |
| 528 | Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)\r | |
| 529 | GCAP(Local0)\r | |
| 530 | Return (Local0)\r | |
| 531 | }\r | |
| 532 | \r | |
| 533 | //\r | |
| 534 | // Get the capability information and load appropriate tables as needed.\r | |
| 535 | //\r | |
| 536 | Method(GCAP, 1)\r | |
| 537 | {\r | |
| 538 | //\r | |
| 539 | // Point to Status DWORD in the Arg0 buffer (STATUS)\r | |
| 540 | //\r | |
| 541 | CreateDWordField(Arg0, 0, STS1)\r | |
| 542 | //\r | |
| 543 | // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)\r | |
| 544 | //\r | |
| 545 | CreateDwordField(Arg0, 4, CAP1)\r | |
| 546 | //\r | |
| 547 | // If the UUID was unrecognized or the _OSC revision was unsupported,\r | |
| 548 | // return without updating capabilities.\r | |
| 549 | //\r | |
| 550 | If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))\r | |
| 551 | {\r | |
| 552 | Return()\r | |
| 553 | }\r | |
| 554 | \r | |
| 555 | //\r | |
| 556 | // Check if this is a query (BIT0 of Status = 1).\r | |
| 557 | // If so, mask off the bits we support and return.\r | |
| 558 | //\r | |
| 559 | if (And(STS1, 1))\r | |
| 560 | {\r | |
| 561 | And(CAP1, 0xBFF, CAP1)\r | |
| 562 | Return()\r | |
| 563 | }\r | |
| 564 | \r | |
| 565 | //\r | |
| 566 | // Store result of PDC. (We clear out the MSB, which was just\r | |
| 567 | // used as a placeholder for the compiler; and then "OR" the\r | |
| 568 | // value in case we get multiple calls, each of which only\r | |
| 569 | // reports partial support.)\r | |
| 570 | //\r | |
| 571 | Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)\r | |
| 572 | \r | |
| 573 | //\r | |
| 574 | // Attempt to dynamically load the IST SSDTs if:\r | |
| 575 | // (1) Driver supports P-States in MP configurations\r | |
| 576 | // (2) Driver supports direct HW P-State control\r | |
| 577 | //\r | |
| 578 | // PDCx[3] = OS supports C1 and P-states in MP systems\r | |
| 579 | // PDCx[0] = OS supports direct access of the perf MSR\r | |
| 580 | //\r | |
| 581 | If(LEqual(And(PDC0, 0x0009), 0x0009))\r | |
| 582 | {\r | |
| 583 | APPT()\r | |
| 584 | }\r | |
| 585 | \r | |
| 586 | //\r | |
| 587 | // Load the CST SSDTs if:\r | |
| 588 | // (1) Driver supports multi-processor configurations\r | |
| 589 | //\r | |
| 590 | // PDCx[3] = OS supports C1 and P-states in MP systems\r | |
| 591 | // PDCx[4] = OS supports ind. C2/C3 in MP systems\r | |
| 592 | //\r | |
| 593 | If(And(PDC0,0x0018))\r | |
| 594 | {\r | |
| 595 | APCT()\r | |
| 596 | }\r | |
| 597 | \r | |
| 598 | Return()\r | |
| 599 | }\r | |
| 600 | \r | |
| 601 | //\r | |
| 602 | // Dynamically load the CST SSDTs if:\r | |
| 603 | // (1) C-States are enabled\r | |
| 604 | // (2) SSDT is not already loaded\r | |
| 605 | //\r | |
| 606 | // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled\r | |
| 607 | // SDTL[5] = AP CST SSDT Loaded\r | |
| 608 | //\r | |
| 609 | Method(APCT,0)\r | |
| 610 | {\r | |
| 611 | If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))\r | |
| 612 | {\r | |
| 613 | //\r | |
| 614 | // Flag the CST SSDT as loaded for the AP's\r | |
| 615 | //\r | |
| 616 | Or(SDTL, 0x20, SDTL)\r | |
| 617 | //\r | |
| 618 | // Dynamically load the APCST SSDT\r | |
| 619 | //\r | |
| 620 | OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))\r | |
| 621 | Load(CST1, HC1)\r | |
| 622 | }\r | |
| 623 | }\r | |
| 624 | \r | |
| 625 | //\r | |
| 626 | // Dynamically load the IST SSDTs if:\r | |
| 627 | // (1) If GV3 capable and enabled\r | |
| 628 | // (2) SSDT is not already loaded\r | |
| 629 | //\r | |
| 630 | // CFGD[0] = GV3 Capable/Enabled\r | |
| 631 | // SDTL[4] = AP IST SSDT Loaded\r | |
| 632 | //\r | |
| 633 | Method(APPT,0)\r | |
| 634 | {\r | |
| 635 | If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))\r | |
| 636 | {\r | |
| 637 | //\r | |
| 638 | // Flag the IST SSDT as loaded for CPU0\r | |
| 639 | //\r | |
| 640 | Or(SDTL, 0x10, SDTL)\r | |
| 641 | \r | |
| 642 | OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))\r | |
| 643 | Load(IST1, HI1) // Dynamically load the CPU1IST SSDT\r | |
| 644 | }\r | |
| 645 | }\r | |
| 646 | } // End CPU1\r | |
| 647 | \r | |
| 648 | Scope(\_PR.CPU3)\r | |
| 649 | {\r | |
| 650 | //\r | |
| 651 | // Define handles for opregions (used by load.)\r | |
| 652 | //\r | |
| 653 | Name(HI1,0) // Handle to APIST\r | |
| 654 | Name(HC1,0) // Handle to APCST\r | |
| 655 | \r | |
| 656 | Method(_PDC,1)\r | |
| 657 | {\r | |
| 658 | //\r | |
| 659 | // Refer to \_PR.CPU0._PDC for description.\r | |
| 660 | //\r | |
| 661 | Store(\_PR.CPU0.CPDC(Arg0), Local0)\r | |
| 662 | GCAP(Local0)\r | |
| 663 | //Return (Local0)\r | |
| 664 | }\r | |
| 665 | \r | |
| 666 | Method(_OSC, 4)\r | |
| 667 | {\r | |
| 668 | //\r | |
| 669 | // Refer to \_PR.CPU0._OSC for description.\r | |
| 670 | //\r | |
| 671 | Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)\r | |
| 672 | GCAP(Local0)\r | |
| 673 | Return (Local0)\r | |
| 674 | }\r | |
| 675 | \r | |
| 676 | //\r | |
| 677 | // Get the capability information and load appropriate tables as needed.\r | |
| 678 | //\r | |
| 679 | Method(GCAP, 1)\r | |
| 680 | {\r | |
| 681 | //\r | |
| 682 | // Point to Status DWORD in the Arg0 buffer (STATUS)\r | |
| 683 | //\r | |
| 684 | CreateDWordField(Arg0, 0, STS1)\r | |
| 685 | //\r | |
| 686 | // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)\r | |
| 687 | //\r | |
| 688 | CreateDwordField(Arg0, 4, CAP1)\r | |
| 689 | //\r | |
| 690 | // If the UUID was unrecognized or the _OSC revision was unsupported,\r | |
| 691 | // return without updating capabilities.\r | |
| 692 | //\r | |
| 693 | If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))\r | |
| 694 | {\r | |
| 695 | Return()\r | |
| 696 | }\r | |
| 697 | \r | |
| 698 | //\r | |
| 699 | // Check if this is a query (BIT0 of Status = 1).\r | |
| 700 | // If so, mask off the bits we support and return.\r | |
| 701 | //\r | |
| 702 | if (And(STS1, 1))\r | |
| 703 | {\r | |
| 704 | And(CAP1, 0xBFF, CAP1)\r | |
| 705 | Return()\r | |
| 706 | }\r | |
| 707 | \r | |
| 708 | //\r | |
| 709 | // Store result of PDC. (We clear out the MSB, which was just\r | |
| 710 | // used as a placeholder for the compiler; and then "OR" the\r | |
| 711 | // value in case we get multiple calls, each of which only\r | |
| 712 | // reports partial support.)\r | |
| 713 | //\r | |
| 714 | Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)\r | |
| 715 | \r | |
| 716 | //\r | |
| 717 | // Attempt to dynamically load the IST SSDTs if:\r | |
| 718 | // (1) Driver supports P-States in MP configurations\r | |
| 719 | // (2) Driver supports direct HW P-State control\r | |
| 720 | //\r | |
| 721 | // PDCx[3] = OS supports C1 and P-states in MP systems\r | |
| 722 | // PDCx[0] = OS supports direct access of the perf MSR\r | |
| 723 | //\r | |
| 724 | If(LEqual(And(PDC0, 0x0009), 0x0009))\r | |
| 725 | {\r | |
| 726 | APPT()\r | |
| 727 | }\r | |
| 728 | \r | |
| 729 | //\r | |
| 730 | // Load the CST SSDTs if:\r | |
| 731 | // (1) Driver supports multi-processor configurations\r | |
| 732 | //\r | |
| 733 | // PDCx[3] = OS supports C1 and P-states in MP systems\r | |
| 734 | // PDCx[4] = OS supports ind. C2/C3 in MP systems\r | |
| 735 | //\r | |
| 736 | If(And(PDC0,0x0018))\r | |
| 737 | {\r | |
| 738 | APCT()\r | |
| 739 | }\r | |
| 740 | \r | |
| 741 | Return()\r | |
| 742 | }\r | |
| 743 | \r | |
| 744 | //\r | |
| 745 | // Dynamically load the CST SSDTs if:\r | |
| 746 | // (1) C-States are enabled\r | |
| 747 | // (2) SSDT is not already loaded\r | |
| 748 | //\r | |
| 749 | // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled\r | |
| 750 | // SDTL[5] = AP CST SSDT Loaded\r | |
| 751 | //\r | |
| 752 | Method(APCT,0)\r | |
| 753 | {\r | |
| 754 | If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))\r | |
| 755 | {\r | |
| 756 | //\r | |
| 757 | // Flag the CST SSDT as loaded for the AP's\r | |
| 758 | //\r | |
| 759 | Or(SDTL, 0x20, SDTL)\r | |
| 760 | //\r | |
| 761 | // Dynamically load the APCST SSDT\r | |
| 762 | //\r | |
| 763 | OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))\r | |
| 764 | Load(CST1, HC1)\r | |
| 765 | }\r | |
| 766 | }\r | |
| 767 | \r | |
| 768 | //\r | |
| 769 | // Dynamically load the IST SSDTs if:\r | |
| 770 | // (1) If GV3 capable and enabled\r | |
| 771 | // (2) SSDT is not already loaded\r | |
| 772 | //\r | |
| 773 | // CFGD[0] = GV3 Capable/Enabled\r | |
| 774 | // SDTL[4] = AP IST SSDT Loaded\r | |
| 775 | //\r | |
| 776 | Method(APPT,0)\r | |
| 777 | {\r | |
| 778 | If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))\r | |
| 779 | {\r | |
| 780 | //\r | |
| 781 | // Flag the IST SSDT as loaded for CPU0\r | |
| 782 | //\r | |
| 783 | Or(SDTL, 0x10, SDTL)\r | |
| 784 | \r | |
| 785 | OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))\r | |
| 786 | Load(IST1, HI1) // Dynamically load the CPU1IST SSDT\r | |
| 787 | }\r | |
| 788 | }\r | |
| 789 | } // End CPU3\r | |
| 790 | } // End of Definition Block\r | |
| 791 | \r | |
| 792 | \r | |
| 793 | \r |