[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / NorthCluster / Include / VlvCommonDefinitions.h

\r
/*++\r
\r
Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
\r
\r
Module Name:\r
\r
  VlvCommonDefinitions.h\r
\r
Abstract:\r
\r
  Macros to simplify and abstract the interface to PCI configuration.\r
\r
--*/\r
\r
///\r
/// PCI CONFIGURATION MAP REGISTER OFFSETS\r
///\r
#ifndef PCI_VID\r
#define PCI_VID             0x0000  ///< Vendor ID Register\r
#define PCI_DID             0x0002  ///< Device ID Register\r
#define PCI_CMD             0x0004  ///< PCI Command Register\r
#define PCI_STS             0x0006  ///< PCI Status Register\r
#define PCI_RID             0x0008  ///< Revision ID Register\r
#define PCI_IFT             0x0009  ///< Interface Type\r
#define PCI_SCC             0x000A  ///< Sub Class Code Register\r
#define PCI_BCC             0x000B  ///< Base Class Code Register\r
#define PCI_CLS             0x000C  ///< Cache Line Size\r
#define PCI_PMLT            0x000D  ///< Primary Master Latency Timer\r
#define PCI_HDR             0x000E  ///< Header Type Register\r
#define PCI_BIST            0x000F  ///< Built in Self Test Register\r
#define PCI_BAR0            0x0010  ///< Base Address Register 0\r
#define PCI_BAR1            0x0014  ///< Base Address Register 1\r
#define PCI_BAR2            0x0018  ///< Base Address Register 2\r
#define PCI_PBUS            0x0018  ///< Primary Bus Number Register\r
#define PCI_SBUS            0x0019  ///< Secondary Bus Number Register\r
#define PCI_SUBUS           0x001A  ///< Subordinate Bus Number Register\r
#define PCI_SMLT            0x001B  ///< Secondary Master Latency Timer\r
#define PCI_BAR3            0x001C  ///< Base Address Register 3\r
#define PCI_IOBASE          0x001C  ///< I/O base Register\r
#define PCI_IOLIMIT         0x001D  ///< I/O Limit Register\r
#define PCI_SECSTATUS       0x001E  ///< Secondary Status Register\r
#define PCI_BAR4            0x0020  ///< Base Address Register 4\r
#define PCI_MEMBASE         0x0020  ///< Memory Base Register\r
#define PCI_MEMLIMIT        0x0022  ///< Memory Limit Register\r
#define PCI_BAR5            0x0024  ///< Base Address Register 5\r
#define PCI_PRE_MEMBASE     0x0024  ///< Prefetchable memory Base register\r
#define PCI_PRE_MEMLIMIT    0x0026  ///< Prefetchable memory Limit register\r
#define PCI_PRE_MEMBASE_U   0x0028  ///< Prefetchable memory base upper 32 bits\r
#define PCI_PRE_MEMLIMIT_U  0x002C  ///< Prefetchable memory limit upper 32 bits\r
#define PCI_SVID            0x002C  ///< Subsystem Vendor ID\r
#define PCI_SID             0x002E  ///< Subsystem ID\r
#define PCI_IOBASE_U        0x0030  ///< I/O base Upper Register\r
#define PCI_IOLIMIT_U       0x0032  ///< I/O Limit Upper Register\r
#define PCI_CAPP            0x0034  ///< Capabilities Pointer\r
#define PCI_EROM            0x0038  ///< Expansion ROM Base Address\r
#define PCI_INTLINE         0x003C  ///< Interrupt Line Register\r
#define PCI_INTPIN          0x003D  ///< Interrupt Pin Register\r
#define PCI_MAXGNT          0x003E  ///< Max Grant Register\r
#define PCI_BRIDGE_CNTL     0x003E  ///< Bridge Control Register\r
#define PCI_MAXLAT          0x003F  ///< Max Latency Register\r
#endif\r
//\r
// Bit Difinitions\r
//\r
#ifndef BIT0\r
#define BIT0                     0x0001\r
#define BIT1                     0x0002\r
#define BIT2                     0x0004\r
#define BIT3                     0x0008\r
#define BIT4                     0x0010\r
#define BIT5                     0x0020\r
#define BIT6                     0x0040\r
#define BIT7                     0x0080\r
#define BIT8                     0x0100\r
#define BIT9                     0x0200\r
#define BIT10                    0x0400\r
#define BIT11                    0x0800\r
#define BIT12                    0x1000\r
#define BIT13                    0x2000\r
#define BIT14                    0x4000\r
#define BIT15                    0x8000\r
#define BIT16                    0x00010000\r
#define BIT17                    0x00020000\r
#define BIT18                    0x00040000\r
#define BIT19                    0x00080000\r
#define BIT20                    0x00100000\r
#define BIT21                    0x00200000\r
#define BIT22                    0x00400000\r
#define BIT23                    0x00800000\r
#define BIT24                    0x01000000\r
#define BIT25                    0x02000000\r
#define BIT26                    0x04000000\r
#define BIT27                    0x08000000\r
#define BIT28                    0x10000000\r
#define BIT29                    0x20000000\r
#define BIT30                    0x40000000\r
#define BIT31                    0x80000000\r
#endif\r
\r
#ifndef _PCIACCESS_H_INCLUDED_\r
#define _PCIACCESS_H_INCLUDED_\r
#ifndef PCI_EXPRESS_BASE_ADDRESS\r
 #define PCI_EXPRESS_BASE_ADDRESS 0xE0000000\r
#endif\r
\r
#ifndef MmPciAddress\r
#define MmPciAddress( Segment, Bus, Device, Function, Register ) \\r
  ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \\r
    (UINTN)(Bus << 20) + \\r
    (UINTN)(Device << 15) + \\r
    (UINTN)(Function << 12) + \\r
    (UINTN)(Register) \\r
  )\r
#endif\r
\r
//\r
// UINT64\r
//\r
#define MmPci64Ptr( Segment, Bus, Device, Function, Register ) \\r
  ( (volatile UINT64 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )\r
\r
#define MmPci64( Segment, Bus, Device, Function, Register ) \\r
  *MmPci64Ptr( Segment, Bus, Device, Function, Register )\r
\r
#define MmPci64Or( Segment, Bus, Device, Function, Register, OrData ) \\r
  MmPci64( Segment, Bus, Device, Function, Register ) = \\r
    (UINT64) ( \\r
      MmPci64( Segment, Bus, Device, Function, Register ) | \\r
      (UINT64)(OrData) \\r
    )\r
\r
#define MmPci64And( Segment, Bus, Device, Function, Register, AndData ) \\r
  MmPci64( Segment, Bus, Device, Function, Register ) = \\r
    (UINT64) ( \\r
      MmPci64( Segment, Bus, Device, Function, Register ) & \\r
      (UINT64)(AndData) \\r
    )\r
\r
#define MmPci64AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
  MmPci64( Segment, Bus, Device, Function, Register ) = \\r
    (UINT64) ( \\r
      ( MmPci64( Segment, Bus, Device, Function, Register ) & \\r
          (UINT64)(AndData) \\r
      ) | \\r
      (UINT64)(OrData) \\r
    )\r
\r
//\r
// UINT32\r
//\r
\r
#define MmPci32Ptr( Segment, Bus, Device, Function, Register ) \\r
  ( (volatile UINT32 *) MmPciAddress( Segment, Bus, Device, Function, Register ) )\r
\r
#define MmPci32( Segment, Bus, Device, Function, Register ) \\r
  *MmPci32Ptr( Segment, Bus, Device, Function, Register )\r
\r
#define MmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \\r
  MmPci32( Segment, Bus, Device, Function, Register ) = \\r
    (UINT32) ( \\r
      MmPci32( Segment, Bus, Device, Function, Register ) | \\r
      (UINT32)(OrData) \\r
    )\r
\r
#define MmPci32And( Segment, Bus, Device, Function, Register, AndData ) \\r
  MmPci32( Segment, Bus, Device, Function, Register ) = \\r
    (UINT32) ( \\r
      MmPci32( Segment, Bus, Device, Function, Register ) & \\r
      (UINT32)(AndData) \\r
    )\r
\r
#define MmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
  MmPci32( Segment, Bus, Device, Function, Register ) = \\r
    (UINT32) ( \\r
      ( MmPci32( Segment, Bus, Device, Function, Register ) & \\r
          (UINT32)(AndData) \\r
      ) | \\r
      (UINT32)(OrData) \\r
    )\r
\r
//\r
// UINT16\r
//\r
\r
#define MmPci16Ptr( Segment, Bus, Device, Function, Register ) \\r
  ( (volatile UINT16 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )\r
\r
#define MmPci16( Segment, Bus, Device, Function, Register ) \\r
  *MmPci16Ptr( Segment, Bus, Device, Function, Register )\r
\r
#define MmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \\r
  MmPci16( Segment, Bus, Device, Function, Register ) = \\r
    (UINT16) ( \\r
      MmPci16( Segment, Bus, Device, Function, Register ) | \\r
      (UINT16)(OrData) \\r
    )\r
\r
#define MmPci16And( Segment, Bus, Device, Function, Register, AndData ) \\r
  MmPci16( Segment, Bus, Device, Function, Register ) = \\r
    (UINT16) ( \\r
      MmPci16( Segment, Bus, Device, Function, Register ) & \\r
      (UINT16)(AndData) \\r
    )\r
\r
#define MmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
  MmPci16( Segment, Bus, Device, Function, Register ) = \\r
    (UINT16) ( \\r
      ( MmPci16( Segment, Bus, Device, Function, Register ) & \\r
          (UINT16)(AndData) \\r
      ) | \\r
      (UINT16)(OrData) \\r
    )\r
\r
//\r
// UINT8\r
//\r
\r
#define MmPci8Ptr( Segment, Bus, Device, Function, Register ) \\r
  ( (volatile UINT8 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )\r
\r
#define MmPci8( Segment, Bus, Device, Function, Register ) \\r
  *MmPci8Ptr( Segment, Bus, Device, Function, Register )\r
\r
#define MmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \\r
  MmPci8( Segment, Bus, Device, Function, Register ) = \\r
    (UINT8) ( \\r
      MmPci8( Segment, Bus, Device, Function, Register ) | \\r
      (UINT8)(OrData) \\r
    )\r
\r
#define MmPci8And( Segment, Bus, Device, Function, Register, AndData ) \\r
  MmPci8( Segment, Bus, Device, Function, Register ) = \\r
    (UINT8) ( \\r
      MmPci8( Segment, Bus, Device, Function, Register ) & \\r
      (UINT8)(AndData) \\r
    )\r
\r
#define MmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
  MmPci8( Segment, Bus, Device, Function, Register ) = \\r
    (UINT8) ( \\r
      ( MmPci8( Segment, Bus, Device, Function, Register ) & \\r
          (UINT8)(AndData) \\r
        ) | \\r
      (UINT8)(OrData) \\r
    )\r
\r
#endif\r
Commit	Line	Data
3cbfba02 DW	1	\r
	2	/*++\r
	3	\r
	4	Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
	5	\r
7ede8060	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
3cbfba02 DW	7	\r
	8	\r
	9	\r
	10	Module Name:\r
	11	\r
	12	VlvCommonDefinitions.h\r
	13	\r
	14	Abstract:\r
	15	\r
	16	Macros to simplify and abstract the interface to PCI configuration.\r
	17	\r
	18	--*/\r
	19	\r
	20	///\r
	21	/// PCI CONFIGURATION MAP REGISTER OFFSETS\r
	22	///\r
	23	#ifndef PCI_VID\r
	24	#define PCI_VID 0x0000 ///< Vendor ID Register\r
	25	#define PCI_DID 0x0002 ///< Device ID Register\r
	26	#define PCI_CMD 0x0004 ///< PCI Command Register\r
	27	#define PCI_STS 0x0006 ///< PCI Status Register\r
	28	#define PCI_RID 0x0008 ///< Revision ID Register\r
	29	#define PCI_IFT 0x0009 ///< Interface Type\r
	30	#define PCI_SCC 0x000A ///< Sub Class Code Register\r
	31	#define PCI_BCC 0x000B ///< Base Class Code Register\r
	32	#define PCI_CLS 0x000C ///< Cache Line Size\r
	33	#define PCI_PMLT 0x000D ///< Primary Master Latency Timer\r
	34	#define PCI_HDR 0x000E ///< Header Type Register\r
	35	#define PCI_BIST 0x000F ///< Built in Self Test Register\r
	36	#define PCI_BAR0 0x0010 ///< Base Address Register 0\r
	37	#define PCI_BAR1 0x0014 ///< Base Address Register 1\r
	38	#define PCI_BAR2 0x0018 ///< Base Address Register 2\r
	39	#define PCI_PBUS 0x0018 ///< Primary Bus Number Register\r
	40	#define PCI_SBUS 0x0019 ///< Secondary Bus Number Register\r
	41	#define PCI_SUBUS 0x001A ///< Subordinate Bus Number Register\r
	42	#define PCI_SMLT 0x001B ///< Secondary Master Latency Timer\r
	43	#define PCI_BAR3 0x001C ///< Base Address Register 3\r
	44	#define PCI_IOBASE 0x001C ///< I/O base Register\r
	45	#define PCI_IOLIMIT 0x001D ///< I/O Limit Register\r
	46	#define PCI_SECSTATUS 0x001E ///< Secondary Status Register\r
	47	#define PCI_BAR4 0x0020 ///< Base Address Register 4\r
	48	#define PCI_MEMBASE 0x0020 ///< Memory Base Register\r
	49	#define PCI_MEMLIMIT 0x0022 ///< Memory Limit Register\r
	50	#define PCI_BAR5 0x0024 ///< Base Address Register 5\r
	51	#define PCI_PRE_MEMBASE 0x0024 ///< Prefetchable memory Base register\r
	52	#define PCI_PRE_MEMLIMIT 0x0026 ///< Prefetchable memory Limit register\r
	53	#define PCI_PRE_MEMBASE_U 0x0028 ///< Prefetchable memory base upper 32 bits\r
	54	#define PCI_PRE_MEMLIMIT_U 0x002C ///< Prefetchable memory limit upper 32 bits\r
	55	#define PCI_SVID 0x002C ///< Subsystem Vendor ID\r
	56	#define PCI_SID 0x002E ///< Subsystem ID\r
	57	#define PCI_IOBASE_U 0x0030 ///< I/O base Upper Register\r
	58	#define PCI_IOLIMIT_U 0x0032 ///< I/O Limit Upper Register\r
	59	#define PCI_CAPP 0x0034 ///< Capabilities Pointer\r
	60	#define PCI_EROM 0x0038 ///< Expansion ROM Base Address\r
	61	#define PCI_INTLINE 0x003C ///< Interrupt Line Register\r
	62	#define PCI_INTPIN 0x003D ///< Interrupt Pin Register\r
	63	#define PCI_MAXGNT 0x003E ///< Max Grant Register\r
	64	#define PCI_BRIDGE_CNTL 0x003E ///< Bridge Control Register\r
	65	#define PCI_MAXLAT 0x003F ///< Max Latency Register\r
	66	#endif\r
	67	//\r
	68	// Bit Difinitions\r
	69	//\r
	70	#ifndef BIT0\r
71	#define BIT0 0x0001\r
72	#define BIT1 0x0002\r
73	#define BIT2 0x0004\r
74	#define BIT3 0x0008\r
75	#define BIT4 0x0010\r
76	#define BIT5 0x0020\r
77	#define BIT6 0x0040\r
78	#define BIT7 0x0080\r
79	#define BIT8 0x0100\r
80	#define BIT9 0x0200\r
81	#define BIT10 0x0400\r
82	#define BIT11 0x0800\r
83	#define BIT12 0x1000\r
84	#define BIT13 0x2000\r
85	#define BIT14 0x4000\r
86	#define BIT15 0x8000\r
87	#define BIT16 0x00010000\r
88	#define BIT17 0x00020000\r
89	#define BIT18 0x00040000\r
90	#define BIT19 0x00080000\r
91	#define BIT20 0x00100000\r
92	#define BIT21 0x00200000\r
93	#define BIT22 0x00400000\r
94	#define BIT23 0x00800000\r
95	#define BIT24 0x01000000\r
96	#define BIT25 0x02000000\r
97	#define BIT26 0x04000000\r
98	#define BIT27 0x08000000\r
99	#define BIT28 0x10000000\r
100	#define BIT29 0x20000000\r
101	#define BIT30 0x40000000\r
102	#define BIT31 0x80000000\r
103	#endif\r
104	\r
105	#ifndef _PCIACCESS_H_INCLUDED_\r
106	#define _PCIACCESS_H_INCLUDED_\r
107	#ifndef PCI_EXPRESS_BASE_ADDRESS\r
108	#define PCI_EXPRESS_BASE_ADDRESS 0xE0000000\r
109	#endif\r
110	\r
111	#ifndef MmPciAddress\r
112	#define MmPciAddress( Segment, Bus, Device, Function, Register ) \\r
113	( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \\r
114	(UINTN)(Bus << 20) + \\r
115	(UINTN)(Device << 15) + \\r
116	(UINTN)(Function << 12) + \\r
117	(UINTN)(Register) \\r
118	)\r
119	#endif\r
120	\r
121	//\r
122	// UINT64\r
123	//\r
124	#define MmPci64Ptr( Segment, Bus, Device, Function, Register ) \\r
125	( (volatile UINT64 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )\r
126	\r
127	#define MmPci64( Segment, Bus, Device, Function, Register ) \\r
128	*MmPci64Ptr( Segment, Bus, Device, Function, Register )\r
129	\r
130	#define MmPci64Or( Segment, Bus, Device, Function, Register, OrData ) \\r
131	MmPci64( Segment, Bus, Device, Function, Register ) = \\r
132	(UINT64) ( \\r
133	MmPci64( Segment, Bus, Device, Function, Register ) \| \\r
134	(UINT64)(OrData) \\r
135	)\r
136	\r
137	#define MmPci64And( Segment, Bus, Device, Function, Register, AndData ) \\r
138	MmPci64( Segment, Bus, Device, Function, Register ) = \\r
139	(UINT64) ( \\r
140	MmPci64( Segment, Bus, Device, Function, Register ) & \\r
141	(UINT64)(AndData) \\r
142	)\r
143	\r
144	#define MmPci64AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
145	MmPci64( Segment, Bus, Device, Function, Register ) = \\r
146	(UINT64) ( \\r
147	( MmPci64( Segment, Bus, Device, Function, Register ) & \\r
148	(UINT64)(AndData) \\r
149	) \| \\r
150	(UINT64)(OrData) \\r
151	)\r
152	\r
153	//\r
154	// UINT32\r
155	//\r
156	\r
157	#define MmPci32Ptr( Segment, Bus, Device, Function, Register ) \\r
158	( (volatile UINT32 *) MmPciAddress( Segment, Bus, Device, Function, Register ) )\r
159	\r
160	#define MmPci32( Segment, Bus, Device, Function, Register ) \\r
161	*MmPci32Ptr( Segment, Bus, Device, Function, Register )\r
162	\r
163	#define MmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \\r
164	MmPci32( Segment, Bus, Device, Function, Register ) = \\r
165	(UINT32) ( \\r
166	MmPci32( Segment, Bus, Device, Function, Register ) \| \\r
167	(UINT32)(OrData) \\r
168	)\r
169	\r
170	#define MmPci32And( Segment, Bus, Device, Function, Register, AndData ) \\r
171	MmPci32( Segment, Bus, Device, Function, Register ) = \\r
172	(UINT32) ( \\r
173	MmPci32( Segment, Bus, Device, Function, Register ) & \\r
174	(UINT32)(AndData) \\r
175	)\r
176	\r
177	#define MmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
178	MmPci32( Segment, Bus, Device, Function, Register ) = \\r
179	(UINT32) ( \\r
180	( MmPci32( Segment, Bus, Device, Function, Register ) & \\r
181	(UINT32)(AndData) \\r
182	) \| \\r
183	(UINT32)(OrData) \\r
184	)\r
185	\r
186	//\r
187	// UINT16\r
188	//\r
189	\r
190	#define MmPci16Ptr( Segment, Bus, Device, Function, Register ) \\r
191	( (volatile UINT16 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )\r
192	\r
193	#define MmPci16( Segment, Bus, Device, Function, Register ) \\r
194	*MmPci16Ptr( Segment, Bus, Device, Function, Register )\r
195	\r
196	#define MmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \\r
197	MmPci16( Segment, Bus, Device, Function, Register ) = \\r
198	(UINT16) ( \\r
199	MmPci16( Segment, Bus, Device, Function, Register ) \| \\r
200	(UINT16)(OrData) \\r
201	)\r
202	\r
203	#define MmPci16And( Segment, Bus, Device, Function, Register, AndData ) \\r
204	MmPci16( Segment, Bus, Device, Function, Register ) = \\r
205	(UINT16) ( \\r
206	MmPci16( Segment, Bus, Device, Function, Register ) & \\r
207	(UINT16)(AndData) \\r
208	)\r
209	\r
210	#define MmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
211	MmPci16( Segment, Bus, Device, Function, Register ) = \\r
212	(UINT16) ( \\r
213	( MmPci16( Segment, Bus, Device, Function, Register ) & \\r
214	(UINT16)(AndData) \\r
215	) \| \\r
216	(UINT16)(OrData) \\r
217	)\r
218	\r
219	//\r
220	// UINT8\r
221	//\r
222	\r
223	#define MmPci8Ptr( Segment, Bus, Device, Function, Register ) \\r
224	( (volatile UINT8 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )\r
225	\r
226	#define MmPci8( Segment, Bus, Device, Function, Register ) \\r
227	*MmPci8Ptr( Segment, Bus, Device, Function, Register )\r
228	\r
229	#define MmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \\r
230	MmPci8( Segment, Bus, Device, Function, Register ) = \\r
231	(UINT8) ( \\r
232	MmPci8( Segment, Bus, Device, Function, Register ) \| \\r
233	(UINT8)(OrData) \\r
234	)\r
235	\r
236	#define MmPci8And( Segment, Bus, Device, Function, Register, AndData ) \\r
237	MmPci8( Segment, Bus, Device, Function, Register ) = \\r
238	(UINT8) ( \\r
239	MmPci8( Segment, Bus, Device, Function, Register ) & \\r
240	(UINT8)(AndData) \\r
241	)\r
242	\r
243	#define MmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
244	MmPci8( Segment, Bus, Device, Function, Register ) = \\r
245	(UINT8) ( \\r
246	( MmPci8( Segment, Bus, Device, Function, Register ) & \\r
247	(UINT8)(AndData) \\r
248	) \| \\r
249	(UINT8)(OrData) \\r
250	)\r
251	\r
252	#endif\r