projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /**\r |
| 2 | \r | |
| 3 | Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r | |
| 4 | \r | |
| 7ede8060 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
6 | \r |
| 7 | \r | |
| 8 | \r | |
| 9 | @file\r | |
| 10 | PchAccess.h\r | |
| 11 | \r | |
| 12 | @brief\r | |
| 13 | Macros that simplify accessing PCH devices's PCI registers.\r | |
| 14 | \r | |
| 15 | ** NOTE ** these macros assume the PCH device is on BUS 0\r | |
| 16 | \r | |
| 17 | **/\r | |
| 18 | #ifndef _PCH_ACCESS_H_\r | |
| 19 | #define _PCH_ACCESS_H_\r | |
| 20 | \r | |
| 21 | #include "PchRegs.h"\r | |
| 22 | #include "PchCommonDefinitions.h"\r | |
| 23 | \r | |
| 24 | #ifndef STALL_ONE_MICRO_SECOND\r | |
| 25 | #define STALL_ONE_MICRO_SECOND 1\r | |
| 26 | #endif\r | |
| 27 | #ifndef STALL_ONE_SECOND\r | |
| 28 | #define STALL_ONE_SECOND 1000000\r | |
| 29 | #endif\r | |
| 30 | \r | |
| 31 | ///\r | |
| 32 | /// Memory Mapped PCI Access macros\r | |
| 33 | ///\r | |
| 34 | ///\r | |
| 35 | /// PCI Device MM Base\r | |
| 36 | ///\r | |
| 37 | #ifndef MmPciAddress\r | |
| 38 | #define MmPciAddress(Segment, Bus, Device, Function, Register) \\r | |
| 39 | ((UINTN) PatchPcdGet64 (PcdPciExpressBaseAddress) + \\r | |
| 40 | (UINTN) (Bus << 20) + \\r | |
| 41 | (UINTN) (Device << 15) + \\r | |
| 42 | (UINTN) (Function << 12) + \\r | |
| 43 | (UINTN) (Register) \\r | |
| 44 | )\r | |
| 45 | #endif\r | |
| 46 | ///\r | |
| 47 | /// Pch Controller PCI access macros\r | |
| 48 | ///\r | |
| 49 | #define PCH_RCRB_BASE ( \\r | |
| 50 | MmioRead32 (MmPciAddress (0, \\r | |
| 51 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 52 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
| 53 | PCI_FUNCTION_NUMBER_PCH_LPC), \\r | |
| 54 | R_PCH_LPC_RCBA)) & B_PCH_LPC_RCBA_BAR \\r | |
| 55 | )\r | |
| 56 | \r | |
| 57 | ///\r | |
| 58 | /// Device 0x1b, Function 0\r | |
| 59 | ///\r | |
| 60 | #define PchAzaliaPciCfg32(Register) \\r | |
| 61 | MmioRead32 ( \\r | |
| 62 | MmPciAddress (0, \\r | |
| 63 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 64 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
| 65 | 0, \\r | |
| 66 | Register) \\r | |
| 67 | )\r | |
| 68 | \r | |
| 69 | #define PchAzaliaPciCfg32Or(Register, OrData) \\r | |
| 70 | MmioOr32 ( \\r | |
| 71 | MmPciAddress (0, \\r | |
| 72 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 73 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
| 74 | 0, \\r | |
| 75 | Register), \\r | |
| 76 | OrData \\r | |
| 77 | )\r | |
| 78 | \r | |
| 79 | #define PchAzaliaPciCfg32And(Register, AndData) \\r | |
| 80 | MmioAnd32 ( \\r | |
| 81 | MmPciAddress (0, \\r | |
| 82 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 83 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
| 84 | 0, \\r | |
| 85 | Register), \\r | |
| 86 | AndData \\r | |
| 87 | )\r | |
| 88 | \r | |
| 89 | #define PchAzaliaPciCfg32AndThenOr(Register, AndData, OrData) \\r | |
| 90 | MmioAndThenOr32 ( \\r | |
| 91 | MmPciAddress (0, \\r | |
| 92 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 93 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
| 94 | 0, \\r | |
| 95 | Register), \\r | |
| 96 | OrData \\r | |
| 97 | )\r | |
| 98 | \r | |
| 99 | #define PchAzaliaPciCfg16(Register) \\r | |
| 100 | MmioRead16 ( \\r | |
| 101 | MmPciAddress (0, \\r | |
| 102 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 103 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
| 104 | 0, \\r | |
| 105 | Register) \\r | |
| 106 | )\r | |
| 107 | \r | |
| 108 | #define PchAzaliaPciCfg16Or(Register, OrData) \\r | |
| 109 | MmioOr16 ( \\r | |
| 110 | MmPciAddress (0, \\r | |
| 111 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 112 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
| 113 | 0, \\r | |
| 114 | Register), \\r | |
| 115 | OrData \\r | |
| 116 | )\r | |
| 117 | \r | |
| 118 | #define PchAzaliaPciCfg16And(Register, AndData) \\r | |
| 119 | MmioAnd16 ( \\r | |
| 120 | MmPciAddress (0, \\r | |
| 121 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 122 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
| 123 | 0, \\r | |
| 124 | Register), \\r | |
| 125 | AndData \\r | |
| 126 | )\r | |
| 127 | \r | |
| 128 | #define PchAzaliaPciCfg16AndThenOr(Register, AndData, OrData) \\r | |
| 129 | MmioAndThenOr16 ( \\r | |
| 130 | MmPciAddress (0, \\r | |
| 131 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 132 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
| 133 | 0, \\r | |
| 134 | Register), \\r | |
| 135 | AndData, \\r | |
| 136 | OrData \\r | |
| 137 | )\r | |
| 138 | \r | |
| 139 | #define PchAzaliaPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_AZALIA, 0, Register))\r | |
| 140 | \r | |
| 141 | #define PchAzaliaPciCfg8Or(Register, OrData) \\r | |
| 142 | MmioOr8 ( \\r | |
| 143 | MmPciAddress (0, \\r | |
| 144 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 145 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
| 146 | 0, \\r | |
| 147 | Register), \\r | |
| 148 | OrData \\r | |
| 149 | )\r | |
| 150 | \r | |
| 151 | #define PchAzaliaPciCfg8And(Register, AndData) \\r | |
| 152 | MmioAnd8 ( \\r | |
| 153 | MmPciAddress (0, \\r | |
| 154 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 155 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
| 156 | 0, \\r | |
| 157 | Register), \\r | |
| 158 | AndData \\r | |
| 159 | )\r | |
| 160 | \r | |
| 161 | #define PchAzaliaPciCfg8AndThenOr(Register, AndData, OrData) \\r | |
| 162 | MmioAndThenOr8 ( \\r | |
| 163 | MmPciAddress (0, \\r | |
| 164 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 165 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
| 166 | 0, \\r | |
| 167 | Register), \\r | |
| 168 | AndData, \\r | |
| 169 | OrData \\r | |
| 170 | )\r | |
| 171 | \r | |
| 172 | ///\r | |
| 173 | /// Device 0x1f, Function 0\r | |
| 174 | ///\r | |
| 175 | #define PchLpcPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))\r | |
| 176 | \r | |
| 177 | #define PchLpcMmioOr32 (Register, OrData) \\r | |
| 178 | MmioOr32 ( \\r | |
| 179 | MmPciAddress (0, \\r | |
| 180 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 181 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
| 182 | 0, \\r | |
| 183 | Register), \\r | |
| 184 | OrData \\r | |
| 185 | )\r | |
| 186 | \r | |
| 187 | #define PchLpcPciCfg32And(Register, AndData) \\r | |
| 188 | MmioAnd32 ( \\r | |
| 189 | MmPciAddress (0, \\r | |
| 190 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 191 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
| 192 | 0, \\r | |
| 193 | Register), \\r | |
| 194 | AndData \\r | |
| 195 | )\r | |
| 196 | \r | |
| 197 | #define PchLpcPciCfg32AndThenOr(Register, AndData, OrData) \\r | |
| 198 | MmioAndThenOr32 ( \\r | |
| 199 | MmPciAddress (0, \\r | |
| 200 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 201 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
| 202 | 0, \\r | |
| 203 | Register), \\r | |
| 204 | AndData, \\r | |
| 205 | OrData \\r | |
| 206 | )\r | |
| 207 | \r | |
| 208 | #define PchLpcPciCfg16(Register) MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))\r | |
| 209 | \r | |
| 210 | #define PchLpcPciCfg16Or(Register, OrData) \\r | |
| 211 | MmioOr16 ( \\r | |
| 212 | MmPciAddress (0, \\r | |
| 213 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 214 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
| 215 | 0, \\r | |
| 216 | Register), \\r | |
| 217 | OrData \\r | |
| 218 | )\r | |
| 219 | \r | |
| 220 | #define PchLpcPciCfg16And(Register, AndData) \\r | |
| 221 | MmioAndThenOr16 ( \\r | |
| 222 | MmPciAddress (0, \\r | |
| 223 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 224 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
| 225 | 0, \\r | |
| 226 | Register), \\r | |
| 227 | AndData \\r | |
| 228 | )\r | |
| 229 | \r | |
| 230 | #define PchLpcPciCfg16AndThenOr(Register, AndData, OrData) \\r | |
| 231 | MmioAndThenOr16 ( \\r | |
| 232 | MmPciAddress (0, \\r | |
| 233 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 234 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
| 235 | 0, \\r | |
| 236 | Register), \\r | |
| 237 | AndData, \\r | |
| 238 | OrData \\r | |
| 239 | )\r | |
| 240 | \r | |
| 241 | #define PchLpcPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))\r | |
| 242 | \r | |
| 243 | #define PchLpcPciCfg8Or(Register, OrData) \\r | |
| 244 | MmioOr8 ( \\r | |
| 245 | MmPciAddress (0, \\r | |
| 246 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 247 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
| 248 | 0, \\r | |
| 249 | Register), \\r | |
| 250 | OrData \\r | |
| 251 | )\r | |
| 252 | \r | |
| 253 | #define PchLpcPciCfg8And(Register, AndData) \\r | |
| 254 | MmioAnd8 ( \\r | |
| 255 | MmPciAddress (0, \\r | |
| 256 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 257 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
| 258 | 0, \\r | |
| 259 | Register), \\r | |
| 260 | AndData \\r | |
| 261 | )\r | |
| 262 | \r | |
| 263 | #define PchLpcPciCfg8AndThenOr(Register, AndData, OrData) \\r | |
| 264 | MmioAndThenOr8 ( \\r | |
| 265 | MmPciAddress (0, \\r | |
| 266 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 267 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
| 268 | 0, \\r | |
| 269 | Register), \\r | |
| 270 | AndData, \\r | |
| 271 | OrData \\r | |
| 272 | )\r | |
| 273 | \r | |
| 274 | \r | |
| 275 | ///\r | |
| 276 | /// SATA device 0x13, Function 0\r | |
| 277 | ///\r | |
| 278 | #define PchSataPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))\r | |
| 279 | \r | |
| 280 | #define PchSataPciCfg32Or(Register, OrData) \\r | |
| 281 | MmioOr32 ( \\r | |
| 282 | MmPciAddress (0, \\r | |
| 283 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 284 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
| 285 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
| 286 | Register), \\r | |
| 287 | OrData \\r | |
| 288 | )\r | |
| 289 | \r | |
| 290 | #define PchSataPciCfg32And(Register, AndData) \\r | |
| 291 | MmioAnd32 ( \\r | |
| 292 | MmPciAddress (0, \\r | |
| 293 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 294 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
| 295 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
| 296 | Register), \\r | |
| 297 | AndData \\r | |
| 298 | )\r | |
| 299 | \r | |
| 300 | #define PchSataPciCfg32AndThenOr(Register, AndData, OrData) \\r | |
| 301 | MmioAndThenOr32 ( \\r | |
| 302 | MmPciAddress (0, \\r | |
| 303 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 304 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
| 305 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
| 306 | Register), \\r | |
| 307 | AndData, \\r | |
| 308 | OrData \\r | |
| 309 | )\r | |
| 310 | \r | |
| 311 | #define PchSataPciCfg16(Register) MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))\r | |
| 312 | \r | |
| 313 | #define PchSataPciCfg16Or(Register, OrData) \\r | |
| 314 | MmioOr16 ( \\r | |
| 315 | MmPciAddress (0, \\r | |
| 316 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 317 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
| 318 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
| 319 | Register), \\r | |
| 320 | OrData \\r | |
| 321 | )\r | |
| 322 | \r | |
| 323 | #define PchSataPciCfg16And(Register, AndData) \\r | |
| 324 | MmioAndThenOr16 ( \\r | |
| 325 | MmPciAddress (0, \\r | |
| 326 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 327 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
| 328 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
| 329 | Register), \\r | |
| 330 | AndData \\r | |
| 331 | )\r | |
| 332 | \r | |
| 333 | #define PchSataPciCfg16AndThenOr(Register, AndData, OrData) \\r | |
| 334 | MmioAndThenOr16 ( \\r | |
| 335 | MmPciAddress (0, \\r | |
| 336 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 337 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
| 338 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
| 339 | Register), \\r | |
| 340 | AndData, \\r | |
| 341 | OrData \\r | |
| 342 | )\r | |
| 343 | \r | |
| 344 | #define PchSataPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))\r | |
| 345 | \r | |
| 346 | #define PchSataPciCfg8Or(Register, OrData) \\r | |
| 347 | MmioOr8 ( \\r | |
| 348 | MmPciAddress (0, \\r | |
| 349 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 350 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
| 351 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
| 352 | Register), \\r | |
| 353 | OrData \\r | |
| 354 | )\r | |
| 355 | \r | |
| 356 | #define PchSataPciCfg8And(Register, AndData) \\r | |
| 357 | MmioAnd8 ( \\r | |
| 358 | MmPciAddress (0, \\r | |
| 359 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 360 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
| 361 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
| 362 | Register), \\r | |
| 363 | AndData \\r | |
| 364 | )\r | |
| 365 | \r | |
| 366 | #define PchSataPciCfg8AndThenOr(Register, AndData, OrData) \\r | |
| 367 | MmioAndThenOr8 ( \\r | |
| 368 | MmPciAddress (0, \\r | |
| 369 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
| 370 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
| 371 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
| 372 | Register), \\r | |
| 373 | AndData, \\r | |
| 374 | OrData \\r | |
| 375 | )\r | |
| 376 | \r | |
| 377 | \r | |
| 378 | ///\r | |
| 379 | /// Root Complex Register Block\r | |
| 380 | ///\r | |
| 381 | #define PchMmRcrb32(Register) MmioRead32 (PCH_RCRB_BASE + Register)\r | |
| 382 | \r | |
| 383 | #define PchMmRcrb32Or(Register, OrData) MmioOr32 (PCH_RCRB_BASE + Register, OrData)\r | |
| 384 | \r | |
| 385 | #define PchMmRcrb32And(Register, AndData) MmioAnd32 (PCH_RCRB_BASE + Register, AndData)\r | |
| 386 | \r | |
| 387 | #define PchMmRcrb32AndThenOr(Register, AndData, OrData) MmioAndThenOr32 (PCH_RCRB_BASE + Register, AndData, OrData)\r | |
| 388 | \r | |
| 389 | #define PchMmRcrb16(Register) MmioRead16 (PCH_RCRB_BASE + Register)\r | |
| 390 | \r | |
| 391 | #define PchMmRcrb16Or(Register, OrData) MmioOr16 (PCH_RCRB_BASE + Register, OrData)\r | |
| 392 | \r | |
| 393 | #define PchMmRcrb16And(Register, AndData) MmioAnd16 (PCH_RCRB_BASE + Register, AndData)\r | |
| 394 | \r | |
| 395 | #define PchMmRcrb16AndThenOr(Register, AndData, OrData) MmioAndThenOr16 (PCH_RCRB_BASE + Register, AndData, OrData)\r | |
| 396 | \r | |
| 397 | #define PchMmRcrb8(Register) MmioRead8 (PCH_RCRB_BASE + Register)\r | |
| 398 | \r | |
| 399 | #define PchMmRcrb8Or(Register, OrData) MmioOr8 (PCH_RCRB_BASE + Register, OrData)\r | |
| 400 | \r | |
| 401 | #define PchMmRcrb8And(Register, AndData) MmioAnd8 (PCH_RCRB_BASE + Register, AndData)\r | |
| 402 | \r | |
| 403 | #define PchMmRcrb8AndThenOr(Register, AndData, OrData) MmioAndThenOr8 (PCH_RCRB_BASE + Register, AndData, OrData)\r | |
| 404 | \r | |
| 405 | \r | |
| 406 | ///\r | |
| 407 | /// Message Bus\r | |
| 408 | ///\r | |
| 409 | \r | |
| 410 | ///\r | |
| 411 | /// Message Bus Registers\r | |
| 412 | ///\r | |
| 413 | #define MC_MCR 0x000000D0 // Cunit Message Control Register\r | |
| 414 | #define MC_MDR 0x000000D4 // Cunit Message Data Register\r | |
| 415 | #define MC_MCRX 0x000000D8 // Cunit Message Control Register Extension\r | |
| 416 | \r | |
| 417 | ///\r | |
| 418 | /// Message Bus API\r | |
| 419 | ///\r | |
| 420 | #define MSG_BUS_ENABLED 0x000000F0\r | |
| 421 | #define MSGBUS_MASKHI 0xFFFFFF00\r | |
| 422 | #define MSGBUS_MASKLO 0x000000FF\r | |
| 423 | #define MESSAGE_DWORD_EN BIT4 | BIT5 | BIT6 | BIT7\r | |
| 424 | \r | |
| 425 | #define PchMsgBusRead32(PortId, Register, Dbuff, ReadOpCode, WriteOpCode) \\r | |
| 426 | { \\r | |
| 427 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r | |
| 428 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r | |
| 429 | (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \\r | |
| 430 | }\r | |
| 431 | \r | |
| 432 | #define PchMsgBusAnd32(PortId, Register, Dbuff, AndData, ReadOpCode, WriteOpCode) \\r | |
| 433 | { \\r | |
| 434 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r | |
| 435 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r | |
| 436 | (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \\r | |
| 437 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r | |
| 438 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff & AndData)); \\r | |
| 439 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r | |
| 440 | }\r | |
| 441 | \r | |
| 442 | #define PchMsgBusOr32(PortId, Register, Dbuff, OrData, ReadOpCode, WriteOpCode) \\r | |
| 443 | { \\r | |
| 444 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r | |
| 445 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r | |
| 446 | (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \\r | |
| 447 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r | |
| 448 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff | OrData)); \\r | |
| 449 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r | |
| 450 | }\r | |
| 451 | \r | |
| 452 | #define PchMsgBusAndThenOr32(PortId, Register, Dbuff, AndData, OrData, ReadOpCode, WriteOpCode) \\r | |
| 453 | { \\r | |
| 454 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r | |
| 455 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r | |
| 456 | (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \\r | |
| 457 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r | |
| 458 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) ((Dbuff & AndData) | OrData)); \\r | |
| 459 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r | |
| 460 | }\r | |
| 461 | \r | |
| 462 | typedef struct _PCH_MSG_BUS_TABLE_STRUCT {\r | |
| 463 | UINT32 PortId;\r | |
| 464 | UINT32 Address;\r | |
| 465 | UINT32 AndMask;\r | |
| 466 | UINT32 OrMask;\r | |
| 467 | UINT32 ReadOpCode;\r | |
| 468 | UINT32 WriteOpCode;\r | |
| 469 | } PCH_MSG_BUS_TABLE_STRUCT_TABLE_STRUCT;\r | |
| 470 | \r | |
| 3cbfba02 | 471 | #endif\r |