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Vlv2DeviceRefCodePkg: Replace BSD License with BSD+Patent License
[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / SouthCluster / Include / PchCommonDefinitions.h
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DW		 1/*++\r
2\r
3Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved\r
4\r
7ede8060 5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
3cbfba02
DW		 6\r
7\r
8\r
9Module Name:\r
10\r
11 PchCommonDefinitions.h\r
12\r
13Abstract:\r
14\r
15 This header file provides common definitions for PCH\r
16\r
17--*/\r
18#ifndef _PCH_COMMON_DEFINITIONS_H_\r
19#define _PCH_COMMON_DEFINITIONS_H_\r
20\r
21//\r
22// MMIO access macros\r
23//\r
24#define PchMmioAddress(BaseAddr, Register) ((UINTN) BaseAddr + (UINTN) (Register))\r
25\r
26//\r
27// 32 bit MMIO access\r
28//\r
29#define PchMmio32Ptr(BaseAddr, Register) ((volatile UINT32 *) PchMmioAddress (BaseAddr, Register))\r
30\r
31#define PchMmio32(BaseAddr, Register) *PchMmio32Ptr (BaseAddr, Register)\r
32\r
33#define PchMmio32Or(BaseAddr, Register, OrData) \\r
34 PchMmio32 (BaseAddr, Register) = (UINT32) \\r
35 (PchMmio32 (BaseAddr, Register) | (UINT32) (OrData))\r
36\r
37#define PchMmio32And(BaseAddr, Register, AndData) \\r
38 PchMmio32 (BaseAddr, Register) = (UINT32) \\r
39 (PchMmio32 (BaseAddr, Register) & (UINT32) (AndData))\r
40\r
41#define PchMmio32AndThenOr(BaseAddr, Register, AndData, OrData) \\r
42 PchMmio32 (BaseAddr, Register) = (UINT32) \\r
43 ((PchMmio32 (BaseAddr, Register) & (UINT32) (AndData)) | (UINT32) (OrData))\r
44\r
45//\r
46// 16 bit MMIO access\r
47//\r
48#define PchMmio16Ptr(BaseAddr, Register) ((volatile UINT16 *) PchMmioAddress (BaseAddr, Register))\r
49\r
50#define PchMmio16(BaseAddr, Register) *PchMmio16Ptr (BaseAddr, Register)\r
51\r
52#define PchMmio16Or(BaseAddr, Register, OrData) \\r
53 PchMmio16 (BaseAddr, Register) = (UINT16) \\r
54 (PchMmio16 (BaseAddr, Register) | (UINT16) (OrData))\r
55\r
56#define PchMmio16And(BaseAddr, Register, AndData) \\r
57 PchMmio16 (BaseAddr, Register) = (UINT16) \\r
58 (PchMmio16 (BaseAddr, Register) & (UINT16) (AndData))\r
59\r
60#define PchMmio16AndThenOr(BaseAddr, Register, AndData, OrData) \\r
61 PchMmio16 (BaseAddr, Register) = (UINT16) \\r
62 ((PchMmio16 (BaseAddr, Register) & (UINT16) (AndData)) | (UINT16) (OrData))\r
63\r
64//\r
65// 8 bit MMIO access\r
66//\r
67#define PchMmio8Ptr(BaseAddr, Register) ((volatile UINT8 *) PchMmioAddress (BaseAddr, Register))\r
68\r
69#define PchMmio8(BaseAddr, Register) *PchMmio8Ptr (BaseAddr, Register)\r
70\r
71#define PchMmio8Or(BaseAddr, Register, OrData) \\r
72 PchMmio8 (BaseAddr, Register) = (UINT8) \\r
73 (PchMmio8 (BaseAddr, Register) | (UINT8) (OrData))\r
74\r
75#define PchMmio8And(BaseAddr, Register, AndData) \\r
76 PchMmio8 (BaseAddr, Register) = (UINT8) \\r
77 (PchMmio8 (BaseAddr, Register) & (UINT8) (AndData))\r
78\r
79#define PchMmio8AndThenOr(BaseAddr, Register, AndData, OrData) \\r
80 PchMmio8 (BaseAddr, Register) = (UINT8) \\r
81 ((PchMmio8 (BaseAddr, Register) & (UINT8) (AndData)) | (UINT8) (OrData))\r
82\r
83//\r
84// Memory Mapped PCI Access macros\r
85//\r
86#define PCH_PCI_EXPRESS_BASE_ADDRESS 0xE0000000\r
87//\r
88// PCI Device MM Base\r
89//\r
90#define PchPciDeviceMmBase(Bus, Device, Function) \\r
91 ( \\r
92 (UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \\r
93 (Function << 12) \\r
94 )\r
95\r
96//\r
97// PCI Device MM Address\r
98//\r
99#define PchPciDeviceMmAddress(Segment, Bus, Device, Function, Register) \\r
100 ( \\r
101 (UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \\r
102 (Function << 12) + (UINTN) (Register) \\r
103 )\r
104\r
105//\r
106// 32 bit PCI access\r
107//\r
108#define PchMmPci32Ptr(Segment, Bus, Device, Function, Register) \\r
109 ((volatile UINT32 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))\r
110\r
111#define PchMmPci32(Segment, Bus, Device, Function, Register) *PchMmPci32Ptr (Segment, Bus, Device, Function, Register)\r
112\r
113#define PchMmPci32Or(Segment, Bus, Device, Function, Register, OrData) \\r
114 PchMmPci32 ( \\r
115 Segment, \\r
116 Bus, \\r
117 Device, \\r
118 Function, \\r
119 Register \\r
120 ) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) | (UINT32) (OrData))\r
121\r
122#define PchMmPci32And(Segment, Bus, Device, Function, Register, AndData) \\r
123 PchMmPci32 ( \\r
124 Segment, \\r
125 Bus, \\r
126 Device, \\r
127 Function, \\r
128 Register \\r
129 ) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData))\r
130\r
131#define PchMmPci32AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \\r
132 PchMmPci32 ( \\r
133 Segment, \\r
134 Bus, \\r
135 Device, \\r
136 Function, \\r
137 Register \\r
138 ) = (UINT32) ((PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData)) | (UINT32) (OrData))\r
139\r
140//\r
141// 16 bit PCI access\r
142//\r
143#define PchMmPci16Ptr(Segment, Bus, Device, Function, Register) \\r
144 ((volatile UINT16 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))\r
145\r
146#define PchMmPci16(Segment, Bus, Device, Function, Register) *PchMmPci16Ptr (Segment, Bus, Device, Function, Register)\r
147\r
148#define PchMmPci16Or(Segment, Bus, Device, Function, Register, OrData) \\r
149 PchMmPci16 ( \\r
150 Segment, \\r
151 Bus, \\r
152 Device, \\r
153 Function, \\r
154 Register \\r
155 ) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) | (UINT16) (OrData))\r
156\r
157#define PchMmPci16And(Segment, Bus, Device, Function, Register, AndData) \\r
158 PchMmPci16 ( \\r
159 Segment, \\r
160 Bus, \\r
161 Device, \\r
162 Function, \\r
163 Register \\r
164 ) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData))\r
165\r
166#define PchMmPci16AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \\r
167 PchMmPci16 ( \\r
168 Segment, \\r
169 Bus, \\r
170 Device, \\r
171 Function, \\r
172 Register \\r
173 ) = (UINT16) ((PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData)) | (UINT16) (OrData))\r
174\r
175//\r
176// 8 bit PCI access\r
177//\r
178#define PchMmPci8Ptr(Segment, Bus, Device, Function, Register) \\r
179 ((volatile UINT8 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))\r
180\r
181#define PchMmPci8(Segment, Bus, Device, Function, Register) *PchMmPci8Ptr (Segment, Bus, Device, Function, Register)\r
182\r
183#define PchMmPci8Or(Segment, Bus, Device, Function, Register, OrData) \\r
184 PchMmPci8 ( \\r
185 Segment, \\r
186 Bus, \\r
187 Device, \\r
188 Function, \\r
189 Register \\r
190 ) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) | (UINT8) (OrData))\r
191\r
192#define PchMmPci8And(Segment, Bus, Device, Function, Register, AndData) \\r
193 PchMmPci8 ( \\r
194 Segment, \\r
195 Bus, \\r
196 Device, \\r
197 Function, \\r
198 Register \\r
199 ) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData))\r
200\r
201#define PchMmPci8AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \\r
202 PchMmPci8 ( \\r
203 Segment, \\r
204 Bus, \\r
205 Device, \\r
206 Function, \\r
207 Register \\r
208 ) = (UINT8) ((PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData)) | (UINT8) (OrData))\r
209\r
210#endif\r
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