projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /*++\r |
| 2 | \r | |
| 3 | Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r | |
| 4 | \r | |
| 7ede8060 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
6 | \r |
| 7 | \r | |
| 8 | \r | |
| 9 | Module Name:\r | |
| 10 | \r | |
| 11 | PchRegsLpss.h\r | |
| 12 | \r | |
| 13 | Abstract:\r | |
| 14 | \r | |
| 15 | Register names for VLV Low Input Output (LPSS) module.\r | |
| 16 | \r | |
| 17 | Conventions:\r | |
| 18 | \r | |
| 19 | - Prefixes:\r | |
| 20 | Definitions beginning with "R_" are registers\r | |
| 21 | Definitions beginning with "B_" are bits within registers\r | |
| 22 | Definitions beginning with "V_" are meaningful values of bits within the registers\r | |
| 23 | Definitions beginning with "S_" are register sizes\r | |
| 24 | Definitions beginning with "N_" are the bit position\r | |
| 25 | - In general, PCH registers are denoted by "_PCH_" in register names\r | |
| 26 | - Registers / bits that are different between PCH generations are denoted by\r | |
| 27 | "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r | |
| 28 | - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r | |
| 29 | at the end of the register/bit names\r | |
| 30 | - Registers / bits of new devices introduced in a PCH generation will be just named\r | |
| 31 | as "_PCH_" without <generation_name> inserted.\r | |
| 32 | \r | |
| 33 | --*/\r | |
| 34 | #ifndef _PCH_REGS_LPSS_H_\r | |
| 35 | #define _PCH_REGS_LPSS_H_\r | |
| 36 | \r | |
| 37 | \r | |
| 38 | //\r | |
| 39 | // Low Power Input Output (LPSS) Module Registers\r | |
| 40 | //\r | |
| 41 | \r | |
| 42 | //\r | |
| 43 | // LPSS DMAC Modules\r | |
| 44 | // PCI Config Space Registers\r | |
| 45 | //\r | |
| 46 | #define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC0 30\r | |
| 47 | #define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC1 24\r | |
| 48 | #define PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC 0\r | |
| 49 | \r | |
| 50 | #define R_PCH_LPSS_DMAC_DEVVENDID 0x00 // Device ID & Vendor ID\r | |
| 51 | #define B_PCH_LPSS_DMAC_DEVVENDID_DID 0xFFFF0000 // Device ID\r | |
| 52 | #define B_PCH_LPSS_DMAC_DEVVENDID_VID 0x0000FFFF // Vendor ID\r | |
| 53 | \r | |
| 54 | #define R_PCH_LPSS_DMAC_STSCMD 0x04 // Status & Command\r | |
| 55 | #define B_PCH_LPSS_DMAC_STSCMD_RMA BIT29 // RMA\r | |
| 56 | #define B_PCH_LPSS_DMAC_STSCMD_RCA BIT28 // RCA\r | |
| 57 | #define B_PCH_LPSS_DMAC_STSCMD_CAPLIST BIT20 // Capability List\r | |
| 58 | #define B_PCH_LPSS_DMAC_STSCMD_INTRSTS BIT19 // Interrupt Status\r | |
| 59 | #define B_PCH_LPSS_DMAC_STSCMD_INTRDIS BIT10 // Interrupt Disable\r | |
| 60 | #define B_PCH_LPSS_DMAC_STSCMD_SERREN BIT8 // SERR# Enable\r | |
| 61 | #define B_PCH_LPSS_DMAC_STSCMD_BME BIT2 // Bus Master Enable\r | |
| 62 | #define B_PCH_LPSS_DMAC_STSCMD_MSE BIT1 // Memory Space Enable\r | |
| 63 | \r | |
| 64 | #define R_PCH_LPSS_DMAC_REVCC 0x08 // Revision ID & Class Code\r | |
| 65 | #define B_PCH_LPSS_DMAC_REVCC_CC 0xFFFFFF00 // Class Code\r | |
| 66 | #define B_PCH_LPSS_DMAC_REVCC_RID 0x000000FF // Revision ID\r | |
| 67 | \r | |
| 68 | #define R_PCH_LPSS_DMAC_CLHB 0x0C\r | |
| 69 | #define B_PCH_LPSS_DMAC_CLHB_MULFNDEV BIT23\r | |
| 70 | #define B_PCH_LPSS_DMAC_CLHB_HT 0x007F0000 // Header Type\r | |
| 71 | #define B_PCH_LPSS_DMAC_CLHB_LT 0x0000FF00 // Latency Timer\r | |
| 72 | #define B_PCH_LPSS_DMAC_CLHB_CLS 0x000000FF // Cache Line Size\r | |
| 73 | \r | |
| 74 | #define R_PCH_LPSS_DMAC_BAR 0x10 // BAR\r | |
| 75 | #define B_PCH_LPSS_DMAC_BAR_BA 0xFFFFC000 // Base Address\r | |
| 76 | #define V_PCH_LPSS_DMAC_BAR_SIZE 0x4000\r | |
| 77 | #define N_PCH_LPSS_DMAC_BAR_ALIGNMENT 14\r | |
| 78 | #define B_PCH_LPSS_DMAC_BAR_SI 0x00000FF0 // Size Indicator\r | |
| 79 | #define B_PCH_LPSS_DMAC_BAR_PF BIT3 // Prefetchable\r | |
| 80 | #define B_PCH_LPSS_DMAC_BAR_TYPE (BIT2 | BIT1) // Type\r | |
| 81 | #define B_PCH_LPSS_DMAC_BAR_MS BIT0 // Message Space\r | |
| 82 | \r | |
| 83 | #define R_PCH_LPSS_DMAC_BAR1 0x14 // BAR 1\r | |
| 84 | #define B_PCH_LPSS_DMAC_BAR1_BA 0xFFFFF000 // Base Address\r | |
| 85 | #define B_PCH_LPSS_DMAC_BAR1_SI 0x00000FF0 // Size Indicator\r | |
| 86 | #define B_PCH_LPSS_DMAC_BAR1_PF BIT3 // Prefetchable\r | |
| 87 | #define B_PCH_LPSS_DMAC_BAR1_TYPE (BIT2 | BIT1) // Type\r | |
| 88 | #define B_PCH_LPSS_DMAC_BAR1_MS BIT0 // Message Space\r | |
| 89 | \r | |
| 90 | #define R_PCH_LPSS_DMAC_SSID 0x2C // Sub System ID\r | |
| 91 | #define B_PCH_LPSS_DMAC_SSID_SID 0xFFFF0000 // Sub System ID\r | |
| 92 | #define B_PCH_LPSS_DMAC_SSID_SVID 0x0000FFFF // Sub System Vendor ID\r | |
| 93 | \r | |
| 94 | #define R_PCH_LPSS_DMAC_ERBAR 0x30 // Expansion ROM BAR\r | |
| 95 | #define B_PCH_LPSS_DMAC_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address\r | |
| 96 | \r | |
| 97 | #define R_PCH_LPSS_DMAC_CAPPTR 0x34 // Capability Pointer\r | |
| 98 | #define B_PCH_LPSS_DMAC_CAPPTR_CPPWR 0xFF // Capability Pointer Power\r | |
| 99 | \r | |
| 100 | #define R_PCH_LPSS_DMAC_INTR 0x3C // Interrupt\r | |
| 101 | #define B_PCH_LPSS_DMAC_INTR_ML 0xFF000000 // Max Latency\r | |
| 102 | #define B_PCH_LPSS_DMAC_INTR_MG 0x00FF0000\r | |
| 103 | #define B_PCH_LPSS_DMAC_INTR_IP 0x00000F00 // Interrupt Pin\r | |
| 104 | #define B_PCH_LPSS_DMAC_INTR_IL 0x000000FF // Interrupt Line\r | |
| 105 | \r | |
| 106 | #define R_PCH_LPSS_DMAC_PCAPID 0x80 // Power Capability ID\r | |
| 107 | #define B_PCH_LPSS_DMAC_PCAPID_PS 0xF8000000 // PME Support\r | |
| 108 | #define B_PCH_LPSS_DMAC_PCAPID_VS 0x00070000 // Version\r | |
| 109 | #define B_PCH_LPSS_DMAC_PCAPID_NC 0x0000FF00 // Next Capability\r | |
| 110 | #define B_PCH_LPSS_DMAC_PCAPID_PC 0x000000FF // Power Capability\r | |
| 111 | \r | |
| 112 | #define R_PCH_LPSS_DMAC_PCS 0x84 // PME Control Status\r | |
| 113 | #define B_PCH_LPSS_DMAC_PCS_PMESTS BIT15 // PME Status\r | |
| 114 | #define B_PCH_LPSS_DMAC_PCS_PMEEN BIT8 // PME Enable\r | |
| 115 | #define B_PCH_LPSS_DMAC_PCS_NSS BIT3 // No Soft Reset\r | |
| 116 | #define B_PCH_LPSS_DMAC_PCS_PS (BIT1 | BIT0) // Power State\r | |
| 117 | \r | |
| 118 | #define R_PCH_LPSS_DMAC_MANID 0xF8 // Manufacturer ID\r | |
| 119 | #define B_PCH_LPSS_DMAC_MANID_MANID 0xFFFFFFFF // Manufacturer ID\r | |
| 120 | \r | |
| 121 | \r | |
| 122 | //\r | |
| 123 | // LPSS I2C Module\r | |
| 124 | // PCI Config Space Registers\r | |
| 125 | //\r | |
| 126 | #define PCI_DEVICE_NUMBER_PCH_LPSS_I2C 24\r | |
| 127 | #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C0 1\r | |
| 128 | #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C1 2\r | |
| 129 | #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C2 3\r | |
| 130 | #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C3 4\r | |
| 131 | #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C4 5\r | |
| 132 | #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C5 6\r | |
| 133 | #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C6 7\r | |
| 134 | \r | |
| 135 | #define R_PCH_LPSS_I2C_DEVVENDID 0x00 // Device ID & Vendor ID\r | |
| 136 | #define B_PCH_LPSS_I2C_DEVVENDID_DID 0xFFFF0000 // Device ID\r | |
| 137 | #define B_PCH_LPSS_I2C_DEVVENDID_VID 0x0000FFFF // Vendor ID\r | |
| 138 | \r | |
| 139 | #define R_PCH_LPSS_I2C_STSCMD 0x04 // Status & Command\r | |
| 140 | #define B_PCH_LPSS_I2C_STSCMD_RMA BIT29 // RMA\r | |
| 141 | #define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA\r | |
| 142 | #define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List\r | |
| 143 | #define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status\r | |
| 144 | #define B_PCH_LPSS_I2C_STSCMD_INTRDIS BIT10 // Interrupt Disable\r | |
| 145 | #define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable\r | |
| 146 | #define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable\r | |
| 147 | #define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable\r | |
| 148 | \r | |
| 149 | #define R_PCH_LPSS_I2C_REVCC 0x08 // Revision ID & Class Code\r | |
| 150 | #define B_PCH_LPSS_I2C_REVCC_CC 0xFFFFFF00 // Class Code\r | |
| 151 | #define B_PCH_LPSS_I2C_REVCC_RID 0x000000FF // Revision ID\r | |
| 152 | \r | |
| 153 | #define R_PCH_LPSS_I2C_CLHB 0x0C\r | |
| 154 | #define B_PCH_LPSS_I2C_CLHB_MULFNDEV BIT23\r | |
| 155 | #define B_PCH_LPSS_I2C_CLHB_HT 0x007F0000 // Header Type\r | |
| 156 | #define B_PCH_LPSS_I2C_CLHB_LT 0x0000FF00 // Latency Timer\r | |
| 157 | #define B_PCH_LPSS_I2C_CLHB_CLS 0x000000FF // Cache Line Size\r | |
| 158 | \r | |
| 159 | #define R_PCH_LPSS_I2C_BAR 0x10 // BAR\r | |
| 160 | #define B_PCH_LPSS_I2C_BAR_BA 0xFFFFF000 // Base Address\r | |
| 161 | #define V_PCH_LPSS_I2C_BAR_SIZE 0x1000\r | |
| 162 | #define N_PCH_LPSS_I2C_BAR_ALIGNMENT 12\r | |
| 163 | #define B_PCH_LPSS_I2C_BAR_SI 0x00000FF0 // Size Indicator\r | |
| 164 | #define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable\r | |
| 165 | #define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type\r | |
| 166 | #define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space\r | |
| 167 | \r | |
| 168 | #define R_PCH_LPSS_I2C_BAR1 0x14 // BAR 1\r | |
| 169 | #define B_PCH_LPSS_I2C_BAR1_BA 0xFFFFF000 // Base Address\r | |
| 170 | #define B_PCH_LPSS_I2C_BAR1_SI 0x00000FF0 // Size Indicator\r | |
| 171 | #define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable\r | |
| 172 | #define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type\r | |
| 173 | #define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space\r | |
| 174 | \r | |
| 175 | #define R_PCH_LPSS_I2C_SSID 0x2C // Sub System ID\r | |
| 176 | #define B_PCH_LPSS_I2C_SSID_SID 0xFFFF0000 // Sub System ID\r | |
| 177 | #define B_PCH_LPSS_I2C_SSID_SVID 0x0000FFFF // Sub System Vendor ID\r | |
| 178 | \r | |
| 179 | #define R_PCH_LPSS_I2C_ERBAR 0x30 // Expansion ROM BAR\r | |
| 180 | #define B_PCH_LPSS_I2C_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address\r | |
| 181 | \r | |
| 182 | #define R_PCH_LPSS_I2C_CAPPTR 0x34 // Capability Pointer\r | |
| 183 | #define B_PCH_LPSS_I2C_CAPPTR_CPPWR 0xFF // Capability Pointer Power\r | |
| 184 | \r | |
| 185 | #define R_PCH_LPSS_I2C_INTR 0x3C // Interrupt\r | |
| 186 | #define B_PCH_LPSS_I2C_INTR_ML 0xFF000000 // Max Latency\r | |
| 187 | #define B_PCH_LPSS_I2C_INTR_MG 0x00FF0000\r | |
| 188 | #define B_PCH_LPSS_I2C_INTR_IP 0x00000F00 // Interrupt Pin\r | |
| 189 | #define B_PCH_LPSS_I2C_INTR_IL 0x000000FF // Interrupt Line\r | |
| 190 | \r | |
| 191 | #define R_PCH_LPSS_I2C_PCAPID 0x80 // Power Capability ID\r | |
| 192 | #define B_PCH_LPSS_I2C_PCAPID_PS 0xF8000000 // PME Support\r | |
| 193 | #define B_PCH_LPSS_I2C_PCAPID_VS 0x00070000 // Version\r | |
| 194 | #define B_PCH_LPSS_I2C_PCAPID_NC 0x0000FF00 // Next Capability\r | |
| 195 | #define B_PCH_LPSS_I2C_PCAPID_PC 0x000000FF // Power Capability\r | |
| 196 | \r | |
| 197 | #define R_PCH_LPSS_I2C_PCS 0x84 // PME Control Status\r | |
| 198 | #define B_PCH_LPSS_I2C_PCS_PMESTS BIT15 // PME Status\r | |
| 199 | #define B_PCH_LPSS_I2C_PCS_PMEEN BIT8 // PME Enable\r | |
| 200 | #define B_PCH_LPSS_I2C_PCS_NSS BIT3 // No Soft Reset\r | |
| 201 | #define B_PCH_LPSS_I2C_PCS_PS (BIT1 | BIT0) // Power State\r | |
| 202 | \r | |
| 203 | #define R_PCH_LPSS_I2C_MANID 0xF8 // Manufacturer ID\r | |
| 204 | #define B_PCH_LPSS_I2C_MANID_MANID 0xFFFFFFFF // Manufacturer ID\r | |
| 205 | \r | |
| 206 | //\r | |
| 207 | // LPSS I2C Module\r | |
| 208 | // Memory Space Registers\r | |
| 209 | //\r | |
| 210 | #define R_PCH_LPSS_I2C_MEM_RESETS 0x804 // Software Reset\r | |
| 211 | #define B_PCH_LPSS_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset\r | |
| 212 | #define B_PCH_LPSS_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset\r | |
| 213 | \r | |
| 214 | //\r | |
| 215 | // LPSS PWM Modules\r | |
| 216 | // PCI Config Space Registers\r | |
| 217 | //\r | |
| 218 | #define PCI_DEVICE_NUMBER_PCH_LPSS_PWM 30\r | |
| 219 | #define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM0 1\r | |
| 220 | #define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM1 2\r | |
| 221 | \r | |
| 222 | #define R_PCH_LPSS_PWM_DEVVENDID 0x00 // Device ID & Vendor ID\r | |
| 223 | #define B_PCH_LPSS_PWM_DEVVENDID_DID 0xFFFF0000 // Device ID\r | |
| 224 | #define B_PCH_LPSS_PWM_DEVVENDID_VID 0x0000FFFF // Vendor ID\r | |
| 225 | \r | |
| 226 | #define R_PCH_LPSS_PWM_STSCMD 0x04 // Status & Command\r | |
| 227 | #define B_PCH_LPSS_PWM_STSCMD_RMA BIT29 // RMA\r | |
| 228 | #define B_PCH_LPSS_PWM_STSCMD_RCA BIT28 // RCA\r | |
| 229 | #define B_PCH_LPSS_PWM_STSCMD_CAPLIST BIT20 // Capability List\r | |
| 230 | #define B_PCH_LPSS_PWM_STSCMD_INTRSTS BIT19 // Interrupt Status\r | |
| 231 | #define B_PCH_LPSS_PWM_STSCMD_INTRDIS BIT10 // Interrupt Disable\r | |
| 232 | #define B_PCH_LPSS_PWM_STSCMD_SERREN BIT8 // SERR# Enable\r | |
| 233 | #define B_PCH_LPSS_PWM_STSCMD_BME BIT2 // Bus Master Enable\r | |
| 234 | #define B_PCH_LPSS_PWM_STSCMD_MSE BIT1 // Memory Space Enable\r | |
| 235 | \r | |
| 236 | #define R_PCH_LPSS_PWM_REVCC 0x08 // Revision ID & Class Code\r | |
| 237 | #define B_PCH_LPSS_PWM_REVCC_CC 0xFFFFFF00 // Class Code\r | |
| 238 | #define B_PCH_LPSS_PWM_REVCC_RID 0x000000FF // Revision ID\r | |
| 239 | \r | |
| 240 | #define R_PCH_LPSS_PWM_CLHB 0x0C\r | |
| 241 | #define B_PCH_LPSS_PWM_CLHB_MULFNDEV BIT23\r | |
| 242 | #define B_PCH_LPSS_PWM_CLHB_HT 0x007F0000 // Header Type\r | |
| 243 | #define B_PCH_LPSS_PWM_CLHB_LT 0x0000FF00 // Latency Timer\r | |
| 244 | #define B_PCH_LPSS_PWM_CLHB_CLS 0x000000FF // Cache Line Size\r | |
| 245 | \r | |
| 246 | #define R_PCH_LPSS_PWM_BAR 0x10 // BAR\r | |
| 247 | #define B_PCH_LPSS_PWM_BAR_BA 0xFFFFF000 // Base Address\r | |
| 248 | #define V_PCH_LPSS_PWM_BAR_SIZE 0x1000\r | |
| 249 | #define N_PCH_LPSS_PWM_BAR_ALIGNMENT 12\r | |
| 250 | #define B_PCH_LPSS_PWM_BAR_SI 0x00000FF0 // Size Indicator\r | |
| 251 | #define B_PCH_LPSS_PWM_BAR_PF BIT3 // Prefetchable\r | |
| 252 | #define B_PCH_LPSS_PWM_BAR_TYPE (BIT2 | BIT1) // Type\r | |
| 253 | #define B_PCH_LPSS_PWM_BAR_MS BIT0 // Message Space\r | |
| 254 | \r | |
| 255 | #define R_PCH_LPSS_PWM_BAR1 0x14 // BAR 1\r | |
| 256 | #define B_PCH_LPSS_PWM_BAR1_BA 0xFFFFF000 // Base Address\r | |
| 257 | #define B_PCH_LPSS_PWM_BAR1_SI 0x00000FF0 // Size Indicator\r | |
| 258 | #define B_PCH_LPSS_PWM_BAR1_PF BIT3 // Prefetchable\r | |
| 259 | #define B_PCH_LPSS_PWM_BAR1_TYPE (BIT2 | BIT1) // Type\r | |
| 260 | #define B_PCH_LPSS_PWM_BAR1_MS BIT0 // Message Space\r | |
| 261 | \r | |
| 262 | #define R_PCH_LPSS_PWM_SSID 0x2C // Sub System ID\r | |
| 263 | #define B_PCH_LPSS_PWM_SSID_SID 0xFFFF0000 // Sub System ID\r | |
| 264 | #define B_PCH_LPSS_PWM_SSID_SVID 0x0000FFFF // Sub System Vendor ID\r | |
| 265 | \r | |
| 266 | #define R_PCH_LPSS_PWM_ERBAR 0x30 // Expansion ROM BAR\r | |
| 267 | #define B_PCH_LPSS_PWM_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address\r | |
| 268 | \r | |
| 269 | #define R_PCH_LPSS_PWM_CAPPTR 0x34 // Capability Pointer\r | |
| 270 | #define B_PCH_LPSS_PWM_CAPPTR_CPPWR 0xFF // Capability Pointer Power\r | |
| 271 | \r | |
| 272 | #define R_PCH_LPSS_PWM_INTR 0x3C // Interrupt\r | |
| 273 | #define B_PCH_LPSS_PWM_INTR_ML 0xFF000000 // Max Latency\r | |
| 274 | #define B_PCH_LPSS_PWM_INTR_MG 0x00FF0000\r | |
| 275 | #define B_PCH_LPSS_PWM_INTR_IP 0x00000F00 // Interrupt Pin\r | |
| 276 | #define B_PCH_LPSS_PWM_INTR_IL 0x000000FF // Interrupt Line\r | |
| 277 | \r | |
| 278 | #define R_PCH_LPSS_PWM_PCAPID 0x80 // Power Capability ID\r | |
| 279 | #define B_PCH_LPSS_PWM_PCAPID_PS 0xF8000000 // PME Support\r | |
| 280 | #define B_PCH_LPSS_PWM_PCAPID_VS 0x00070000 // Version\r | |
| 281 | #define B_PCH_LPSS_PWM_PCAPID_NC 0x0000FF00 // Next Capability\r | |
| 282 | #define B_PCH_LPSS_PWM_PCAPID_PC 0x000000FF // Power Capability\r | |
| 283 | \r | |
| 284 | #define R_PCH_LPSS_PWM_PCS 0x84 // PME Control Status\r | |
| 285 | #define B_PCH_LPSS_PWM_PCS_PMESTS BIT15 // PME Status\r | |
| 286 | #define B_PCH_LPSS_PWM_PCS_PMEEN BIT8 // PME Enable\r | |
| 287 | #define B_PCH_LPSS_PWM_PCS_NSS BIT3 // No Soft Reset\r | |
| 288 | #define B_PCH_LPSS_PWM_PCS_PS (BIT1 | BIT0) // Power State\r | |
| 289 | \r | |
| 290 | #define R_PCH_LPSS_PWM_MANID 0xF8 // Manufacturer ID\r | |
| 291 | #define B_PCH_LPSS_PWM_MANID_MANID 0xFFFFFFFF // Manufacturer ID\r | |
| 292 | \r | |
| 293 | //\r | |
| 294 | // LPSS PWM Module\r | |
| 295 | // Memory Space Registers\r | |
| 296 | //\r | |
| 297 | #define R_PCH_LPSS_PWM_MEM_RESETS 0x804 // Software Reset\r | |
| 298 | #define B_PCH_LPSS_PWM_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset\r | |
| 299 | #define B_PCH_LPSS_PWM_MEM_RESETS_APB BIT0 // APB Domain Reset\r | |
| 300 | \r | |
| 301 | //\r | |
| 302 | // LPSS HSUART Modules\r | |
| 303 | // PCI Config Space Registers\r | |
| 304 | //\r | |
| 305 | #define PCI_DEVICE_NUMBER_PCH_LPSS_HSUART 30\r | |
| 306 | #define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART0 3\r | |
| 307 | #define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART1 4\r | |
| 308 | \r | |
| 309 | #define R_PCH_LPSS_HSUART_DEVVENDID 0x00 // Device ID & Vendor ID\r | |
| 310 | #define B_PCH_LPSS_HSUART_DEVVENDID_DID 0xFFFF0000 // Device ID\r | |
| 311 | #define B_PCH_LPSS_HSUART_DEVVENDID_VID 0x0000FFFF // Vendor ID\r | |
| 312 | \r | |
| 313 | #define R_PCH_LPSS_HSUART_STSCMD 0x04 // Status & Command\r | |
| 314 | #define B_PCH_LPSS_HSUART_STSCMD_RMA BIT29 // RMA\r | |
| 315 | #define B_PCH_LPSS_HSUART_STSCMD_RCA BIT28 // RCA\r | |
| 316 | #define B_PCH_LPSS_HSUART_STSCMD_CAPLIST BIT20 // Capability List\r | |
| 317 | #define B_PCH_LPSS_HSUART_STSCMD_INTRSTS BIT19 // Interrupt Status\r | |
| 318 | #define B_PCH_LPSS_HSUART_STSCMD_INTRDIS BIT10 // Interrupt Disable\r | |
| 319 | #define B_PCH_LPSS_HSUART_STSCMD_SERREN BIT8 // SERR# Enable\r | |
| 320 | #define B_PCH_LPSS_HSUART_STSCMD_BME BIT2 // Bus Master Enable\r | |
| 321 | #define B_PCH_LPSS_HSUART_STSCMD_MSE BIT1 // Memory Space Enable\r | |
| 322 | \r | |
| 323 | #define R_PCH_LPSS_HSUART_REVCC 0x08 // Revision ID & Class Code\r | |
| 324 | #define B_PCH_LPSS_HSUART_REVCC_CC 0xFFFFFF00 // Class Code\r | |
| 325 | #define B_PCH_LPSS_HSUART_REVCC_RID 0x000000FF // Revision ID\r | |
| 326 | \r | |
| 327 | #define R_PCH_LPSS_HSUART_CLHB 0x0C\r | |
| 328 | #define B_PCH_LPSS_HSUART_CLHB_MULFNDEV BIT23\r | |
| 329 | #define B_PCH_LPSS_HSUART_CLHB_HT 0x007F0000 // Header Type\r | |
| 330 | #define B_PCH_LPSS_HSUART_CLHB_LT 0x0000FF00 // Latency Timer\r | |
| 331 | #define B_PCH_LPSS_HSUART_CLHB_CLS 0x000000FF // Cache Line Size\r | |
| 332 | \r | |
| 333 | #define R_PCH_LPSS_HSUART_BAR 0x10 // BAR\r | |
| 334 | #define B_PCH_LPSS_HSUART_BAR_BA 0xFFFFF000 // Base Address\r | |
| 335 | #define V_PCH_LPSS_HSUART_BAR_SIZE 0x1000\r | |
| 336 | #define N_PCH_LPSS_HSUART_BAR_ALIGNMENT 12\r | |
| 337 | #define B_PCH_LPSS_HSUART_BAR_SI 0x00000FF0 // Size Indicator\r | |
| 338 | #define B_PCH_LPSS_HSUART_BAR_PF BIT3 // Prefetchable\r | |
| 339 | #define B_PCH_LPSS_HSUART_BAR_TYPE (BIT2 | BIT1) // Type\r | |
| 340 | #define B_PCH_LPSS_HSUART_BAR_MS BIT0 // Message Space\r | |
| 341 | \r | |
| 342 | #define R_PCH_LPSS_HSUART_BAR1 0x14 // BAR 1\r | |
| 343 | #define B_PCH_LPSS_HSUART_BAR1_BA 0xFFFFF000 // Base Address\r | |
| 344 | #define B_PCH_LPSS_HSUART_BAR1_SI 0x00000FF0 // Size Indicator\r | |
| 345 | #define B_PCH_LPSS_HSUART_BAR1_PF BIT3 // Prefetchable\r | |
| 346 | #define B_PCH_LPSS_HSUART_BAR1_TYPE (BIT2 | BIT1) // Type\r | |
| 347 | #define B_PCH_LPSS_HSUART_BAR1_MS BIT0 // Message Space\r | |
| 348 | \r | |
| 349 | #define R_PCH_LPSS_HSUART_SSID 0x2C // Sub System ID\r | |
| 350 | #define B_PCH_LPSS_HSUART_SSID_SID 0xFFFF0000 // Sub System ID\r | |
| 351 | #define B_PCH_LPSS_HSUART_SSID_SVID 0x0000FFFF // Sub System Vendor ID\r | |
| 352 | \r | |
| 353 | #define R_PCH_LPSS_HSUART_ERBAR 0x30 // Expansion ROM BAR\r | |
| 354 | #define B_PCH_LPSS_HSUART_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address\r | |
| 355 | \r | |
| 356 | #define R_PCH_LPSS_HSUART_CAPPTR 0x34 // Capability Pointer\r | |
| 357 | #define B_PCH_LPSS_HSUART_CAPPTR_CPPWR 0xFF // Capability Pointer Power\r | |
| 358 | \r | |
| 359 | #define R_PCH_LPSS_HSUART_INTR 0x3C // Interrupt\r | |
| 360 | #define B_PCH_LPSS_HSUART_INTR_ML 0xFF000000 // Max Latency\r | |
| 361 | #define B_PCH_LPSS_HSUART_INTR_MG 0x00FF0000\r | |
| 362 | #define B_PCH_LPSS_HSUART_INTR_IP 0x00000F00 // Interrupt Pin\r | |
| 363 | #define B_PCH_LPSS_HSUART_INTR_IL 0x000000FF // Interrupt Line\r | |
| 364 | \r | |
| 365 | #define R_PCH_LPSS_HSUART_PCAPID 0x80 // Power Capability ID\r | |
| 366 | #define B_PCH_LPSS_HSUART_PCAPID_PS 0xF8000000 // PME Support\r | |
| 367 | #define B_PCH_LPSS_HSUART_PCAPID_VS 0x00070000 // Version\r | |
| 368 | #define B_PCH_LPSS_HSUART_PCAPID_NC 0x0000FF00 // Next Capability\r | |
| 369 | #define B_PCH_LPSS_HSUART_PCAPID_PC 0x000000FF // Power Capability\r | |
| 370 | \r | |
| 371 | #define R_PCH_LPSS_HSUART_PCS 0x84 // PME Control Status\r | |
| 372 | #define B_PCH_LPSS_HSUART_PCS_PMESTS BIT15 // PME Status\r | |
| 373 | #define B_PCH_LPSS_HSUART_PCS_PMEEN BIT8 // PME Enable\r | |
| 374 | #define B_PCH_LPSS_HSUART_PCS_NSS BIT3 // No Soft Reset\r | |
| 375 | #define B_PCH_LPSS_HSUART_PCS_PS (BIT1 | BIT0) // Power State\r | |
| 376 | \r | |
| 377 | #define R_PCH_LPSS_HSUART_MANID 0xF8 // Manufacturer ID\r | |
| 378 | #define B_PCH_LPSS_HSUART_MANID_MANID 0xFFFFFFFF // Manufacturer ID\r | |
| 379 | \r | |
| 380 | //\r | |
| 381 | // LPSS HSUART Module\r | |
| 382 | // Memory Space Registers\r | |
| 383 | //\r | |
| 384 | #define R_PCH_LPSS_HSUART_MEM_PCP 0x800 // Private Clock Parameters\r | |
| 385 | #define B_PCH_LPSS_HSUART_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update\r | |
| 386 | #define B_PCH_LPSS_HSUART_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider\r | |
| 387 | #define B_PCH_LPSS_HSUART_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider\r | |
| 388 | #define B_PCH_LPSS_HSUART_MEM_PCP_CLKEN BIT0 // Clock Enable\r | |
| 389 | \r | |
| 390 | #define R_PCH_LPSS_HSUART_MEM_RESETS 0x804 // Software Reset\r | |
| 391 | #define B_PCH_LPSS_HSUART_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset\r | |
| 392 | #define B_PCH_LPSS_HSUART_MEM_RESETS_APB BIT0 // APB Domain Reset\r | |
| 393 | \r | |
| 394 | //\r | |
| 395 | // LPSS SPI Module\r | |
| 396 | // PCI Config Space Registers\r | |
| 397 | //\r | |
| 398 | #define PCI_DEVICE_NUMBER_PCH_LPSS_SPI 30\r | |
| 399 | #define PCI_FUNCTION_NUMBER_PCH_LPSS_SPI 5\r | |
| 400 | \r | |
| 401 | #define R_PCH_LPSS_SPI_DEVVENDID 0x00 // Device ID & Vendor ID\r | |
| 402 | #define B_PCH_LPSS_SPI_DEVVENDID_DID 0xFFFF0000 // Device ID\r | |
| 403 | #define B_PCH_LPSS_SPI_DEVVENDID_VID 0x0000FFFF // Vendor ID\r | |
| 404 | \r | |
| 405 | #define R_PCH_LPSS_SPI_STSCMD 0x04 // Status & Command\r | |
| 406 | #define B_PCH_LPSS_SPI_STSCMD_RMA BIT29 // RMA\r | |
| 407 | #define B_PCH_LPSS_SPI_STSCMD_RCA BIT28 // RCA\r | |
| 408 | #define B_PCH_LPSS_SPI_STSCMD_CAPLIST BIT20 // Capability List\r | |
| 409 | #define B_PCH_LPSS_SPI_STSCMD_INTRSTS BIT19 // Interrupt Status\r | |
| 410 | #define B_PCH_LPSS_SPI_STSCMD_INTRDIS BIT10 // Interrupt Disable\r | |
| 411 | #define B_PCH_LPSS_SPI_STSCMD_SERREN BIT8 // SERR# Enable\r | |
| 412 | #define B_PCH_LPSS_SPI_STSCMD_BME BIT2 // Bus Master Enable\r | |
| 413 | #define B_PCH_LPSS_SPI_STSCMD_MSE BIT1 // Memory Space Enable\r | |
| 414 | \r | |
| 415 | #define R_PCH_LPSS_SPI_REVCC 0x08 // Revision ID & Class Code\r | |
| 416 | #define B_PCH_LPSS_SPI_REVCC_CC 0xFFFFFF00 // Class Code\r | |
| 417 | #define B_PCH_LPSS_SPI_REVCC_RID 0x000000FF // Revision ID\r | |
| 418 | \r | |
| 419 | #define R_PCH_LPSS_SPI_CLHB 0x0C\r | |
| 420 | #define B_PCH_LPSS_SPI_CLHB_MULFNDEV BIT23\r | |
| 421 | #define B_PCH_LPSS_SPI_CLHB_HT 0x007F0000 // Header Type\r | |
| 422 | #define B_PCH_LPSS_SPI_CLHB_LT 0x0000FF00 // Latency Timer\r | |
| 423 | #define B_PCH_LPSS_SPI_CLHB_CLS 0x000000FF // Cache Line Size\r | |
| 424 | \r | |
| 425 | #define R_PCH_LPSS_SPI_BAR 0x10 // BAR\r | |
| 426 | #define B_PCH_LPSS_SPI_BAR_BA 0xFFFFF000 // Base Address\r | |
| 427 | #define V_PCH_LPSS_SPI_BAR_SIZE 0x1000\r | |
| 428 | #define N_PCH_LPSS_SPI_BAR_ALIGNMENT 12\r | |
| 429 | #define B_PCH_LPSS_SPI_BAR_SI 0x00000FF0 // Size Indicator\r | |
| 430 | #define B_PCH_LPSS_SPI_BAR_PF BIT3 // Prefetchable\r | |
| 431 | #define B_PCH_LPSS_SPI_BAR_TYPE (BIT2 | BIT1) // Type\r | |
| 432 | #define B_PCH_LPSS_SPI_BAR_MS BIT0 // Message Space\r | |
| 433 | \r | |
| 434 | #define R_PCH_LPSS_SPI_BAR1 0x14 // BAR 1\r | |
| 435 | #define B_PCH_LPSS_SPI_BAR1_BA 0xFFFFF000 // Base Address\r | |
| 436 | #define B_PCH_LPSS_SPI_BAR1_SI 0x00000FF0 // Size Indicator\r | |
| 437 | #define B_PCH_LPSS_SPI_BAR1_PF BIT3 // Prefetchable\r | |
| 438 | #define B_PCH_LPSS_SPI_BAR1_TYPE (BIT2 | BIT1) // Type\r | |
| 439 | #define B_PCH_LPSS_SPI_BAR1_MS BIT0 // Message Space\r | |
| 440 | \r | |
| 441 | #define R_PCH_LPSS_SPI_SSID 0x2C // Sub System ID\r | |
| 442 | #define B_PCH_LPSS_SPI_SSID_SID 0xFFFF0000 // Sub System ID\r | |
| 443 | #define B_PCH_LPSS_SPI_SSID_SVID 0x0000FFFF // Sub System Vendor ID\r | |
| 444 | \r | |
| 445 | #define R_PCH_LPSS_SPI_ERBAR 0x30 // Expansion ROM BAR\r | |
| 446 | #define B_PCH_LPSS_SPI_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address\r | |
| 447 | \r | |
| 448 | #define R_PCH_LPSS_SPI_CAPPTR 0x34 // Capability Pointer\r | |
| 449 | #define B_PCH_LPSS_SPI_CAPPTR_CPPWR 0xFF // Capability Pointer Power\r | |
| 450 | \r | |
| 451 | #define R_PCH_LPSS_SPI_INTR 0x3C // Interrupt\r | |
| 452 | #define B_PCH_LPSS_SPI_INTR_ML 0xFF000000 // Max Latency\r | |
| 453 | #define B_PCH_LPSS_SPI_INTR_MG 0x00FF0000\r | |
| 454 | #define B_PCH_LPSS_SPI_INTR_IP 0x00000F00 // Interrupt Pin\r | |
| 455 | #define B_PCH_LPSS_SPI_INTR_IL 0x000000FF // Interrupt Line\r | |
| 456 | \r | |
| 457 | #define R_PCH_LPSS_SPI_PCAPID 0x80 // Power Capability ID\r | |
| 458 | #define B_PCH_LPSS_SPI_PCAPID_PS 0xF8000000 // PME Support\r | |
| 459 | #define B_PCH_LPSS_SPI_PCAPID_VS 0x00070000 // Version\r | |
| 460 | #define B_PCH_LPSS_SPI_PCAPID_NC 0x0000FF00 // Next Capability\r | |
| 461 | #define B_PCH_LPSS_SPI_PCAPID_PC 0x000000FF // Power Capability\r | |
| 462 | \r | |
| 463 | #define R_PCH_LPSS_SPI_PCS 0x84 // PME Control Status\r | |
| 464 | #define B_PCH_LPSS_SPI_PCS_PMESTS BIT15 // PME Status\r | |
| 465 | #define B_PCH_LPSS_SPI_PCS_PMEEN BIT8 // PME Enable\r | |
| 466 | #define B_PCH_LPSS_SPI_PCS_NSS BIT3 // No Soft Reset\r | |
| 467 | #define B_PCH_LPSS_SPI_PCS_PS (BIT1 | BIT0) // Power State\r | |
| 468 | \r | |
| 469 | #define R_PCH_LPSS_SPI_MANID 0xF8 // Manufacturer ID\r | |
| 470 | #define B_PCH_LPSS_SPI_MANID_MANID 0xFFFFFFFF // Manufacturer ID\r | |
| 471 | \r | |
| 472 | //\r | |
| 473 | // LPSS SPI Module\r | |
| 474 | // Memory Space Registers\r | |
| 475 | //\r | |
| 476 | #define R_PCH_LPSS_SPI_MEM_PCP 0x400 // Private Clock Parameters\r | |
| 477 | #define B_PCH_LPSS_SPI_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update\r | |
| 478 | #define B_PCH_LPSS_SPI_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider\r | |
| 479 | #define B_PCH_LPSS_SPI_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider\r | |
| 480 | #define B_PCH_LPSS_SPI_MEM_PCP_CLKEN BIT0 // Clock Enable\r | |
| 481 | \r | |
| 482 | #define R_PCH_LPSS_SPI_MEM_RESETS 0x404 // Software Reset\r | |
| 483 | #define B_PCH_LPSS_SPI_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset\r | |
| 484 | #define B_PCH_LPSS_SPI_MEM_RESETS_APB BIT0 // APB Domain Reset\r | |
| 485 | \r | |
| 486 | #endif\r |