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3cbfba02 DW |
1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r | |
4 | \r | |
7ede8060 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
3cbfba02 DW |
6 | \r |
7 | \r | |
8 | \r | |
9 | Module Name:\r | |
10 | \r | |
11 | PchRegsScc.h\r | |
12 | \r | |
13 | Abstract:\r | |
14 | \r | |
15 | Register names for VLV SCC module.\r | |
16 | \r | |
17 | Conventions:\r | |
18 | \r | |
19 | - Prefixes:\r | |
20 | Definitions beginning with "R_" are registers\r | |
21 | Definitions beginning with "B_" are bits within registers\r | |
22 | Definitions beginning with "V_" are meaningful values of bits within the registers\r | |
23 | Definitions beginning with "S_" are register sizes\r | |
24 | Definitions beginning with "N_" are the bit position\r | |
25 | - In general, PCH registers are denoted by "_PCH_" in register names\r | |
26 | - Registers / bits that are different between PCH generations are denoted by\r | |
27 | "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r | |
28 | - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r | |
29 | at the end of the register/bit names\r | |
30 | - Registers / bits of new devices introduced in a PCH generation will be just named\r | |
31 | as "_PCH_" without <generation_name> inserted.\r | |
32 | \r | |
33 | --*/\r | |
34 | #ifndef _PCH_REGS_SCC_H_\r | |
35 | #define _PCH_REGS_SCC_H_\r | |
36 | \r | |
37 | \r | |
38 | //\r | |
39 | // SCC Modules Registers\r | |
40 | //\r | |
41 | \r | |
42 | //\r | |
43 | // SCC SDIO Modules\r | |
44 | // PCI Config Space Registers\r | |
45 | //\r | |
46 | #define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_0 16\r | |
47 | #define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_1 17\r | |
48 | #define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_2 18\r | |
49 | #define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_3 23\r | |
50 | \r | |
51 | #define PCI_FUNCTION_NUMBER_PCH_SCC_SDIO 0\r | |
52 | \r | |
53 | #endif\r |