projects / mirror_edk2.git / blame
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|---|---|---|
| 3cbfba02 DW |
1 | /**\r |
| 2 | **/\r | |
| 3 | /**\r | |
| 4 | \r | |
| 5 | Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r | |
| 6 | \r | |
| 7ede8060 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
8 | \r |
| 9 | \r | |
| 10 | \r | |
| 11 | @file\r | |
| 12 | Spi.h\r | |
| 13 | \r | |
| 14 | @brief\r | |
| 15 | This file defines the EFI SPI PPI which implements the\r | |
| 16 | Intel(R) PCH SPI Host Controller Compatibility Interface.\r | |
| 17 | \r | |
| 18 | **/\r | |
| 19 | #ifndef _PEI_SDHC_H_\r | |
| 20 | #define _PEI_SDHC_H_\r | |
| 21 | \r | |
| 22 | \r | |
| 23 | \r | |
| 24 | //\r | |
| 25 | #define PEI_SDHC_PPI_GUID \\r | |
| 26 | { \\r | |
| 27 | 0xf4ef9d7a, 0x98c5, 0x4c1a, 0xb4, 0xd9, 0xd8, 0xd8, 0x72, 0x65, 0xbe, 0xc \\r | |
| 28 | }\r | |
| 29 | typedef struct _PEI_SD_CONTROLLER_PPI PEI_SD_CONTROLLER_PPI;\r | |
| 30 | \r | |
| 31 | #define EFI_SD_HOST_IO_PROTOCOL_REVISION_01 0x01\r | |
| 32 | \r | |
| 33 | typedef enum {\r | |
| 34 | ResponseNo = 0,\r | |
| 35 | ResponseR1,\r | |
| 36 | ResponseR1b,\r | |
| 37 | ResponseR2,\r | |
| 38 | ResponseR3,\r | |
| 39 | ResponseR4,\r | |
| 40 | ResponseR5,\r | |
| 41 | ResponseR5b,\r | |
| 42 | ResponseR6,\r | |
| 43 | ResponseR7\r | |
| 44 | } RESPONSE_TYPE;\r | |
| 45 | \r | |
| 46 | typedef enum {\r | |
| 47 | NoData = 0,\r | |
| 48 | InData,\r | |
| 49 | OutData\r | |
| 50 | } TRANSFER_TYPE;\r | |
| 51 | \r | |
| 52 | typedef enum {\r | |
| 53 | Reset_Auto = 0,\r | |
| 54 | Reset_DAT,\r | |
| 55 | Reset_CMD,\r | |
| 56 | Reset_DAT_CMD,\r | |
| 57 | Reset_All\r | |
| 58 | } RESET_TYPE;\r | |
| 59 | \r | |
| 60 | \r | |
| 61 | \r | |
| 62 | typedef enum {\r | |
| 63 | SDMA = 0,\r | |
| 64 | ADMA2,\r | |
| 65 | PIO\r | |
| 66 | } DMA_MOD;\r | |
| 67 | \r | |
| 68 | typedef struct {\r | |
| 69 | UINT32 HighSpeedSupport: 1; //High speed supported\r | |
| 70 | UINT32 V18Support: 1; //1.8V supported\r | |
| 71 | UINT32 V30Support: 1; //3.0V supported\r | |
| 72 | UINT32 V33Support: 1; //3.3V supported\r | |
| 73 | UINT32 Reserved0: 4;\r | |
| 74 | UINT32 BusWidth4: 1; // 4 bit width\r | |
| 75 | UINT32 BusWidth8: 1; // 8 bit width\r | |
| 76 | UINT32 Reserved1: 6;\r | |
| 77 | UINT32 SDMASupport: 1;\r | |
| 78 | UINT32 ADMA2Support: 1;\r | |
| 79 | UINT32 DmaMode: 2;\r | |
| 80 | UINT32 Reserved2: 12;\r | |
| 81 | UINT32 BoundarySize;\r | |
| 82 | }HOST_CAPABILITY;\r | |
| 83 | \r | |
| 84 | \r | |
| 85 | #define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05\r | |
| 86 | #define PCI_IF_STANDARD_HOST_NO_DMA 0x00\r | |
| 87 | #define PCI_IF_STANDARD_HOST_SUPPORT_DMA 0x01\r | |
| 88 | \r | |
| 89 | //\r | |
| 90 | //MMIO Registers definition for MMC/SDIO controller\r | |
| 91 | //\r | |
| 92 | #define MMIO_DMAADR 0x00\r | |
| 93 | #define MMIO_BLKSZ 0x04\r | |
| 94 | #define MMIO_BLKCNT 0x06\r | |
| 95 | #define MMIO_CMDARG 0x08\r | |
| 96 | #define MMIO_XFRMODE 0x0C\r | |
| 97 | #define MMIO_SDCMD 0x0E\r | |
| 98 | #define MMIO_RESP 0x10\r | |
| 99 | #define MMIO_BUFDATA 0x20\r | |
| 100 | #define MMIO_PSTATE 0x24\r | |
| 101 | #define MMIO_HOSTCTL 0x28\r | |
| 102 | #define MMIO_PWRCTL 0x29\r | |
| 103 | #define MMIO_BLKGAPCTL 0x2A\r | |
| 104 | #define MMIO_WAKECTL 0x2B\r | |
| 105 | #define MMIO_CLKCTL 0x2C\r | |
| 106 | #define MMIO_TOCTL 0x2E\r | |
| 107 | #define MMIO_SWRST 0x2F\r | |
| 108 | #define MMIO_NINTSTS 0x30\r | |
| 109 | #define MMIO_ERINTSTS 0x32\r | |
| 110 | #define MMIO_NINTEN 0x34\r | |
| 111 | #define MMIO_ERINTEN 0x36\r | |
| 112 | #define MMIO_NINTSIGEN 0x38\r | |
| 113 | #define MMIO_ERINTSIGEN 0x3A\r | |
| 114 | #define MMIO_AC12ERRSTS 0x3C\r | |
| 115 | #define MMIO_HOST_CTL2 0x3E //hphang <- New in VLV2\r | |
| 116 | #define MMIO_CAP 0x40\r | |
| 117 | #define MMIO_CAP2 0x44 //hphang <- New in VLV2\r | |
| 118 | #define MMIO_MCCAP 0x48\r | |
| 119 | #define MMIO_FORCEEVENTCMD12ERRSTAT 0x50 //hphang <- New in VLV2\r | |
| 120 | #define MMIO_FORCEEVENTERRINTSTAT 0x52 //hphang <- New in VLV2\r | |
| 121 | #define MMIO_ADMAERRSTAT 0x54 //hphang <- New in VLV2\r | |
| 122 | #define MMIO_ADMASYSADDR 0x58 //hphang <- New in VLV2\r | |
| 123 | #define MMIO_PRESETVALUE0 0x60 //hphang <- New in VLV2\r | |
| 124 | #define MMIO_PRESETVALUE1 0x64 //hphang <- New in VLV2\r | |
| 125 | #define MMIO_PRESETVALUE2 0x68 //hphang <- New in VLV2\r | |
| 126 | #define MMIO_PRESETVALUE3 0x6C //hphang <- New in VLV2\r | |
| 127 | #define MMIO_BOOTTIMEOUTCTRL 0x70 //hphang <- New in VLV2\r | |
| 128 | #define MMIO_DEBUGSEL 0x74 //hphang <- New in VLV2\r | |
| 129 | #define MMIO_SHAREDBUS 0xE0 //hphang <- New in VLV2\r | |
| 130 | #define MMIO_SPIINTSUP 0xF0 //hphang <- New in VLV2\r | |
| 131 | #define MMIO_SLTINTSTS 0xFC\r | |
| 132 | #define MMIO_CTRLRVER 0xFE\r | |
| 133 | #define MMIO_SRST 0x1FC\r | |
| 134 | \r | |
| 135 | typedef\r | |
| 136 | EFI_STATUS\r | |
| 137 | (EFIAPI *EFI_SD_CONTROLLER_PPI_SEND_COMMAND) (\r | |
| 138 | IN PEI_SD_CONTROLLER_PPI *This,\r | |
| 139 | IN UINT16 CommandIndex,\r | |
| 140 | IN UINT32 Argument,\r | |
| 141 | IN TRANSFER_TYPE DataType,\r | |
| 142 | IN UINT8 *Buffer, OPTIONAL\r | |
| 143 | IN UINT32 BufferSize,\r | |
| 144 | IN RESPONSE_TYPE ResponseType,\r | |
| 145 | IN UINT32 TimeOut,\r | |
| 146 | OUT UINT32 *ResponseData OPTIONAL\r | |
| 147 | );\r | |
| 148 | \r | |
| 149 | /*++\r | |
| 150 | \r | |
| 151 | Routine Description:\r | |
| 152 | Set max clock frequency of the host, the actual frequency\r | |
| 153 | may not be the same as MaxFrequency. It depends on\r | |
| 154 | the max frequency the host can support, divider, and host\r | |
| 155 | speed mode.\r | |
| 156 | \r | |
| 157 | Arguments:\r | |
| 158 | This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r | |
| 159 | MaxFrequency - Max frequency in HZ\r | |
| 160 | \r | |
| 161 | Returns:\r | |
| 162 | EFI_SUCCESS\r | |
| 163 | EFI_TIMEOUT\r | |
| 164 | --*/\r | |
| 165 | typedef\r | |
| 166 | EFI_STATUS\r | |
| 167 | (EFIAPI *EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY) (\r | |
| 168 | IN PEI_SD_CONTROLLER_PPI *This,\r | |
| 169 | IN UINT32 MaxFrequency\r | |
| 170 | );\r | |
| 171 | \r | |
| 172 | /*++\r | |
| 173 | \r | |
| 174 | Routine Description:\r | |
| 175 | Set bus width of the host\r | |
| 176 | \r | |
| 177 | Arguments:\r | |
| 178 | This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r | |
| 179 | BusWidth - Bus width in 1, 4, 8 bits\r | |
| 180 | \r | |
| 181 | Returns:\r | |
| 182 | EFI_SUCCESS\r | |
| 183 | EFI_INVALID_PARAMETER\r | |
| 184 | \r | |
| 185 | --*/\r | |
| 186 | typedef\r | |
| 187 | EFI_STATUS\r | |
| 188 | (EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH) (\r | |
| 189 | IN PEI_SD_CONTROLLER_PPI *This,\r | |
| 190 | IN UINT32 BusWidth\r | |
| 191 | );\r | |
| 192 | \r | |
| 193 | /*++\r | |
| 194 | \r | |
| 195 | Routine Description:\r | |
| 196 | Set Host mode in DDR\r | |
| 197 | Arguments:\r | |
| 198 | This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r | |
| 199 | SetHostDdrMode - True for DDR Mode set, false for normal mode\r | |
| 200 | \r | |
| 201 | Returns:\r | |
| 202 | EFI_SUCCESS\r | |
| 203 | EFI_INVALID_PARAMETER\r | |
| 204 | \r | |
| 205 | --*/\r | |
| 206 | typedef\r | |
| 207 | EFI_STATUS\r | |
| 208 | (EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) (\r | |
| 209 | IN PEI_SD_CONTROLLER_PPI *This,\r | |
| 210 | IN UINT32 DdrMode\r | |
| 211 | );\r | |
| 212 | \r | |
| 213 | /*++\r | |
| 214 | \r | |
| 215 | Routine Description:\r | |
| 216 | Set voltage which could supported by the host.\r | |
| 217 | Support 0(Power off the host), 1.8V, 3.0V, 3.3V\r | |
| 218 | Arguments:\r | |
| 219 | This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r | |
| 220 | Voltage - Units in 0.1 V\r | |
| 221 | \r | |
| 222 | Returns:\r | |
| 223 | EFI_SUCCESS\r | |
| 224 | EFI_INVALID_PARAMETER\r | |
| 225 | \r | |
| 226 | --*/\r | |
| 227 | typedef\r | |
| 228 | EFI_STATUS\r | |
| 229 | (EFIAPI *EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE) (\r | |
| 230 | IN PEI_SD_CONTROLLER_PPI *This,\r | |
| 231 | IN UINT32 Voltage\r | |
| 232 | );\r | |
| 233 | \r | |
| 234 | /*++\r | |
| 235 | \r | |
| 236 | Routine Description:\r | |
| 237 | Reset the host\r | |
| 238 | \r | |
| 239 | Arguments:\r | |
| 240 | This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r | |
| 241 | ResetAll - TRUE to reset all\r | |
| 242 | \r | |
| 243 | Returns:\r | |
| 244 | EFI_SUCCESS\r | |
| 245 | EFI_TIMEOUT\r | |
| 246 | \r | |
| 247 | --*/\r | |
| 248 | typedef\r | |
| 249 | EFI_STATUS\r | |
| 250 | (EFIAPI *EFI_SD_CONTROLLER_PPI_RESET_SD_HOST) (\r | |
| 251 | IN PEI_SD_CONTROLLER_PPI *This,\r | |
| 252 | IN RESET_TYPE ResetType\r | |
| 253 | );\r | |
| 254 | \r | |
| 255 | /*++\r | |
| 256 | \r | |
| 257 | Routine Description:\r | |
| 258 | Reset the host\r | |
| 259 | \r | |
| 260 | Arguments:\r | |
| 261 | This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r | |
| 262 | Enable - TRUE to enable, FALSE to disable\r | |
| 263 | \r | |
| 264 | Returns:\r | |
| 265 | EFI_SUCCESS\r | |
| 266 | EFI_TIMEOUT\r | |
| 267 | \r | |
| 268 | --*/\r | |
| 269 | typedef\r | |
| 270 | EFI_STATUS\r | |
| 271 | (EFIAPI *EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD) (\r | |
| 272 | IN PEI_SD_CONTROLLER_PPI *This,\r | |
| 273 | IN BOOLEAN Enable\r | |
| 274 | );\r | |
| 275 | \r | |
| 276 | /*++\r | |
| 277 | \r | |
| 278 | Routine Description:\r | |
| 279 | Find whether these is a card inserted into the slot. If so\r | |
| 280 | init the host. If not, return EFI_NOT_FOUND.\r | |
| 281 | \r | |
| 282 | Arguments:\r | |
| 283 | This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r | |
| 284 | \r | |
| 285 | Returns:\r | |
| 286 | EFI_SUCCESS\r | |
| 287 | EFI_NOT_FOUND\r | |
| 288 | \r | |
| 289 | --*/\r | |
| 290 | typedef\r | |
| 291 | EFI_STATUS\r | |
| 292 | (EFIAPI *EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST) (\r | |
| 293 | IN PEI_SD_CONTROLLER_PPI *This\r | |
| 294 | );\r | |
| 295 | \r | |
| 296 | /*++\r | |
| 297 | \r | |
| 298 | Routine Description:\r | |
| 299 | Set the Block length\r | |
| 300 | \r | |
| 301 | Arguments:\r | |
| 302 | This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r | |
| 303 | BlockLength - card supportes block length\r | |
| 304 | \r | |
| 305 | Returns:\r | |
| 306 | EFI_SUCCESS\r | |
| 307 | EFI_TIMEOUT\r | |
| 308 | \r | |
| 309 | --*/\r | |
| 310 | typedef\r | |
| 311 | EFI_STATUS\r | |
| 312 | (EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH) (\r | |
| 313 | IN PEI_SD_CONTROLLER_PPI *This,\r | |
| 314 | IN UINT32 BlockLength\r | |
| 315 | );\r | |
| 316 | \r | |
| 317 | /*++\r | |
| 318 | \r | |
| 319 | Routine Description:\r | |
| 320 | Set the Block length\r | |
| 321 | \r | |
| 322 | Arguments:\r | |
| 323 | This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r | |
| 324 | BlockLength - card supportes block length\r | |
| 325 | \r | |
| 326 | Returns:\r | |
| 327 | EFI_SUCCESS\r | |
| 328 | EFI_TIMEOUT\r | |
| 329 | \r | |
| 330 | --*/\r | |
| 331 | \r | |
| 332 | typedef EFI_STATUS\r | |
| 333 | (EFIAPI *EFI_SD_CONTROLLER_PPI_SETUP_DEVICE)(\r | |
| 334 | IN PEI_SD_CONTROLLER_PPI *This\r | |
| 335 | );\r | |
| 336 | \r | |
| 337 | //\r | |
| 338 | // Interface structure for the EFI SD Host I/O Protocol\r | |
| 339 | //\r | |
| 340 | struct _PEI_SD_CONTROLLER_PPI {\r | |
| 341 | UINT32 Revision;\r | |
| 342 | HOST_CAPABILITY HostCapability;\r | |
| 343 | EFI_SD_CONTROLLER_PPI_SEND_COMMAND SendCommand;\r | |
| 344 | EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY SetClockFrequency;\r | |
| 345 | EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH SetBusWidth;\r | |
| 346 | EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE SetHostVoltage;\r | |
| 347 | EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE SetHostDdrMode;\r | |
| 348 | EFI_SD_CONTROLLER_PPI_RESET_SD_HOST ResetSdHost;\r | |
| 349 | EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD EnableAutoStopCmd;\r | |
| 350 | EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST DetectCardAndInitHost;\r | |
| 351 | EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH SetBlockLength;\r | |
| 352 | EFI_SD_CONTROLLER_PPI_SETUP_DEVICE SetupDevice;\r | |
| 353 | };\r | |
| 354 | // Extern the GUID for PPI users.\r | |
| 355 | //\r | |
| 356 | extern EFI_GUID gPeiSdhcPpiGuid;\r | |
| 357 | \r | |
| 358 | \r | |
| 359 | #endif\r |