[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / SouthCluster / Include / Protocol / Gpio.h

/*++\r
\r
Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
\r
\r
Module Name:\r
\r
  Gpio.h\r
\r
Abstract:\r
\r
EFI 2.0 PEIM to provide platform specific information to other\r
modules and to do some platform specific initialization.\r
\r
--*/\r
\r
#ifndef _PEI_GPIO_H\r
#define _PEI_GPIO_H\r
\r
//#include "Efi.h"\r
//#include "EfiCommonLib.h"\r
//#include "Pei.h"\r
//#include "Numbers.h"\r
\r
////\r
//// GPIO Register Settings for BeaverBridge (FFVS) (Cedarview/Tigerpoint)\r
////\r
//// Field Descriptions:\r
////    USE: Defines the pin's usage model:  GPIO (G) or Native (N) mode.\r
////    I/O: Defines whether GPIOs are inputs (I) or outputs (O).\r
////         (Note:  Only meaningful for pins used as GPIOs.)\r
////    LVL: This field gives you the initial value for "output" GPIO's.\r
////         (Note: The output level is dependent upon whether the pin is inverted.)\r
////    INV: Defines whether Input GPIOs activation level is inverted.\r
////         (Note:  Only affects the level sent to the GPE logic and does not\r
////         affect the level read through the GPIO registers.)\r
////\r
//// Notes:\r
////    1. BoardID is GPIO [8:38:34]\r
////\r
////Signal         UsedAs               USE     I/O      LVL     INV\r
////--------------------------------------------------------------------------\r
////GPIO0           Nonfunction       G     O            H       -\r
////GPIO1           SMC_RUNTIME_SCI#    G        I           -       I\r
////PIRQE#/GPIO2    Nonfunction G   O   H   -\r
////PIRQF#/GPIO3    Nonfunction G   O   H   -\r
////PIRQG#/GPIO4    Nonfunction G   O   H   -\r
////PIRQH#/GPIO5    Nonfunction G   O   H   -\r
////GPIO6   unused  G   O   L   -\r
////GPIO7   unused  G   O   L   -\r
////GPIO8          BOARD ID2    G   I   -   -\r
////GPIO9   unused  G   O   L   -\r
////GPIO10  SMC_EXTSMI# G   I   -   I\r
////GPIO11  Nonfunction G   O   H   -\r
////GPIO12  unused  G   O   L   -\r
////GPIO13  SMC_WAKE_SCI#   G   I   -   I\r
////GPIO14  unused  G   O   L   -\r
////GPIO15  unused  G   O   L   -\r
////GPIO16  PM_DPRSLPVR N   -   -   -\r
////GNT5#/GPIO17    GNT5#   N   -   -   -\r
////STPPCI#/GPIO18  PM_STPPCI#  N   -   -   -\r
////STPCPU#/GPIO20  PM_STPCPU#  N   -   -   -\r
////GPIO22  CRT_RefClk  G   I   -   -\r
////GPIO23  unused  G   O   L   -\r
////GPIO24  unused  G   O   L   -\r
////GPIO25  DMI strap   G   O   L   -\r
////GPIO26  unused  G   O   L   -\r
////GPIO27  unused  G   O   L   -\r
////GPIO28  RF_KILL#    G   O   H   -\r
////OC5#/GPIO29 OC  N   -   -   -\r
////OC6#/GPIO30 OC  N   -   -   -\r
////OC7#/GPIO31 OC  N   -   -   -\r
////CLKRUN#/GPIO32  PM_CLKRUN#  N   -   -   -\r
////GPIO33  NC  G   O   L   -\r
////GPIO34  BOARD ID0   G   I   -   -\r
////GPIO36  unused  G   O   L   -\r
////GPIO38  BOARD ID1   G   I   -   -\r
////GPIO39  unused  G   O   L   -\r
////GPIO48  unused  G   O   L   -\r
////CPUPWRGD/GPIO49 H_PWRGD N   -   -   -\r
//\r
//#define   GPIO_USE_SEL_VAL              0x1FC0FFFF       //GPIO1, 10, 13 is EC signal\r
//#define   GPIO_USE_SEL2_VAL             0x000100D6\r
//#define   GPIO_IO_SEL_VAL               0x00402502\r
//#define   GPIO_IO_SEL2_VAL              0x00000044\r
//#define   GPIO_LVL_VAL                  0x1800083D\r
//#define   GPIO_LVL2_VAL                 0x00000000\r
//#define   GPIO_INV_VAL                  0x00002402\r
//#define   GPIO_BLNK_VAL                 0x00000000\r
//#define   ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1))\r
\r
//\r
// GPIO Register Settings for CedarRock and CedarFalls platforms\r
//\r
//      GPIO Register Settings for NB10_CRB\r
//---------------------------------------------------------------------------------\r
//Signal        Used As         USE         I/O     LVL\r
//---------------------------------------------------------------------------------\r
//\r
// GPIO0    FP_AUDIO_DETECT     G       I\r
// GPIO1    SMC_RUNTIME_SCI#    G       I\r
// GPIO2        INT_PIRQE_N     N       I\r
// GPIO3    INT_PIRQF_N     N       I\r
// GPIO4        INT_PIRQG_N     N       I\r
// GPIO5        INT_PIRQH_N     N       I\r
// GPIO6\r
// GPIO7\r
// GPIO8\r
// GPIO9    LPC_SIO_PME     G       I\r
// GPIO10   SMC_EXTSMI_N        G       I\r
// GPIO11   SMBALERT- pullup    N\r
// GPIO12   ICH_GP12        G       I\r
// GPIO13   SMC_WAKE_SCI_N      G       I\r
// GPIO14   LCD_PID0        G       O       H\r
// GPIO15   CONFIG_MODE_N       G       I\r
// GPIO16       PM_DPRSLPVR     N\r
// GPIO17   SPI_SELECT_STRAP1\r
//          /L_BKLTSEL0_N   G       I\r
// GPIO18   PM_STPPCI_N     N\r
// GPIO19\r
// GPIO20   PM_STPCPU_N     N\r
// GPIO21\r
// GPIO22   REQ4B           G       I\r
// GPIO23   L_DRQ1_N        N\r
// GPIO24   CRB_SV_DET_N        G       O       H\r
// GPIO25   DMI strap\r
//          / L_BKLTSEL1_N  G       O       H\r
// GPIO26   LCD_PID1        G       O       H\r
// GPIO27   TPEV_DDR3L_DETECT   G       O       H\r
// GPIO28   RF_KILL         G       O       H:enable\r
// GPIO29   OC          N\r
// GPIO30   OC          N\r
// GPIO31   OC          N\r
// GPIO32   PM_CLKRUN_N     Native\r
// GPIO33   MFG_MODE_N      G       I\r
// GPIO34   BOARD ID0       G       I\r
// GPIO35\r
// GPIO36   SV_SET_UP       G       O       H\r
// GPIO37\r
// GPIO38   BOARD ID1       G       I\r
// GPIO39   BOARD ID2       G       I\r
// GPIO48   FLASH_SEL0      N\r
// GPIO49   H_PWRGD         N\r
\r
#define ICH_GPI_ROUTE_SMI(Gpio)          ((( 0 << ((Gpio * 2) + 1)) | (1 << (Gpio * 2))))\r
#define ICH_GPI_ROUTE_SCI(Gpio)          ((( 1 << ((Gpio * 2) + 1)) | (0 << (Gpio * 2))))\r
\r
#define   GPIO_USE_SEL_VAL              0X1F42F7C3\r
#define   GPIO_USE_SEL2_VAL             0X000000D6\r
#define   GPIO_IO_SEL_VAL               0X1042B73F\r
#define   GPIO_IO_SEL2_VAL              0X000100C6\r
#define   GPIO_LVL_VAL                  0X1F15F601\r
#define   GPIO_LVL2_VAL                 0X000200D7\r
#define   GPIO_INV_VAL                  0x00002602\r
#define   GPIO_BLNK_VAL                 0x00040000\r
#define   ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1))\r
\r
#endif\r
Commit	Line	Data
3cbfba02 DW	1	/*++\r
	2	\r
	3	Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
	4	\r
7ede8060	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
3cbfba02 DW	6	\r
	7	\r
	8	\r
	9	Module Name:\r
	10	\r
	11	Gpio.h\r
	12	\r
	13	Abstract:\r
	14	\r
	15	EFI 2.0 PEIM to provide platform specific information to other\r
	16	modules and to do some platform specific initialization.\r
	17	\r
	18	--*/\r
	19	\r
	20	#ifndef _PEI_GPIO_H\r
	21	#define _PEI_GPIO_H\r
	22	\r
	23	//#include "Efi.h"\r
	24	//#include "EfiCommonLib.h"\r
	25	//#include "Pei.h"\r
	26	//#include "Numbers.h"\r
	27	\r
	28	////\r
	29	//// GPIO Register Settings for BeaverBridge (FFVS) (Cedarview/Tigerpoint)\r
	30	////\r
	31	//// Field Descriptions:\r
	32	//// USE: Defines the pin's usage model: GPIO (G) or Native (N) mode.\r
	33	//// I/O: Defines whether GPIOs are inputs (I) or outputs (O).\r
	34	//// (Note: Only meaningful for pins used as GPIOs.)\r
	35	//// LVL: This field gives you the initial value for "output" GPIO's.\r
	36	//// (Note: The output level is dependent upon whether the pin is inverted.)\r
	37	//// INV: Defines whether Input GPIOs activation level is inverted.\r
	38	//// (Note: Only affects the level sent to the GPE logic and does not\r
	39	//// affect the level read through the GPIO registers.)\r
	40	////\r
	41	//// Notes:\r
	42	//// 1. BoardID is GPIO [8:38:34]\r
	43	////\r
	44	////Signal UsedAs USE I/O LVL INV\r
	45	////--------------------------------------------------------------------------\r
	46	////GPIO0 Nonfunction G O H -\r
	47	////GPIO1 SMC_RUNTIME_SCI# G I - I\r
	48	////PIRQE#/GPIO2 Nonfunction G O H -\r
	49	////PIRQF#/GPIO3 Nonfunction G O H -\r
	50	////PIRQG#/GPIO4 Nonfunction G O H -\r
	51	////PIRQH#/GPIO5 Nonfunction G O H -\r
	52	////GPIO6 unused G O L -\r
	53	////GPIO7 unused G O L -\r
	54	////GPIO8 BOARD ID2 G I - -\r
	55	////GPIO9 unused G O L -\r
	56	////GPIO10 SMC_EXTSMI# G I - I\r
	57	////GPIO11 Nonfunction G O H -\r
	58	////GPIO12 unused G O L -\r
	59	////GPIO13 SMC_WAKE_SCI# G I - I\r
	60	////GPIO14 unused G O L -\r
	61	////GPIO15 unused G O L -\r
	62	////GPIO16 PM_DPRSLPVR N - - -\r
	63	////GNT5#/GPIO17 GNT5# N - - -\r
	64	////STPPCI#/GPIO18 PM_STPPCI# N - - -\r
	65	////STPCPU#/GPIO20 PM_STPCPU# N - - -\r
	66	////GPIO22 CRT_RefClk G I - -\r
	67	////GPIO23 unused G O L -\r
	68	////GPIO24 unused G O L -\r
	69	////GPIO25 DMI strap G O L -\r
70	////GPIO26 unused G O L -\r
71	////GPIO27 unused G O L -\r
72	////GPIO28 RF_KILL# G O H -\r
73	////OC5#/GPIO29 OC N - - -\r
74	////OC6#/GPIO30 OC N - - -\r
75	////OC7#/GPIO31 OC N - - -\r
76	////CLKRUN#/GPIO32 PM_CLKRUN# N - - -\r
77	////GPIO33 NC G O L -\r
78	////GPIO34 BOARD ID0 G I - -\r
79	////GPIO36 unused G O L -\r
80	////GPIO38 BOARD ID1 G I - -\r
81	////GPIO39 unused G O L -\r
82	////GPIO48 unused G O L -\r
83	////CPUPWRGD/GPIO49 H_PWRGD N - - -\r
84	//\r
85	//#define GPIO_USE_SEL_VAL 0x1FC0FFFF //GPIO1, 10, 13 is EC signal\r
86	//#define GPIO_USE_SEL2_VAL 0x000100D6\r
87	//#define GPIO_IO_SEL_VAL 0x00402502\r
88	//#define GPIO_IO_SEL2_VAL 0x00000044\r
89	//#define GPIO_LVL_VAL 0x1800083D\r
90	//#define GPIO_LVL2_VAL 0x00000000\r
91	//#define GPIO_INV_VAL 0x00002402\r
92	//#define GPIO_BLNK_VAL 0x00000000\r
93	//#define ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) \| ICH_GPI_ROUTE_SCI(1))\r
94	\r
95	//\r
96	// GPIO Register Settings for CedarRock and CedarFalls platforms\r
97	//\r
98	// GPIO Register Settings for NB10_CRB\r
99	//---------------------------------------------------------------------------------\r
100	//Signal Used As USE I/O LVL\r
101	//---------------------------------------------------------------------------------\r
102	//\r
103	// GPIO0 FP_AUDIO_DETECT G I\r
104	// GPIO1 SMC_RUNTIME_SCI# G I\r
105	// GPIO2 INT_PIRQE_N N I\r
106	// GPIO3 INT_PIRQF_N N I\r
107	// GPIO4 INT_PIRQG_N N I\r
108	// GPIO5 INT_PIRQH_N N I\r
109	// GPIO6\r
110	// GPIO7\r
111	// GPIO8\r
112	// GPIO9 LPC_SIO_PME G I\r
113	// GPIO10 SMC_EXTSMI_N G I\r
114	// GPIO11 SMBALERT- pullup N\r
115	// GPIO12 ICH_GP12 G I\r
116	// GPIO13 SMC_WAKE_SCI_N G I\r
117	// GPIO14 LCD_PID0 G O H\r
118	// GPIO15 CONFIG_MODE_N G I\r
119	// GPIO16 PM_DPRSLPVR N\r
120	// GPIO17 SPI_SELECT_STRAP1\r
121	// /L_BKLTSEL0_N G I\r
122	// GPIO18 PM_STPPCI_N N\r
123	// GPIO19\r
124	// GPIO20 PM_STPCPU_N N\r
125	// GPIO21\r
126	// GPIO22 REQ4B G I\r
127	// GPIO23 L_DRQ1_N N\r
128	// GPIO24 CRB_SV_DET_N G O H\r
129	// GPIO25 DMI strap\r
130	// / L_BKLTSEL1_N G O H\r
131	// GPIO26 LCD_PID1 G O H\r
132	// GPIO27 TPEV_DDR3L_DETECT G O H\r
133	// GPIO28 RF_KILL G O H:enable\r
134	// GPIO29 OC N\r
135	// GPIO30 OC N\r
136	// GPIO31 OC N\r
137	// GPIO32 PM_CLKRUN_N Native\r
138	// GPIO33 MFG_MODE_N G I\r
139	// GPIO34 BOARD ID0 G I\r
140	// GPIO35\r
141	// GPIO36 SV_SET_UP G O H\r
142	// GPIO37\r
143	// GPIO38 BOARD ID1 G I\r
144	// GPIO39 BOARD ID2 G I\r
145	// GPIO48 FLASH_SEL0 N\r
146	// GPIO49 H_PWRGD N\r
147	\r
148	#define ICH_GPI_ROUTE_SMI(Gpio) ((( 0 << ((Gpio * 2) + 1)) \| (1 << (Gpio * 2))))\r
149	#define ICH_GPI_ROUTE_SCI(Gpio) ((( 1 << ((Gpio * 2) + 1)) \| (0 << (Gpio * 2))))\r
150	\r
151	#define GPIO_USE_SEL_VAL 0X1F42F7C3\r
152	#define GPIO_USE_SEL2_VAL 0X000000D6\r
153	#define GPIO_IO_SEL_VAL 0X1042B73F\r
154	#define GPIO_IO_SEL2_VAL 0X000100C6\r
155	#define GPIO_LVL_VAL 0X1F15F601\r
156	#define GPIO_LVL2_VAL 0X000200D7\r
157	#define GPIO_INV_VAL 0x00002602\r
158	#define GPIO_BLNK_VAL 0x00040000\r
159	#define ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) \| ICH_GPI_ROUTE_SCI(1))\r
160	\r
161	#endif\r