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1 | /** @file\r |
2 | I2C bus interface\r | |
3 | \r | |
4 | This layer provides I/O access to an I2C device.\r | |
5 | \r | |
7ede8060 MK |
6 | Copyright (c) 2012, Intel Corporation. All rights reserved.\r |
7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
3cbfba02 DW |
8 | \r |
9 | **/\r | |
10 | \r | |
11 | #ifndef __I2C_BUS_H__\r | |
12 | #define __I2C_BUS_H__\r | |
13 | \r | |
14 | #include <Protocol/I2cHostMcg.h>\r | |
15 | \r | |
16 | ///\r | |
17 | /// I2C bus protocol\r | |
18 | ///\r | |
19 | typedef struct _EFI_I2C_BUS_PROTOCOL EFI_I2C_BUS_PROTOCOL;\r | |
20 | \r | |
21 | \r | |
22 | /**\r | |
23 | Perform an I2C operation on the device\r | |
24 | \r | |
25 | This routine must be called at or below TPL_NOTIFY. For synchronous\r | |
26 | requests this routine must be called at or below TPL_CALLBACK.\r | |
27 | \r | |
28 | N.B. The typical consumers of this API are the third party I2C\r | |
29 | drivers. Extreme care must be taken by other consumers of this\r | |
30 | API to prevent confusing the third party I2C drivers due to a\r | |
31 | state change at the I2C device which the third party I2C drivers\r | |
32 | did not initiate. I2C platform drivers may use this API within\r | |
33 | these guidelines.\r | |
34 | \r | |
35 | This routine queues an operation to the I2C controller for execution\r | |
36 | on the I2C bus.\r | |
37 | \r | |
38 | As an upper layer driver writer, the following need to be provided\r | |
39 | to the platform vendor:\r | |
40 | \r | |
41 | 1. ACPI CID value or string - this is used to connect the upper layer\r | |
42 | driver to the device.\r | |
43 | 2. Slave address array guidance when the I2C device uses more than one\r | |
44 | slave address. This is used to access the blocks of hardware within\r | |
45 | the I2C device.\r | |
46 | \r | |
47 | @param[in] This Address of an EFI_I2C_BUS_PROTOCOL\r | |
48 | structure\r | |
49 | @param[in] SlaveAddressIndex Index into an array of slave addresses for\r | |
50 | the I2C device. The values in the array are\r | |
51 | specified by the board designer, with the\r | |
52 | I2C device driver writer providing the slave\r | |
53 | address order.\r | |
54 | \r | |
55 | For devices that have a single slave address,\r | |
56 | this value must be zero. If the I2C device\r | |
57 | uses more than one slave address then the third\r | |
58 | party (upper level) I2C driver writer needs to\r | |
59 | specify the order of entries in the slave address\r | |
60 | array.\r | |
61 | \r | |
62 | \ref ThirdPartyI2cDrivers "Third Party I2C Drivers"\r | |
63 | section in I2cMaster.h.\r | |
64 | @param[in] Event Event to set for asynchronous operations,\r | |
65 | NULL for synchronous operations\r | |
66 | @param[in] RequestPacket Address of an EFI_I2C_REQUEST_PACKET\r | |
67 | structure describing the I2C operation\r | |
68 | @param[out] I2cStatus Optional buffer to receive the I2C operation\r | |
69 | completion status\r | |
70 | \r | |
71 | @retval EFI_SUCCESS The operation completed successfully.\r | |
72 | @retval EFI_ABORTED The request did not complete because the driver\r | |
73 | was shutdown.\r | |
74 | @retval EFI_ACCESS_DENIED Invalid SlaveAddressIndex value\r | |
75 | @retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size is too large.\r | |
76 | @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the operation.\r | |
77 | This could indicate the slave device is not present.\r | |
78 | @retval EFI_INVALID_PARAMETER RequestPacket is NULL\r | |
79 | @retval EFI_INVALID_PARAMETER TPL is too high\r | |
80 | @retval EFI_NO_RESPONSE The I2C device is not responding to the\r | |
81 | slave address. EFI_DEVICE_ERROR may also be\r | |
82 | returned if the controller can not distinguish\r | |
83 | when the NACK occurred.\r | |
84 | @retval EFI_NOT_FOUND I2C slave address exceeds maximum address\r | |
85 | @retval EFI_NOT_READY I2C bus is busy or operation pending, wait for\r | |
86 | the event and then read status pointed to by\r | |
87 | the request packet.\r | |
88 | @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation\r | |
89 | @retval EFI_TIMEOUT The transaction did not complete within an internally\r | |
90 | specified timeout period.\r | |
91 | \r | |
92 | **/\r | |
93 | typedef\r | |
94 | EFI_STATUS\r | |
95 | (EFIAPI *EFI_I2C_BUS_START_REQUEST) (\r | |
96 | IN CONST EFI_I2C_BUS_PROTOCOL *This,\r | |
97 | IN UINTN SlaveAddressIndex,\r | |
98 | IN EFI_EVENT Event OPTIONAL,\r | |
99 | IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket,\r | |
100 | OUT EFI_STATUS *I2cStatus OPTIONAL\r | |
101 | );\r | |
102 | \r | |
103 | ///\r | |
104 | /// The I2C bus protocol enables access to a specific device on the I2C bus.\r | |
105 | ///\r | |
106 | /// Each I2C device is described as an ACPI node (HID, UID and CID) within the\r | |
107 | /// platform layer. The I2C bus protocol enumerates the I2C devices in the\r | |
108 | /// platform and creates a unique handle and device path for each I2C device.\r | |
109 | ///\r | |
110 | /// I2C slave addressing is abstracted to validate addresses and limit operation\r | |
111 | /// to the specified I2C device. The third party providing the I2C device support\r | |
112 | /// provides an ordered list of slave addresses for the I2C device to the team\r | |
113 | /// building the platform layer. The platform team must preserve the order of the\r | |
114 | /// supplied list. SlaveAddressCount is the number of entries in this list or\r | |
115 | /// array within the platform layer. The third party device support references\r | |
116 | /// a slave address using an index into the list or array in the range of zero\r | |
117 | /// to SlaveAddressCount - 1.\r | |
118 | ///\r | |
119 | struct _EFI_I2C_BUS_PROTOCOL {\r | |
120 | ///\r | |
121 | /// Start an I2C operation on the bus\r | |
122 | ///\r | |
123 | EFI_I2C_BUS_START_REQUEST StartRequest;\r | |
124 | \r | |
125 | ///\r | |
126 | /// The maximum number of slave addresses for the I2C device. The caller may\r | |
127 | /// validate this value as a check on the platform layer's configuration. Slave\r | |
128 | /// address selection uses an index value in the range of zero to SlaveAddressCount - 1.\r | |
129 | ///\r | |
130 | UINTN SlaveAddressCount;\r | |
131 | \r | |
132 | ///\r | |
133 | /// Hardware revision - Matches the ACPI _HRV value\r | |
134 | ///\r | |
135 | /// The HardwareRevision value allows a single driver to support multiple hardware\r | |
136 | /// revisions and implement the necessary workarounds for limitations within the\r | |
137 | /// hardware.\r | |
138 | ///\r | |
139 | UINT32 HardwareRevision;\r | |
140 | \r | |
141 | ///\r | |
142 | /// The maximum number of bytes the I2C host controller\r | |
143 | /// is able to receive from the I2C bus.\r | |
144 | ///\r | |
145 | UINT32 MaximumReceiveBytes;\r | |
146 | \r | |
147 | ///\r | |
148 | /// The maximum number of bytes the I2C host controller\r | |
149 | /// is able to send on the I2C bus.\r | |
150 | ///\r | |
151 | UINT32 MaximumTransmitBytes;\r | |
152 | \r | |
153 | ///\r | |
154 | /// The maximum number of bytes in the I2C bus transaction.\r | |
155 | ///\r | |
156 | UINT32 MaximumTotalBytes;\r | |
157 | };\r | |
158 | \r | |
159 | ///\r | |
160 | /// GUID for the I2C bus protocol\r | |
161 | ///\r | |
162 | extern EFI_GUID gEfiI2cBusProtocolGuid;\r | |
163 | \r | |
164 | #endif // __I2C_BUS_H__\r |