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1/** @file\r
2\r
3Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved.<BR>\r
4 \r\r
5 This program and the accompanying materials are licensed and made available under\r\r
6 the terms and conditions of the BSD License that accompanies this distribution. \r\r
7 The full text of the license may be found at \r\r
8 http://opensource.org/licenses/bsd-license.php. \r\r
9 \r\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r
12 \r\r
13\r
14**/\r
15\r
16#ifndef _FIRMWARE_UPDATE_H_\r
17#define _FIRMWARE_UPDATE_H_\r
18\r
19#include <Uefi.h>\r
20\r
21#include <PiDxe.h>\r
22\r
23#include <Guid/FileInfo.h>\r
24\r
25#include <Protocol/FirmwareVolumeBlock.h>\r
26#include <Protocol/LoadedImage.h>\r
27#include <Protocol/SimpleFileSystem.h>\r
28#include <Protocol/Spi.h>\r
29\r
30#include <Library/BaseLib.h>\r
31#include <Library/BaseMemoryLib.h>\r
32#include <Library/CacheMaintenanceLib.h>\r
33#include <Library/DebugLib.h>\r
34#include <Library/FileHandleLib.h>\r
35#include <Library/HiiLib.h>\r
36#include <Library/MemoryAllocationLib.h>\r
37#include <Library/PcdLib.h>\r
38#include <Library/PrintLib.h>\r
39#include <Library/ShellLib.h>\r
40#include <Library/UefiApplicationEntryPoint.h>\r
41#include <Library/UefiBootServicesTableLib.h>\r
42#include <Library/UefiLib.h>\r
43#include <Library/UefiRuntimeServicesTableLib.h>\r
44\r
45//\r
46// Function Prototypes.\r
47//\r
48STATIC\r
49EFI_STATUS\r
50ReadFileData (\r
51 IN CHAR16 *FileName,\r
52 OUT UINT8 **Buffer,\r
53 OUT UINT32 *BufferSize\r
54 );\r
55\r
56STATIC\r
57EFI_STATUS\r
58InternalEraseBlock (\r
59 IN EFI_PHYSICAL_ADDRESS BaseAddress\r
60 );\r
61\r
62#if 0\r
63STATIC\r
64EFI_STATUS\r
65InternalReadBlock (\r
66 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
67 OUT VOID *ReadBuffer\r
68 );\r
69#endif\r
70\r
71STATIC\r
72EFI_STATUS\r
73InternalCompareBlock (\r
74 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
75 IN UINT8 *Buffer\r
76 );\r
77\r
78STATIC\r
79EFI_STATUS\r
80InternalWriteBlock (\r
81 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
82 IN UINT8 *Buffer,\r
83 IN UINT32 BufferSize\r
84 );\r
85\r
86STATIC\r
87VOID\r
88PrintHelpInfo (\r
89 VOID\r
90 );\r
91\r
92STATIC\r
93EFI_STATUS\r
94EFIAPI\r
95SpiFlashRead (\r
96 IN UINTN Address,\r
97 IN OUT UINT32 *NumBytes,\r
98 OUT UINT8 *Buffer\r
99 );\r
100\r
101STATIC\r
102EFI_STATUS\r
103EFIAPI\r
104SpiFlashWrite (\r
105 IN UINTN Address,\r
106 IN OUT UINT32 *NumBytes,\r
107 IN UINT8 *Buffer\r
108 );\r
109\r
110STATIC\r
111EFI_STATUS\r
112EFIAPI\r
113SpiFlashBlockErase (\r
114 IN UINTN Address,\r
115 IN UINTN *NumBytes\r
116 );\r
117\r
118STATIC\r
119EFI_STATUS\r
120EFIAPI\r
121ConvertMac (\r
122 CHAR16 *Str\r
123 );\r
124\r
125EFI_STATUS\r
126InitializeFVUPDATE (\r
127 IN EFI_HANDLE ImageHandle,\r
128 IN EFI_SYSTEM_TABLE *SystemTable\r
129 );\r
130\r
131//\r
132// Flash specific definitions.\r
133// - Should we use a PCD for this information?\r
134//\r
135#define BLOCK_SIZE SIZE_4KB\r
136\r
137//\r
138// Flash region layout and update information.\r
139//\r
140typedef struct {\r
141 EFI_PHYSICAL_ADDRESS Base;\r
142 UINTN Size;\r
143 BOOLEAN Update;\r
144} FV_REGION_INFO;\r
145\r
146//\r
147// MAC Address information.\r
148//\r
149#define MAC_ADD_STR_LEN 12\r
150#define MAC_ADD_STR_SIZE (MAC_ADD_STR_LEN + 1)\r
151#define MAC_ADD_BYTE_COUNT 6\r
152#define MAC_ADD_TMP_STR_LEN 2\r
153#define MAC_ADD_TMP_STR_SIZE (MAC_ADD_TMP_STR_LEN + 1)\r
154\r
155//\r
156// Command Line Data.\r
157//\r
158#define INPUT_STRING_LEN 255\r
159#define INPUT_STRING_SIZE (INPUT_STRING_LEN + 1)\r
160typedef struct {\r
161 BOOLEAN UpdateFromFile;\r
162 CHAR16 FileName[INPUT_STRING_SIZE];\r
163 BOOLEAN UpdateMac;\r
164 UINT8 MacValue[MAC_ADD_BYTE_COUNT];\r
165 BOOLEAN FullFlashUpdate;\r
166} FV_INPUT_DATA;\r
167\r
168//\r
169// Prefix Opcode Index on the host SPI controller.\r
170//\r
171typedef enum {\r
172 SPI_WREN, // Prefix Opcode 0: Write Enable.\r
173 SPI_EWSR, // Prefix Opcode 1: Enable Write Status Register.\r
174} PREFIX_OPCODE_INDEX;\r
175\r
176//\r
177// Opcode Menu Index on the host SPI controller.\r
178//\r
179typedef enum {\r
180 SPI_READ_ID, // Opcode 0: READ ID, Read cycle with address.\r
181 SPI_READ, // Opcode 1: READ, Read cycle with address.\r
182 SPI_RDSR, // Opcode 2: Read Status Register, No address.\r
183 SPI_WRDI_SFDP, // Opcode 3: Write Disable or Discovery Parameters, No address.\r
184 SPI_SERASE, // Opcode 4: Sector Erase (4KB), Write cycle with address.\r
185 SPI_BERASE, // Opcode 5: Block Erase (32KB), Write cycle with address.\r
186 SPI_PROG, // Opcode 6: Byte Program, Write cycle with address.\r
187 SPI_WRSR, // Opcode 7: Write Status Register, No address.\r
188} SPI_OPCODE_INDEX;\r
189\r
190#endif\r