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75ce133c JY |
1 | /** @file\r |
2 | Platform Flash Access library.\r | |
3 | \r | |
3eac7496 | 4 | Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r |
9dc8036d | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
75ce133c JY |
6 | \r |
7 | **/\r | |
27f44846 | 8 | #include <Uefi.h>\r |
75ce133c JY |
9 | \r |
10 | #include <PiDxe.h>\r | |
11 | \r | |
12 | #include <Library/BaseLib.h>\r | |
13 | #include <Library/BaseMemoryLib.h>\r | |
14 | #include <Library/DebugLib.h>\r | |
15 | #include <Library/PcdLib.h>\r | |
16 | #include <Library/PlatformFlashAccessLib.h>\r | |
27f44846 | 17 | //#include <Library/FlashDeviceLib.h>\r |
75ce133c | 18 | #include <Library/MemoryAllocationLib.h>\r |
27f44846 KM |
19 | #include <Protocol/Spi.h>\r |
20 | #include <Library/CacheMaintenanceLib.h>\r | |
21 | #include "PchAccess.h"\r | |
22 | #include <Library/IoLib.h>\r | |
23 | #include <Library/UefiLib.h>\r | |
24 | #include <Library/UefiBootServicesTableLib.h>\r | |
25 | #include <Library/PrintLib.h>\r | |
75ce133c | 26 | \r |
27f44846 KM |
27 | //#define SECTOR_SIZE_64KB 0x10000 // Common 64kBytes sector size\r |
28 | //#define ALINGED_SIZE SECTOR_SIZE_64KB\r | |
29 | \r | |
30 | #define BLOCK_SIZE 0x1000\r | |
31 | #define ALINGED_SIZE BLOCK_SIZE\r | |
32 | \r | |
33 | #define R_PCH_LPC_BIOS_CNTL 0xDC\r | |
34 | #define B_PCH_LPC_BIOS_CNTL_SMM_BWP 0x20 ///< SMM BIOS write protect disable\r | |
35 | \r | |
36 | //\r | |
37 | // Prefix Opcode Index on the host SPI controller\r | |
38 | //\r | |
39 | typedef enum {\r | |
40 | SPI_WREN, // Prefix Opcode 0: Write Enable\r | |
41 | SPI_EWSR, // Prefix Opcode 1: Enable Write Status Register\r | |
42 | } PREFIX_OPCODE_INDEX;\r | |
43 | //\r | |
44 | // Opcode Menu Index on the host SPI controller\r | |
45 | //\r | |
46 | typedef enum {\r | |
47 | SPI_READ_ID, // Opcode 0: READ ID, Read cycle with address\r | |
48 | SPI_READ, // Opcode 1: READ, Read cycle with address\r | |
49 | SPI_RDSR, // Opcode 2: Read Status Register, No address\r | |
50 | SPI_WRDI_SFDP, // Opcode 3: Write Disable or Discovery Parameters, No address\r | |
51 | SPI_SERASE, // Opcode 4: Sector Erase (4KB), Write cycle with address\r | |
52 | SPI_BERASE, // Opcode 5: Block Erase (32KB), Write cycle with address\r | |
53 | SPI_PROG, // Opcode 6: Byte Program, Write cycle with address\r | |
54 | SPI_WRSR, // Opcode 7: Write Status Register, No address\r | |
55 | } SPI_OPCODE_INDEX;\r | |
75ce133c JY |
56 | \r |
57 | STATIC EFI_PHYSICAL_ADDRESS mInternalFdAddress;\r | |
58 | \r | |
27f44846 KM |
59 | EFI_SPI_PROTOCOL *mSpiProtocol;\r |
60 | \r | |
61 | /**\r | |
62 | Read NumBytes bytes of data from the address specified by\r | |
63 | PAddress into Buffer.\r | |
64 | \r | |
65 | @param[in] Address The starting physical address of the read.\r | |
66 | @param[in,out] NumBytes On input, the number of bytes to read. On output, the number\r | |
67 | of bytes actually read.\r | |
68 | @param[out] Buffer The destination data buffer for the read.\r | |
69 | \r | |
70 | @retval EFI_SUCCESS Opertion is successful.\r | |
71 | @retval EFI_DEVICE_ERROR If there is any device errors.\r | |
72 | \r | |
73 | **/\r | |
74 | EFI_STATUS\r | |
75 | EFIAPI\r | |
76 | SpiFlashRead (\r | |
77 | IN UINTN Address,\r | |
78 | IN OUT UINT32 *NumBytes,\r | |
79 | OUT UINT8 *Buffer\r | |
80 | )\r | |
81 | {\r | |
82 | EFI_STATUS Status = EFI_SUCCESS;\r | |
83 | UINTN Offset = 0;\r | |
84 | \r | |
85 | ASSERT ((NumBytes != NULL) && (Buffer != NULL));\r | |
86 | \r | |
87 | \r | |
88 | //if (Address >= (UINTN)PcdGet32 (PcdGbeRomBase) && Address < (UINTN)PcdGet32 (PcdPDRRomBase)) {\r | |
89 | Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase);\r | |
90 | \r | |
91 | Status = mSpiProtocol->Execute (\r | |
92 | mSpiProtocol,\r | |
93 | 1, //SPI_READ,\r | |
94 | 0, //SPI_WREN,\r | |
95 | TRUE,\r | |
96 | TRUE,\r | |
97 | FALSE,\r | |
98 | Offset,\r | |
99 | BLOCK_SIZE,\r | |
100 | Buffer,\r | |
101 | EnumSpiRegionAll\r | |
102 | );\r | |
103 | return Status;\r | |
104 | }\r | |
105 | \r | |
106 | /**\r | |
107 | Write NumBytes bytes of data from Buffer to the address specified by\r | |
108 | PAddresss.\r | |
109 | \r | |
110 | @param[in] Address The starting physical address of the write.\r | |
111 | @param[in,out] NumBytes On input, the number of bytes to write. On output,\r | |
112 | the actual number of bytes written.\r | |
113 | @param[in] Buffer The source data buffer for the write.\r | |
114 | \r | |
115 | @retval EFI_SUCCESS Opertion is successful.\r | |
116 | @retval EFI_DEVICE_ERROR If there is any device errors.\r | |
117 | \r | |
118 | **/\r | |
119 | EFI_STATUS\r | |
120 | EFIAPI\r | |
121 | SpiFlashWrite (\r | |
122 | IN UINTN Address,\r | |
123 | IN OUT UINT32 *NumBytes,\r | |
124 | IN UINT8 *Buffer\r | |
125 | )\r | |
126 | {\r | |
127 | EFI_STATUS Status;\r | |
128 | UINTN Offset;\r | |
129 | UINT32 Length;\r | |
130 | UINT32 RemainingBytes;\r | |
131 | \r | |
132 | ASSERT ((NumBytes != NULL) && (Buffer != NULL));\r | |
133 | ASSERT (Address >= (UINTN)PcdGet32 (PcdFlashChipBase));\r | |
134 | \r | |
135 | Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase);\r | |
136 | \r | |
137 | ASSERT ((*NumBytes + Offset) <= (UINTN)PcdGet32 (PcdFlashChipSize));\r | |
138 | \r | |
139 | Status = EFI_SUCCESS;\r | |
140 | RemainingBytes = *NumBytes;\r | |
141 | \r | |
142 | while (RemainingBytes > 0) {\r | |
143 | if (RemainingBytes > SIZE_4KB) {\r | |
144 | Length = SIZE_4KB;\r | |
145 | } else {\r | |
146 | Length = RemainingBytes;\r | |
147 | }\r | |
148 | Status = mSpiProtocol->Execute (\r | |
149 | mSpiProtocol,\r | |
150 | SPI_PROG,\r | |
151 | SPI_WREN,\r | |
152 | TRUE,\r | |
153 | TRUE,\r | |
154 | TRUE,\r | |
155 | (UINT32) Offset,\r | |
156 | Length,\r | |
157 | Buffer,\r | |
158 | EnumSpiRegionAll\r | |
159 | );\r | |
160 | if (EFI_ERROR (Status)) {\r | |
161 | break;\r | |
162 | }\r | |
163 | RemainingBytes -= Length;\r | |
164 | Offset += Length;\r | |
165 | Buffer += Length;\r | |
166 | }\r | |
167 | \r | |
168 | //\r | |
169 | // Actual number of bytes written\r | |
170 | //\r | |
171 | *NumBytes -= RemainingBytes;\r | |
172 | \r | |
173 | return Status;\r | |
174 | }\r | |
175 | \r | |
176 | \r | |
177 | EFI_STATUS\r | |
178 | InternalReadBlock (\r | |
179 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
180 | OUT VOID *ReadBuffer\r | |
181 | )\r | |
182 | {\r | |
183 | EFI_STATUS Status;\r | |
184 | UINT32 BlockSize;\r | |
185 | \r | |
186 | BlockSize = BLOCK_SIZE;\r | |
187 | \r | |
188 | Status = SpiFlashRead ((UINTN) BaseAddress, &BlockSize, ReadBuffer);\r | |
189 | \r | |
190 | return Status;\r | |
191 | }\r | |
192 | \r | |
193 | /**\r | |
194 | Erase the block starting at Address.\r | |
195 | \r | |
196 | @param[in] Address The starting physical address of the block to be erased.\r | |
197 | This library assume that caller garantee that the PAddress\r | |
198 | is at the starting address of this block.\r | |
199 | @param[in] NumBytes On input, the number of bytes of the logical block to be erased.\r | |
200 | On output, the actual number of bytes erased.\r | |
201 | \r | |
202 | @retval EFI_SUCCESS. Opertion is successful.\r | |
203 | @retval EFI_DEVICE_ERROR If there is any device errors.\r | |
204 | \r | |
205 | **/\r | |
206 | EFI_STATUS\r | |
207 | EFIAPI\r | |
208 | SpiFlashBlockErase (\r | |
209 | IN UINTN Address,\r | |
210 | IN UINTN *NumBytes\r | |
211 | )\r | |
212 | {\r | |
213 | EFI_STATUS Status;\r | |
214 | UINTN Offset;\r | |
215 | UINTN RemainingBytes;\r | |
216 | \r | |
217 | ASSERT (NumBytes != NULL);\r | |
218 | ASSERT (Address >= (UINTN)PcdGet32 (PcdFlashChipBase));\r | |
219 | \r | |
220 | Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase);\r | |
221 | \r | |
222 | ASSERT ((*NumBytes % SIZE_4KB) == 0);\r | |
223 | ASSERT ((*NumBytes + Offset) <= (UINTN)PcdGet32 (PcdFlashChipSize));\r | |
224 | \r | |
225 | Status = EFI_SUCCESS;\r | |
226 | RemainingBytes = *NumBytes;\r | |
227 | \r | |
228 | //\r | |
229 | // To adjust the Offset with Bios/Gbe\r | |
230 | //\r | |
231 | // if (Address >= (UINTN)PcdGet32 (PcdFlashChipBase)) {\r | |
232 | // Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase);\r | |
233 | \r | |
234 | while (RemainingBytes > 0) {\r | |
235 | Status = mSpiProtocol->Execute (\r | |
236 | mSpiProtocol,\r | |
237 | SPI_SERASE,\r | |
238 | SPI_WREN,\r | |
239 | FALSE,\r | |
240 | TRUE,\r | |
241 | FALSE,\r | |
242 | (UINT32) Offset,\r | |
243 | 0,\r | |
244 | NULL,\r | |
245 | EnumSpiRegionAll\r | |
246 | );\r | |
247 | if (EFI_ERROR (Status)) {\r | |
248 | break;\r | |
249 | }\r | |
250 | RemainingBytes -= SIZE_4KB;\r | |
251 | Offset += SIZE_4KB;\r | |
252 | }\r | |
253 | // }\r | |
254 | \r | |
255 | //\r | |
256 | // Actual number of bytes erased\r | |
257 | //\r | |
258 | *NumBytes -= RemainingBytes;\r | |
259 | \r | |
260 | return Status;\r | |
261 | }\r | |
262 | \r | |
263 | /**\r | |
264 | \r | |
265 | Routine Description:\r | |
266 | \r | |
267 | Erase the whole block.\r | |
268 | \r | |
269 | Arguments:\r | |
270 | \r | |
271 | BaseAddress - Base address of the block to be erased.\r | |
272 | \r | |
273 | Returns:\r | |
274 | \r | |
275 | EFI_SUCCESS - The command completed successfully.\r | |
276 | Other - Device error or wirte-locked, operation failed.\r | |
277 | \r | |
278 | **/\r | |
279 | EFI_STATUS\r | |
280 | InternalEraseBlock (\r | |
281 | IN EFI_PHYSICAL_ADDRESS BaseAddress\r | |
282 | )\r | |
283 | {\r | |
284 | EFI_STATUS Status;\r | |
285 | UINTN NumBytes;\r | |
286 | \r | |
287 | NumBytes = BLOCK_SIZE;\r | |
288 | \r | |
289 | Status = SpiFlashBlockErase ((UINTN) BaseAddress, &NumBytes);\r | |
290 | \r | |
291 | return Status;\r | |
292 | }\r | |
293 | \r | |
294 | EFI_STATUS\r | |
295 | InternalCompareBlock (\r | |
296 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
297 | IN UINT8 *Buffer\r | |
298 | )\r | |
299 | {\r | |
300 | EFI_STATUS Status;\r | |
301 | VOID *CompareBuffer;\r | |
302 | UINT32 NumBytes;\r | |
303 | INTN CompareResult;\r | |
304 | \r | |
305 | NumBytes = BLOCK_SIZE;\r | |
306 | CompareBuffer = AllocatePool (NumBytes);\r | |
307 | if (CompareBuffer == NULL) {\r | |
308 | Status = EFI_OUT_OF_RESOURCES;\r | |
309 | goto Done;\r | |
310 | }\r | |
311 | \r | |
312 | Status = SpiFlashRead ((UINTN) BaseAddress, &NumBytes, CompareBuffer);\r | |
313 | if (EFI_ERROR (Status)) {\r | |
314 | goto Done;\r | |
315 | }\r | |
316 | CompareResult = CompareMem (CompareBuffer, Buffer, BLOCK_SIZE);\r | |
317 | if (CompareResult != 0) {\r | |
318 | Status = EFI_VOLUME_CORRUPTED;\r | |
319 | }\r | |
320 | \r | |
321 | Done:\r | |
322 | if (CompareBuffer != NULL) {\r | |
323 | FreePool (CompareBuffer);\r | |
324 | }\r | |
325 | \r | |
326 | return Status;\r | |
327 | }\r | |
328 | \r | |
329 | /**\r | |
330 | \r | |
331 | Routine Description:\r | |
332 | \r | |
333 | Write a block of data.\r | |
334 | \r | |
335 | Arguments:\r | |
336 | \r | |
337 | BaseAddress - Base address of the block.\r | |
338 | Buffer - Data buffer.\r | |
339 | BufferSize - Size of the buffer.\r | |
340 | \r | |
341 | Returns:\r | |
342 | \r | |
343 | EFI_SUCCESS - The command completed successfully.\r | |
344 | EFI_INVALID_PARAMETER - Invalid parameter, can not proceed.\r | |
345 | Other - Device error or wirte-locked, operation failed.\r | |
346 | \r | |
347 | **/\r | |
348 | EFI_STATUS\r | |
349 | InternalWriteBlock (\r | |
350 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
351 | IN UINT8 *Buffer,\r | |
352 | IN UINT32 BufferSize\r | |
353 | )\r | |
354 | {\r | |
355 | EFI_STATUS Status;\r | |
356 | \r | |
357 | Status = SpiFlashWrite ((UINTN) BaseAddress, &BufferSize, Buffer);\r | |
358 | \r | |
359 | if (EFI_ERROR (Status)) {\r | |
360 | DEBUG((DEBUG_ERROR, "\nFlash write error."));\r | |
361 | return Status;\r | |
362 | }\r | |
363 | \r | |
364 | WriteBackInvalidateDataCacheRange ((VOID *) (UINTN) BaseAddress, BLOCK_SIZE);\r | |
365 | \r | |
366 | Status = InternalCompareBlock (BaseAddress, Buffer);\r | |
367 | if (EFI_ERROR (Status)) {\r | |
368 | DEBUG((DEBUG_ERROR, "\nError when writing to BaseAddress %x with different at offset %x.", BaseAddress, Status));\r | |
369 | } else {\r | |
370 | DEBUG((DEBUG_INFO, "\nVerified data written to Block at %x is correct.", BaseAddress));\r | |
371 | }\r | |
372 | \r | |
373 | return Status;\r | |
374 | \r | |
375 | }\r | |
376 | \r | |
75ce133c | 377 | /**\r |
20eb921b MK |
378 | Perform flash write operation with progress indicator. The start and end\r |
379 | completion percentage values are passed into this function. If the requested\r | |
380 | flash write operation is broken up, then completion percentage between the\r | |
381 | start and end values may be passed to the provided Progress function. The\r | |
382 | caller of this function is required to call the Progress function for the\r | |
383 | start and end completion percentage values. This allows the Progress,\r | |
384 | StartPercentage, and EndPercentage parameters to be ignored if the requested\r | |
385 | flash write operation can not be broken up\r | |
75ce133c JY |
386 | \r |
387 | @param[in] FirmwareType The type of firmware.\r | |
388 | @param[in] FlashAddress The address of flash device to be accessed.\r | |
389 | @param[in] FlashAddressType The type of flash device address.\r | |
390 | @param[in] Buffer The pointer to the data buffer.\r | |
391 | @param[in] Length The length of data buffer in bytes.\r | |
20eb921b MK |
392 | @param[in] Progress A function used report the progress of the\r |
393 | firmware update. This is an optional parameter\r | |
394 | that may be NULL.\r | |
395 | @param[in] StartPercentage The start completion percentage value that may\r | |
396 | be used to report progress during the flash\r | |
397 | write operation.\r | |
398 | @param[in] EndPercentage The end completion percentage value that may\r | |
399 | be used to report progress during the flash\r | |
400 | write operation.\r | |
75ce133c JY |
401 | \r |
402 | @retval EFI_SUCCESS The operation returns successfully.\r | |
403 | @retval EFI_WRITE_PROTECTED The flash device is read only.\r | |
404 | @retval EFI_UNSUPPORTED The flash device access is unsupported.\r | |
405 | @retval EFI_INVALID_PARAMETER The input parameter is not valid.\r | |
406 | **/\r | |
407 | EFI_STATUS\r | |
408 | EFIAPI\r | |
20eb921b MK |
409 | PerformFlashWriteWithProgress (\r |
410 | IN PLATFORM_FIRMWARE_TYPE FirmwareType,\r | |
411 | IN EFI_PHYSICAL_ADDRESS FlashAddress,\r | |
412 | IN FLASH_ADDRESS_TYPE FlashAddressType,\r | |
413 | IN VOID *Buffer,\r | |
414 | IN UINTN Length,\r | |
415 | IN EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS Progress, OPTIONAL\r | |
416 | IN UINTN StartPercentage,\r | |
417 | IN UINTN EndPercentage\r | |
75ce133c JY |
418 | )\r |
419 | {\r | |
27f44846 KM |
420 | EFI_STATUS Status = EFI_SUCCESS;\r |
421 | UINTN Index;\r | |
422 | EFI_PHYSICAL_ADDRESS Address;\r | |
423 | UINTN CountOfBlocks;\r | |
424 | EFI_TPL OldTpl;\r | |
425 | BOOLEAN FlashError;\r | |
426 | UINT8 *Buf;\r | |
427 | UINTN LpcBaseAddress;\r | |
428 | UINT8 Data8Or;\r | |
429 | UINT8 Data8And;\r | |
430 | UINT8 BiosCntl;\r | |
431 | \r | |
432 | Index = 0;\r | |
433 | Address = 0;\r | |
434 | CountOfBlocks = 0;\r | |
435 | FlashError = FALSE;\r | |
436 | Buf = Buffer;\r | |
75ce133c | 437 | \r |
27f44846 | 438 | DEBUG((DEBUG_INFO | DEBUG_ERROR, "PerformFlashWrite - 0x%x(%x) - 0x%x\n", (UINTN)FlashAddress, (UINTN)FlashAddressType, Length));\r |
75ce133c JY |
439 | if (FlashAddressType == FlashAddressTypeRelativeAddress) {\r |
440 | FlashAddress = FlashAddress + mInternalFdAddress;\r | |
441 | }\r | |
442 | \r | |
27f44846 KM |
443 | CountOfBlocks = (UINTN) (Length / BLOCK_SIZE);\r |
444 | Address = FlashAddress;\r | |
75ce133c | 445 | \r |
27f44846 KM |
446 | LpcBaseAddress = MmPciAddress (0,\r |
447 | DEFAULT_PCI_BUS_NUMBER_PCH,\r | |
448 | PCI_DEVICE_NUMBER_PCH_LPC,\r | |
449 | PCI_FUNCTION_NUMBER_PCH_LPC,\r | |
450 | 0\r | |
451 | );\r | |
452 | BiosCntl = MmioRead8 (LpcBaseAddress + R_PCH_LPC_BIOS_CNTL);\r | |
453 | if ((BiosCntl & B_PCH_LPC_BIOS_CNTL_SMM_BWP) == B_PCH_LPC_BIOS_CNTL_SMM_BWP) {\r | |
454 | ///\r | |
455 | /// Clear SMM_BWP bit (D31:F0:RegDCh[5])\r | |
456 | ///\r | |
457 | Data8And = (UINT8) ~B_PCH_LPC_BIOS_CNTL_SMM_BWP;\r | |
458 | Data8Or = 0x00;\r | |
459 | \r | |
460 | MmioAndThenOr8 (\r | |
461 | LpcBaseAddress + R_PCH_LPC_BIOS_CNTL,\r | |
462 | Data8And,\r | |
463 | Data8Or\r | |
464 | );\r | |
465 | DEBUG((DEBUG_INFO, "PerformFlashWrite Clear SMM_BWP bit\n"));\r | |
466 | }\r | |
467 | \r | |
468 | //\r | |
469 | // Raise TPL to TPL_NOTIFY to block any event handler,\r | |
470 | // while still allowing RaiseTPL(TPL_NOTIFY) within\r | |
471 | // output driver during Print()\r | |
20eb921b | 472 | //\r |
27f44846 KM |
473 | OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r |
474 | for (Index = 0; Index < CountOfBlocks; Index++) {\r | |
20eb921b MK |
475 | if (Progress != NULL) {\r |
476 | Progress (StartPercentage + ((Index * (EndPercentage - StartPercentage)) / CountOfBlocks));\r | |
477 | }\r | |
27f44846 KM |
478 | //\r |
479 | // Handle block based on address and contents.\r | |
480 | //\r | |
481 | if (!EFI_ERROR (InternalCompareBlock (Address, Buf))) {\r | |
482 | DEBUG((DEBUG_INFO, "Skipping block at 0x%lx (already programmed)\n", Address));\r | |
483 | } else {\r | |
27f44846 KM |
484 | //\r |
485 | // Make updating process uninterruptable,\r | |
486 | // so that the flash memory area is not accessed by other entities\r | |
487 | // which may interfere with the updating process\r | |
488 | //\r | |
489 | Status = InternalEraseBlock (Address);\r | |
20eb921b | 490 | if (EFI_ERROR(Status)) {\r |
27f44846 KM |
491 | gBS->RestoreTPL (OldTpl);\r |
492 | FlashError = TRUE;\r | |
493 | goto Done;\r | |
20eb921b | 494 | }\r |
27f44846 KM |
495 | Status = InternalWriteBlock (\r |
496 | Address,\r | |
497 | Buf,\r | |
498 | (UINT32)(Length > BLOCK_SIZE ? BLOCK_SIZE : Length)\r | |
499 | );\r | |
20eb921b | 500 | if (EFI_ERROR(Status)) {\r |
27f44846 KM |
501 | gBS->RestoreTPL (OldTpl);\r |
502 | FlashError = TRUE;\r | |
503 | goto Done;\r | |
504 | }\r | |
20eb921b | 505 | }\r |
75ce133c | 506 | \r |
27f44846 KM |
507 | //\r |
508 | // Move to next block to update.\r | |
509 | //\r | |
510 | Address += BLOCK_SIZE;\r | |
511 | Buf += BLOCK_SIZE;\r | |
512 | if (Length > BLOCK_SIZE) {\r | |
513 | Length -= BLOCK_SIZE;\r | |
514 | } else {\r | |
515 | Length = 0;\r | |
516 | }\r | |
517 | }\r | |
518 | gBS->RestoreTPL (OldTpl);\r | |
519 | \r | |
20eb921b | 520 | Done:\r |
27f44846 KM |
521 | if ((BiosCntl & B_PCH_LPC_BIOS_CNTL_SMM_BWP) == B_PCH_LPC_BIOS_CNTL_SMM_BWP) {\r |
522 | //\r | |
523 | // Restore original control setting\r | |
524 | //\r | |
525 | MmioWrite8 (LpcBaseAddress + R_PCH_LPC_BIOS_CNTL, BiosCntl);\r | |
20eb921b | 526 | }\r |
27f44846 | 527 | \r |
20eb921b MK |
528 | if (Progress != NULL) {\r |
529 | Progress (EndPercentage);\r | |
27f44846 | 530 | }\r |
75ce133c | 531 | \r |
3eac7496 MK |
532 | if (FlashError) {\r |
533 | return EFI_WRITE_PROTECTED;\r | |
534 | }\r | |
535 | \r | |
75ce133c JY |
536 | return EFI_SUCCESS;\r |
537 | }\r | |
538 | \r | |
539 | /**\r | |
20eb921b MK |
540 | Perform flash write operation.\r |
541 | \r | |
542 | @param[in] FirmwareType The type of firmware.\r | |
543 | @param[in] FlashAddress The address of flash device to be accessed.\r | |
544 | @param[in] FlashAddressType The type of flash device address.\r | |
545 | @param[in] Buffer The pointer to the data buffer.\r | |
546 | @param[in] Length The length of data buffer in bytes.\r | |
547 | \r | |
548 | @retval EFI_SUCCESS The operation returns successfully.\r | |
549 | @retval EFI_WRITE_PROTECTED The flash device is read only.\r | |
550 | @retval EFI_UNSUPPORTED The flash device access is unsupported.\r | |
551 | @retval EFI_INVALID_PARAMETER The input parameter is not valid.\r | |
552 | **/\r | |
553 | EFI_STATUS\r | |
554 | EFIAPI\r | |
555 | PerformFlashWrite (\r | |
556 | IN PLATFORM_FIRMWARE_TYPE FirmwareType,\r | |
557 | IN EFI_PHYSICAL_ADDRESS FlashAddress,\r | |
558 | IN FLASH_ADDRESS_TYPE FlashAddressType,\r | |
559 | IN VOID *Buffer,\r | |
560 | IN UINTN Length\r | |
561 | )\r | |
562 | {\r | |
563 | return PerformFlashWriteWithProgress (\r | |
564 | FirmwareType,\r | |
565 | FlashAddress,\r | |
566 | FlashAddressType,\r | |
567 | Buffer,\r | |
568 | Length,\r | |
569 | NULL,\r | |
570 | 0,\r | |
571 | 0\r | |
572 | );\r | |
573 | }\r | |
574 | \r | |
575 | /**\r | |
576 | Perform microcode write operation.\r | |
75ce133c JY |
577 | \r |
578 | @param[in] FlashAddress The address of flash device to be accessed.\r | |
579 | @param[in] Buffer The pointer to the data buffer.\r | |
580 | @param[in] Length The length of data buffer in bytes.\r | |
581 | \r | |
582 | @retval EFI_SUCCESS The operation returns successfully.\r | |
583 | @retval EFI_WRITE_PROTECTED The flash device is read only.\r | |
584 | @retval EFI_UNSUPPORTED The flash device access is unsupported.\r | |
585 | @retval EFI_INVALID_PARAMETER The input parameter is not valid.\r | |
586 | **/\r | |
587 | EFI_STATUS\r | |
588 | EFIAPI\r | |
589 | MicrocodeFlashWrite (\r | |
590 | IN EFI_PHYSICAL_ADDRESS FlashAddress,\r | |
591 | IN VOID *Buffer,\r | |
592 | IN UINTN Length\r | |
593 | )\r | |
594 | {\r | |
595 | EFI_PHYSICAL_ADDRESS AlignedFlashAddress;\r | |
596 | VOID *AlignedBuffer;\r | |
597 | UINTN AlignedLength;\r | |
598 | UINTN OffsetHead;\r | |
599 | UINTN OffsetTail;\r | |
600 | EFI_STATUS Status;\r | |
601 | \r | |
602 | DEBUG((DEBUG_INFO, "MicrocodeFlashWrite - 0x%x - 0x%x\n", (UINTN)FlashAddress, Length));\r | |
603 | \r | |
604 | //\r | |
605 | // Need make buffer 64K aligned to support ERASE\r | |
606 | //\r | |
607 | // [Aligned] FlashAddress [Aligned]\r | |
608 | // | | |\r | |
609 | // V V V\r | |
610 | // +--------------+========+------------+\r | |
611 | // | OffsetHeader | Length | OffsetTail |\r | |
612 | // +--------------+========+------------+\r | |
613 | // ^\r | |
614 | // |<-----------AlignedLength----------->\r | |
615 | // |\r | |
616 | // AlignedFlashAddress\r | |
617 | //\r | |
618 | OffsetHead = FlashAddress & (ALINGED_SIZE - 1);\r | |
619 | OffsetTail = (FlashAddress + Length) & (ALINGED_SIZE - 1);\r | |
620 | if (OffsetTail != 0) {\r | |
621 | OffsetTail = ALINGED_SIZE - OffsetTail;\r | |
622 | }\r | |
623 | \r | |
624 | if ((OffsetHead != 0) || (OffsetTail != 0)) {\r | |
625 | AlignedFlashAddress = FlashAddress - OffsetHead;\r | |
626 | AlignedLength = Length + OffsetHead + OffsetTail;\r | |
627 | \r | |
628 | AlignedBuffer = AllocatePool(AlignedLength);\r | |
629 | if (AlignedBuffer == NULL) {\r | |
630 | return EFI_OUT_OF_RESOURCES;\r | |
631 | }\r | |
632 | //\r | |
633 | // Save original buffer\r | |
634 | //\r | |
635 | if (OffsetHead != 0) {\r | |
71d86ec8 | 636 | CopyMem((UINT8 *)AlignedBuffer, (VOID *)(UINTN)AlignedFlashAddress, OffsetHead);\r |
75ce133c JY |
637 | }\r |
638 | if (OffsetTail != 0) {\r | |
71d86ec8 | 639 | CopyMem((UINT8 *)AlignedBuffer + OffsetHead + Length, (VOID *)(UINTN)(AlignedFlashAddress + OffsetHead + Length), OffsetTail);\r |
75ce133c JY |
640 | }\r |
641 | //\r | |
642 | // Override new buffer\r | |
643 | //\r | |
644 | CopyMem((UINT8 *)AlignedBuffer + OffsetHead, Buffer, Length);\r | |
645 | } else {\r | |
646 | AlignedFlashAddress = FlashAddress;\r | |
647 | AlignedBuffer = Buffer;\r | |
648 | AlignedLength = Length;\r | |
649 | }\r | |
650 | \r | |
651 | Status = PerformFlashWrite(\r | |
652 | PlatformFirmwareTypeSystemFirmware,\r | |
653 | AlignedFlashAddress,\r | |
654 | FlashAddressTypeAbsoluteAddress,\r | |
655 | AlignedBuffer,\r | |
656 | AlignedLength\r | |
657 | );\r | |
658 | if ((OffsetHead != 0) || (OffsetTail != 0)) {\r | |
659 | FreePool (AlignedBuffer);\r | |
660 | }\r | |
661 | return Status;\r | |
662 | }\r | |
663 | \r | |
664 | /**\r | |
665 | Platform Flash Access Lib Constructor.\r | |
666 | **/\r | |
667 | EFI_STATUS\r | |
668 | EFIAPI\r | |
669 | PerformFlashAccessLibConstructor (\r | |
670 | VOID\r | |
671 | )\r | |
672 | {\r | |
27f44846 | 673 | EFI_STATUS Status;\r |
75ce133c JY |
674 | mInternalFdAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32(PcdFlashAreaBaseAddress);\r |
675 | DEBUG((DEBUG_INFO, "PcdFlashAreaBaseAddress - 0x%x\n", mInternalFdAddress));\r | |
676 | \r | |
27f44846 KM |
677 | Status = gBS->LocateProtocol (\r |
678 | &gEfiSpiProtocolGuid,\r | |
679 | NULL,\r | |
680 | (VOID **) &mSpiProtocol\r | |
681 | );\r | |
682 | ASSERT_EFI_ERROR(Status);\r | |
683 | \r | |
75ce133c JY |
684 | return EFI_SUCCESS;\r |
685 | }\r |