projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /*++\r |
| 2 | \r | |
| 3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
| 4 | \r\r | |
| 9dc8036d MK |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 6 | \r | |
| 3cbfba02 DW |
7 | \r\r |
| 8 | \r | |
| 9 | \r | |
| 10 | Module Name:\r | |
| 11 | \r | |
| 12 | PlatformCpuInfo.h\r | |
| 13 | \r | |
| 14 | Abstract:\r | |
| 15 | \r | |
| 16 | GUID used for Platform CPU Info Data entries in the HOB list.\r | |
| 17 | \r | |
| 18 | --*/\r | |
| 19 | \r | |
| 20 | #ifndef _PLATFORM_CPU_INFO_GUID_H_\r | |
| 21 | #define _PLATFORM_CPU_INFO_GUID_H_\r | |
| 22 | \r | |
| 23 | #include "CpuType.h"\r | |
| 24 | #include <Library/CpuIA32.h>\r | |
| 25 | \r | |
| 26 | #define EFI_PLATFORM_CPU_INFO_GUID \\r | |
| 27 | {\\r | |
| 28 | 0xbb9c7ab7, 0xb8d9, 0x4bf3, 0x9c, 0x29, 0x9b, 0xf3, 0x41, 0xe2, 0x17, 0xbc \\r | |
| 29 | }\r | |
| 30 | \r | |
| 31 | extern EFI_GUID gEfiPlatformCpuInfoGuid;\r | |
| 32 | extern CHAR16 EfiPlatformCpuInfoVariable[];\r | |
| 33 | \r | |
| 34 | //\r | |
| 35 | // Tri-state for feature capabilities and enable/disable.\r | |
| 36 | // [0] clear=feature isn't capable\r | |
| 37 | // [0] set =feature is capable\r | |
| 38 | // [1] clear=feature is disabled\r | |
| 39 | // [1] set =feature is enabled\r | |
| 40 | //\r | |
| 41 | #define CPU_FEATURES_CAPABLE BIT0\r | |
| 42 | #define CPU_FEATURES_ENABLE BIT1\r | |
| 43 | \r | |
| 44 | #define MAX_CACHE_DESCRIPTORS 64\r | |
| 45 | #define MAXIMUM_CPU_BRAND_STRING_LENGTH 48\r | |
| 46 | \r | |
| 47 | #pragma pack(1)\r | |
| 48 | \r | |
| 49 | typedef struct {\r | |
| 50 | UINT32 FullCpuId; // [31:0] & 0x0FFF0FFF\r | |
| 51 | UINT32 FullFamilyModelId; // [31:0] & 0x0FFF0FF0\r | |
| 52 | UINT8 ExtendedFamilyId; // [27:20]\r | |
| 53 | UINT8 ExtendedModelId; // [19:16]\r | |
| 54 | UINT8 ProcessorType; // [13:11]\r | |
| 55 | UINT8 FamilyId; // [11:8]\r | |
| 56 | UINT8 Model; // [7:4]\r | |
| 57 | UINT8 SteppingId; // [3:0]\r | |
| 58 | } EFI_CPU_VERSION_INFO; // CPUID.1.EAX\r | |
| 59 | \r | |
| 60 | typedef struct {\r | |
| 61 | UINT32 L1InstructionCacheSize;\r | |
| 62 | UINT32 L1DataCacheSize;\r | |
| 63 | UINT32 L2CacheSize;\r | |
| 64 | UINT32 L3CacheSize;\r | |
| 65 | UINT32 TraceCacheSize;\r | |
| 66 | UINT8 CacheDescriptor[MAX_CACHE_DESCRIPTORS];\r | |
| 67 | } EFI_CPU_CACHE_INFO; // CPUID.2.EAX\r | |
| 68 | \r | |
| 69 | typedef struct {\r | |
| 70 | UINT8 PhysicalPackages;\r | |
| 71 | UINT8 LogicalProcessorsPerPhysicalPackage;\r | |
| 72 | UINT8 CoresPerPhysicalPackage;\r | |
| 73 | UINT8 ThreadsPerCore;\r | |
| 74 | } EFI_CPU_PACKAGE_INFO; // CPUID.4.EAX\r | |
| 75 | \r | |
| 76 | typedef struct {\r | |
| 77 | UINT32 RegEdx; // CPUID.5.EAX\r | |
| 78 | UINT8 MaxCState;\r | |
| 79 | UINT8 C0SubCStatesMwait; // EDX [3:0]\r | |
| 80 | UINT8 C1SubCStatesMwait; // EDX [7:4]\r | |
| 81 | UINT8 C2SubCStatesMwait; // EDX [11:8]\r | |
| 82 | UINT8 C3SubCStatesMwait; // EDX [15:12]\r | |
| 83 | UINT8 C4SubCStatesMwait; // EDX [19:16]\r | |
| 84 | UINT8 C5SubCStatesMwait; // EDX [23:20]\r | |
| 85 | UINT8 C6SubCStatesMwait; // EDX [27:24]\r | |
| 86 | UINT8 C7SubCStatesMwait; // EDX [31:28]\r | |
| 87 | UINT8 MonitorMwaitSupport; // ECX [0]\r | |
| 88 | UINT8 InterruptsBreakMwait; // ECX [1]\r | |
| 89 | } EFI_CPU_CSTATE_INFO; // CPUID.5.EAX\r | |
| 90 | \r | |
| 91 | typedef struct {\r | |
| 92 | UINT8 Turbo; // EAX [1]\r | |
| 93 | UINT8 PECI; // EAX [0]\r | |
| 94 | UINT8 NumIntThresholds; // EBX [3:0]\r | |
| 95 | UINT8 HwCoordinationFeedback; // ECX [0]\r | |
| 96 | } EFI_CPU_POWER_MANAGEMENT; // CPUID.6.EAX\r | |
| 97 | \r | |
| 98 | //\r | |
| 99 | // IMPORTANT: Each CPU feature enabling entry is assumed a tri-state variable.\r | |
| 100 | // - Keep the respective feature entry variable as default value (0x00)\r | |
| 101 | // if the CPU is not capable for the feature.\r | |
| 102 | // - Use the specially defined programming convention to update the variable\r | |
| 103 | // to indicate capable, enable or disable.\r | |
| 104 | // ie. F_CAPABLE for feature available\r | |
| 105 | // F_ENABLE for feature enable\r | |
| 106 | // F_DISABLE for feature disable\r | |
| 107 | //\r | |
| 108 | typedef struct {\r | |
| 109 | EFI_CPUID_REGISTER Regs; // CPUID.1.EAX\r | |
| 110 | UINT8 Xapic; // ECX [21]\r | |
| 111 | UINT8 SSE4_2; // ECX [20]\r | |
| 112 | UINT8 SSE4_1; // ECX [19]\r | |
| 113 | UINT8 Dca; // ECX [18]\r | |
| 114 | UINT8 SupSSE3; // ECX [9]\r | |
| 115 | UINT8 Tm2; // ECX [8]\r | |
| 116 | UINT8 Eist; // ECX [7]\r | |
| 117 | UINT8 Lt; // ECX [6]\r | |
| 118 | UINT8 Vt; // ECX [5]\r | |
| 119 | UINT8 Mwait; // ECX [3]\r | |
| 120 | UINT8 SSE3; // ECX [0]\r | |
| 121 | UINT8 Tcc; // EDX [29]\r | |
| 122 | UINT8 Mt; // EDX [28]\r | |
| 123 | UINT8 SSE2; // EDX [26]\r | |
| 124 | UINT8 SSE; // EDX [25]\r | |
| 125 | UINT8 MMX; // EDX [23]\r | |
| 126 | EFI_CPUID_REGISTER ExtRegs; // CPUID.80000001.EAX\r | |
| 127 | UINT8 ExtLahfSahf64; // ECX [0]\r | |
| 128 | UINT8 ExtIntel64; // EDX [29]\r | |
| 129 | UINT8 ExtXd; // EDX [20]\r | |
| 130 | UINT8 ExtSysCallRet64; // EDX [11]\r | |
| 131 | UINT16 Ht; // CPUID.0B.EAX EBX [15:0]\r | |
| 132 | } EFI_CPU_FEATURES; // CPUID.1.EAX, CPUID.0B.EAX, CPUID.80000001.EAX\r | |
| 133 | \r | |
| 134 | typedef struct {\r | |
| 135 | UINT8 PhysicalBits;\r | |
| 136 | UINT8 VirtualBits;\r | |
| 137 | } EFI_CPU_ADDRESS_BITS; // CPUID.80000008.EAX\r | |
| 138 | \r | |
| 139 | typedef struct {\r | |
| 140 | UINT8 PlatformID; // MSR 0x17 [52:50]\r | |
| 141 | UINT32 MicrocodeRevision; // MSR 0x8B [63:32]\r | |
| 142 | UINT8 MaxEfficiencyRatio; // MSR 0xCE [47:40]\r | |
| 143 | UINT8 DdrRatioUnlockCap; // MSR 0xCE [30]\r | |
| 144 | UINT8 TdcTdpLimitsTurbo; // MSR 0xCE [29]\r | |
| 145 | UINT8 RatioLimitsTurbo; // MSR 0xCE [28]\r | |
| 146 | UINT8 PreProduction; // MSR 0xCE [27]\r | |
| 147 | UINT8 DcuModeSelect; // MSR 0xCE [26]\r | |
| 148 | UINT8 MaxNonTurboRatio; // MSR 0xCE [15:8]\r | |
| 149 | UINT8 Emrr; // MSR 0xFE [12]\r | |
| 150 | UINT8 Smrr; // MSR 0xFE [11]\r | |
| 151 | UINT8 VariableMtrrCount; // MSR 0xFE [7:0]\r | |
| 152 | UINT16 PState; // MSR 0x198 [15:0]\r | |
| 153 | UINT8 TccActivationTemperature; // MSR 0x1A2 [23:16]\r | |
| 154 | UINT8 TemperatureControlOffset; // MSR 0x1A2 [15:8]\r | |
| 155 | UINT32 PCIeBar; // MSR 0x300 [39:20]\r | |
| 156 | UINT8 PCIeBarSizeMB; // MSR 0x300 [3:1]\r | |
| 157 | } EFI_MSR_FEATURES;\r | |
| 158 | \r | |
| 159 | typedef struct {\r | |
| 160 | BOOLEAN IsIntelProcessor;\r | |
| 161 | UINT8 BrandString[MAXIMUM_CPU_BRAND_STRING_LENGTH + 1];\r | |
| 162 | UINT32 CpuidMaxInputValue;\r | |
| 163 | UINT32 CpuidMaxExtInputValue;\r | |
| 164 | EFI_CPU_UARCH CpuUarch;\r | |
| 165 | EFI_CPU_FAMILY CpuFamily;\r | |
| 166 | EFI_CPU_PLATFORM CpuPlatform;\r | |
| 167 | EFI_CPU_TYPE CpuType;\r | |
| 168 | EFI_CPU_VERSION_INFO CpuVersion;\r | |
| 169 | EFI_CPU_CACHE_INFO CpuCache;\r | |
| 170 | EFI_CPU_FEATURES CpuFeatures;\r | |
| 171 | EFI_CPU_CSTATE_INFO CpuCState;\r | |
| 172 | EFI_CPU_PACKAGE_INFO CpuPackage;\r | |
| 173 | EFI_CPU_POWER_MANAGEMENT CpuPowerManagement;\r | |
| 174 | EFI_CPU_ADDRESS_BITS CpuAddress;\r | |
| 175 | EFI_MSR_FEATURES Msr;\r | |
| 176 | } EFI_PLATFORM_CPU_INFO;\r | |
| 177 | \r | |
| 178 | #pragma pack()\r | |
| 179 | \r | |
| 180 | #endif\r |