[mirror_edk2.git] / Vlv2TbltDevicePkg / Include / Library / EfiRegTableLib.h

/*++\r
\r
  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
                                                                                   \r\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
                                                                                   \r\r
\r
\r
Module Name:\r
\r
  EfiRegTableLib.h\r
\r
Abstract:\r
\r
  Definitions and macros for building register tables for chipset\r
  initialization..\r
\r
  Components linking this lib must include CpuIo, PciRootBridgeIo, and\r
  BootScriptSave protocols in their DPX.\r
\r
\r
\r
--*/\r
\r
#ifndef EFI_REG_TABLE_H\r
#define EFI_REG_TABLE_H\r
\r
\r
#include <PiDxe.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/UefiDriverEntryPoint.h>\r
#include <Protocol/CpuIo.h>\r
#include <Protocol/BootScriptSave.h>\r
#include <Framework/BootScript.h>\r
#include <Protocol/PciRootBridgeIo.h>\r
\r
\r
#define OPCODE_BASE(OpCode)       ((UINT8)((OpCode) & 0xFF))\r
#define OPCODE_FLAGS(OpCode)      ((UINT8)(((OpCode) >> 8) & 0xFF))\r
#define OPCODE_EXTRA_DATA(OpCode) ((UINT16)((OpCode) >> 16))\r
\r
//\r
// RegTable Base OpCodes\r
//\r
#define OP_TERMINATE_TABLE                0\r
#define OP_MEM_WRITE                      1\r
#define OP_MEM_READ_MODIFY_WRITE          2\r
#define OP_IO_WRITE                       3\r
#define OP_IO_READ_MODIFY_WRITE           4\r
#define OP_PCI_WRITE                      5\r
#define OP_PCI_READ_MODIFY_WRITE          6\r
#define OP_STALL                          7\r
\r
//\r
// RegTable OpCode Flags\r
//\r
#define OPCODE_FLAG_S3SAVE                1\r
\r
\r
#define TERMINATE_TABLE { (UINT32) OP_TERMINATE_TABLE, (UINT32) 0, (UINT32) 0 }\r
\r
\r
//\r
// REG_TABLE_ENTRY_PCI_WRITE encodes the width in the upper bits of the OpCode\r
// as one of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH values\r
//\r
typedef struct {\r
  UINT32                                OpCode;\r
  UINT32                                PciAddress;\r
  UINT32                                Data;\r
} EFI_REG_TABLE_PCI_WRITE;\r
\r
#define PCI_WRITE(Bus, Dev, Fnc, Reg, Width, Data, S3Flag)                    \\r
  {                                                                           \\r
    (UINT32) (OP_PCI_WRITE | ((S3Flag) << 8) | ((Width) << 16)),              \\r
    (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))),                  \\r
    (UINT32) (Data),                                                          \\r
    (UINT32) (0)                                                              \\r
  }\r
\r
typedef struct {\r
  UINT32                                OpCode;\r
  UINT32                                MemAddress;\r
  UINT32                                Data;\r
} EFI_REG_TABLE_MEM_WRITE;\r
\r
typedef struct {\r
  UINT32                                OpCode;\r
  UINT32                                PciAddress;\r
  UINT32                                OrMask;\r
  UINT32                                AndMask;\r
} EFI_REG_TABLE_PCI_READ_MODIFY_WRITE;\r
\r
#define PCI_READ_MODIFY_WRITE(Bus, Dev, Fnc, Reg, Width, OrMask, AndMask, S3Flag)  \\r
  {                                                                           \\r
    (UINT32) (OP_PCI_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)),  \\r
    (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))),                  \\r
    (UINT32) (OrMask),                                                        \\r
    (UINT32) (AndMask)                                                        \\r
  }\r
\r
typedef struct {\r
  UINT32                                OpCode;\r
  UINT32                                MemAddress;\r
  UINT32                                OrMask;\r
  UINT32                                AndMask;\r
} EFI_REG_TABLE_MEM_READ_MODIFY_WRITE;\r
\r
#define MEM_READ_MODIFY_WRITE(Address, Width, OrMask, AndMask, S3Flag)  \\r
  {                                                                           \\r
    (UINT32) (OP_MEM_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)),  \\r
    (UINT32) (Address),                  \\r
    (UINT32) (OrMask),                                                        \\r
    (UINT32) (AndMask)                                                        \\r
  }\r
\r
typedef struct {\r
  UINT32                                OpCode;\r
  UINT32                                Field2;\r
  UINT32                                Field3;\r
  UINT32                                Field4;\r
} EFI_REG_TABLE_GENERIC;\r
\r
typedef union {\r
  EFI_REG_TABLE_GENERIC                 Generic;\r
  EFI_REG_TABLE_PCI_WRITE               PciWrite;\r
  EFI_REG_TABLE_PCI_READ_MODIFY_WRITE   PciReadModifyWrite;\r
  EFI_REG_TABLE_MEM_READ_MODIFY_WRITE   MemReadModifyWrite;\r
} EFI_REG_TABLE;\r
\r
/**\r
  Processes register table assuming which may contain PCI, IO, MEM, and STALL\r
  entries.\r
\r
  No parameter checking is done so the caller must be careful about omitting\r
  values for PciRootBridgeIo or CpuIo parameters.  If the regtable does\r
  not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply\r
  NULL).  If the regtable does not contain any IO or Mem entries, it is safe to\r
  omit the CpuIo (supply NULL).\r
\r
  The RegTableEntry parameter is not checked, but is required.\r
\r
  gBS is assumed to have been defined and is used when processing stalls.\r
\r
  The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
  entry is encountered.\r
\r
  @param[in] RegTableEntry    A pointer to the register table to process\r
\r
  @param[in] PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used\r
                              when processing PCI table entries\r
\r
  @param[in] CpuIo            A pointer to the instance of CpuIo that is used when processing IO and\r
                              MEM table entries\r
\r
  @retval Nothing.\r
\r
**/\r
VOID\r
ProcessRegTablePci (\r
  EFI_REG_TABLE                   * RegTableEntry,\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL * PciRootBridgeIo,\r
  EFI_CPU_IO_PROTOCOL             * CpuIo\r
  );\r
\r
/**\r
  Processes register table assuming which may contain IO, MEM, and STALL\r
  entries, but must NOT contain any PCI entries.  Any PCI entries cause an\r
  ASSERT in a DEBUG build and are skipped in a free build.\r
\r
  No parameter checking is done.  Both RegTableEntry and CpuIo parameters are\r
  required.\r
\r
  gBS is assumed to have been defined and is used when processing stalls.\r
\r
  The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
  entry is encountered.\r
\r
  @param[in] RegTableEntry - A pointer to the register table to process\r
\r
  @param[in] CpuIo - A pointer to the instance of CpuIo that is used when processing IO and\r
                  MEM table entries\r
\r
  @retval Nothing.\r
\r
**/\r
VOID\r
ProcessRegTableCpu (\r
  EFI_REG_TABLE                   * RegTableEntry,\r
  EFI_CPU_IO_PROTOCOL             * CpuIo\r
  );\r
\r
#endif\r
Commit	Line	Data
3cbfba02 DW	1	/*++\r
	2	\r
	3	Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
	4	\r\r
9dc8036d MK	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
9dc8036d MK	6	\r
3cbfba02 DW	7	\r\r
	8	\r
	9	\r
	10	Module Name:\r
	11	\r
	12	EfiRegTableLib.h\r
	13	\r
	14	Abstract:\r
	15	\r
	16	Definitions and macros for building register tables for chipset\r
	17	initialization..\r
	18	\r
	19	Components linking this lib must include CpuIo, PciRootBridgeIo, and\r
	20	BootScriptSave protocols in their DPX.\r
	21	\r
	22	\r
	23	\r
	24	--*/\r
	25	\r
	26	#ifndef EFI_REG_TABLE_H\r
	27	#define EFI_REG_TABLE_H\r
	28	\r
	29	\r
	30	#include <PiDxe.h>\r
	31	#include <Library/BaseLib.h>\r
	32	#include <Library/DebugLib.h>\r
	33	#include <Library/UefiLib.h>\r
	34	#include <Library/UefiDriverEntryPoint.h>\r
	35	#include <Protocol/CpuIo.h>\r
	36	#include <Protocol/BootScriptSave.h>\r
	37	#include <Framework/BootScript.h>\r
	38	#include <Protocol/PciRootBridgeIo.h>\r
	39	\r
	40	\r
	41	#define OPCODE_BASE(OpCode) ((UINT8)((OpCode) & 0xFF))\r
	42	#define OPCODE_FLAGS(OpCode) ((UINT8)(((OpCode) >> 8) & 0xFF))\r
	43	#define OPCODE_EXTRA_DATA(OpCode) ((UINT16)((OpCode) >> 16))\r
	44	\r
	45	//\r
	46	// RegTable Base OpCodes\r
	47	//\r
	48	#define OP_TERMINATE_TABLE 0\r
	49	#define OP_MEM_WRITE 1\r
	50	#define OP_MEM_READ_MODIFY_WRITE 2\r
	51	#define OP_IO_WRITE 3\r
	52	#define OP_IO_READ_MODIFY_WRITE 4\r
	53	#define OP_PCI_WRITE 5\r
	54	#define OP_PCI_READ_MODIFY_WRITE 6\r
	55	#define OP_STALL 7\r
	56	\r
	57	//\r
	58	// RegTable OpCode Flags\r
	59	//\r
	60	#define OPCODE_FLAG_S3SAVE 1\r
	61	\r
	62	\r
	63	#define TERMINATE_TABLE { (UINT32) OP_TERMINATE_TABLE, (UINT32) 0, (UINT32) 0 }\r
	64	\r
	65	\r
	66	//\r
	67	// REG_TABLE_ENTRY_PCI_WRITE encodes the width in the upper bits of the OpCode\r
	68	// as one of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH values\r
	69	//\r
	70	typedef struct {\r
71	UINT32 OpCode;\r
72	UINT32 PciAddress;\r
73	UINT32 Data;\r
74	} EFI_REG_TABLE_PCI_WRITE;\r
75	\r
76	#define PCI_WRITE(Bus, Dev, Fnc, Reg, Width, Data, S3Flag) \\r
77	{ \\r
78	(UINT32) (OP_PCI_WRITE \| ((S3Flag) << 8) \| ((Width) << 16)), \\r
79	(UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \\r
80	(UINT32) (Data), \\r
81	(UINT32) (0) \\r
82	}\r
83	\r
84	typedef struct {\r
85	UINT32 OpCode;\r
86	UINT32 MemAddress;\r
87	UINT32 Data;\r
88	} EFI_REG_TABLE_MEM_WRITE;\r
89	\r
90	typedef struct {\r
91	UINT32 OpCode;\r
92	UINT32 PciAddress;\r
93	UINT32 OrMask;\r
94	UINT32 AndMask;\r
95	} EFI_REG_TABLE_PCI_READ_MODIFY_WRITE;\r
96	\r
97	#define PCI_READ_MODIFY_WRITE(Bus, Dev, Fnc, Reg, Width, OrMask, AndMask, S3Flag) \\r
98	{ \\r
99	(UINT32) (OP_PCI_READ_MODIFY_WRITE \| ((S3Flag) << 8) \| ((Width) << 16)), \\r
100	(UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \\r
101	(UINT32) (OrMask), \\r
102	(UINT32) (AndMask) \\r
103	}\r
104	\r
105	typedef struct {\r
106	UINT32 OpCode;\r
107	UINT32 MemAddress;\r
108	UINT32 OrMask;\r
109	UINT32 AndMask;\r
110	} EFI_REG_TABLE_MEM_READ_MODIFY_WRITE;\r
111	\r
112	#define MEM_READ_MODIFY_WRITE(Address, Width, OrMask, AndMask, S3Flag) \\r
113	{ \\r
114	(UINT32) (OP_MEM_READ_MODIFY_WRITE \| ((S3Flag) << 8) \| ((Width) << 16)), \\r
115	(UINT32) (Address), \\r
116	(UINT32) (OrMask), \\r
117	(UINT32) (AndMask) \\r
118	}\r
119	\r
120	typedef struct {\r
121	UINT32 OpCode;\r
122	UINT32 Field2;\r
123	UINT32 Field3;\r
124	UINT32 Field4;\r
125	} EFI_REG_TABLE_GENERIC;\r
126	\r
127	typedef union {\r
128	EFI_REG_TABLE_GENERIC Generic;\r
129	EFI_REG_TABLE_PCI_WRITE PciWrite;\r
130	EFI_REG_TABLE_PCI_READ_MODIFY_WRITE PciReadModifyWrite;\r
131	EFI_REG_TABLE_MEM_READ_MODIFY_WRITE MemReadModifyWrite;\r
132	} EFI_REG_TABLE;\r
133	\r
134	/**\r
135	Processes register table assuming which may contain PCI, IO, MEM, and STALL\r
136	entries.\r
137	\r
138	No parameter checking is done so the caller must be careful about omitting\r
139	values for PciRootBridgeIo or CpuIo parameters. If the regtable does\r
140	not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply\r
141	NULL). If the regtable does not contain any IO or Mem entries, it is safe to\r
142	omit the CpuIo (supply NULL).\r
143	\r
144	The RegTableEntry parameter is not checked, but is required.\r
145	\r
146	gBS is assumed to have been defined and is used when processing stalls.\r
147	\r
148	The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
149	entry is encountered.\r
150	\r
151	@param[in] RegTableEntry A pointer to the register table to process\r
152	\r
153	@param[in] PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used\r
154	when processing PCI table entries\r
155	\r
156	@param[in] CpuIo A pointer to the instance of CpuIo that is used when processing IO and\r
157	MEM table entries\r
158	\r
159	@retval Nothing.\r
160	\r
161	**/\r
162	VOID\r
163	ProcessRegTablePci (\r
164	EFI_REG_TABLE * RegTableEntry,\r
165	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL * PciRootBridgeIo,\r
166	EFI_CPU_IO_PROTOCOL * CpuIo\r
167	);\r
168	\r
169	/**\r
170	Processes register table assuming which may contain IO, MEM, and STALL\r
171	entries, but must NOT contain any PCI entries. Any PCI entries cause an\r
172	ASSERT in a DEBUG build and are skipped in a free build.\r
173	\r
174	No parameter checking is done. Both RegTableEntry and CpuIo parameters are\r
175	required.\r
176	\r
177	gBS is assumed to have been defined and is used when processing stalls.\r
178	\r
179	The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
180	entry is encountered.\r
181	\r
182	@param[in] RegTableEntry - A pointer to the register table to process\r
183	\r
184	@param[in] CpuIo - A pointer to the instance of CpuIo that is used when processing IO and\r
185	MEM table entries\r
186	\r
187	@retval Nothing.\r
188	\r
189	**/\r
190	VOID\r
191	ProcessRegTableCpu (\r
192	EFI_REG_TABLE * RegTableEntry,\r
193	EFI_CPU_IO_PROTOCOL * CpuIo\r
194	);\r
195	\r
196	#endif\r