projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /*++\r |
| 2 | \r | |
| 3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
| 4 | \r\r | |
| 9dc8036d MK |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 6 | \r | |
| 3cbfba02 DW |
7 | \r\r |
| 8 | \r | |
| 9 | \r | |
| 10 | Module Name:\r | |
| 11 | \r | |
| 12 | Platform.h\r | |
| 13 | \r | |
| 14 | Abstract:\r | |
| 15 | \r | |
| 16 | Pinetrail platform specific information.\r | |
| 17 | \r | |
| 18 | **/\r | |
| 19 | \r | |
| 20 | #ifndef _PLATFORM_H\r | |
| 21 | #define _PLATFORM_H\r | |
| 22 | \r | |
| 23 | #include "ChipsetAccess.h"\r | |
| 24 | #include "PlatformBaseAddresses.h"\r | |
| 25 | \r | |
| 26 | \r | |
| 27 | //\r | |
| 28 | // Number of P & T states supported.\r | |
| 29 | //\r | |
| 30 | #define NPTM_P_STATES_SUPPORTED 16\r | |
| 31 | #define NPTM_T_STATES_SUPPORTED 8\r | |
| 32 | \r | |
| 33 | //\r | |
| 34 | // I/O APIC IDs, the code uses math to generate the numbers\r | |
| 35 | // instead of using these defines.\r | |
| 36 | //\r | |
| 37 | #define ICH_IOAPIC (1 << 0)\r | |
| 38 | #define ICH_IOAPIC_ID 0x08\r | |
| 39 | \r | |
| 40 | //\r | |
| 41 | // Possible SMBus addresses that will be present.\r | |
| 42 | //\r | |
| 43 | #define SMBUS_ADDR_CH_A_1 0xA0\r | |
| 44 | #define SMBUS_ADDR_CH_A_2 0xA2\r | |
| 45 | #define SMBUS_ADDR_CH_B_1 0xA4\r | |
| 46 | #define SMBUS_ADDR_CH_B_2 0xA6\r | |
| 47 | #define SMBUS_ADDR_CH_C_1 0xA8\r | |
| 48 | #define SMBUS_ADDR_CH_C_2 0xAA\r | |
| 49 | #define SMBUS_ADDR_CH_D_1 0xAC\r | |
| 50 | #define SMBUS_ADDR_CH_D_2 0xAE\r | |
| 51 | #define SMBUS_ADDR_HOST_CLK_BUFFER 0xDC\r | |
| 52 | #define SMBUS_ADDR_ICH_SLAVE 0x44\r | |
| 53 | #define SMBUS_ADDR_HECETA 0x5C\r | |
| 54 | #define SMBUS_ADDR_SMBARP 0xC2\r | |
| 55 | #define SMBUS_ADDR_82573E 0xC6\r | |
| 56 | #define SMBUS_ADDR_CLKCHIP 0xD2\r | |
| 57 | #define SMBUS_ADDR_BRD_REV 0x4E\r | |
| 58 | #define SMBUS_ADDR_DB803 0x82\r | |
| 59 | \r | |
| 60 | //\r | |
| 61 | // SMBus addresses that used on this platform.\r | |
| 62 | //\r | |
| 63 | #define PLATFORM_SMBUS_RSVD_ADDRESSES { \\r | |
| 64 | SMBUS_ADDR_CH_A_1, \\r | |
| 65 | SMBUS_ADDR_CH_A_2, \\r | |
| 66 | SMBUS_ADDR_HOST_CLK_BUFFER, \\r | |
| 67 | SMBUS_ADDR_ICH_SLAVE, \\r | |
| 68 | SMBUS_ADDR_SMBARP, \\r | |
| 69 | SMBUS_ADDR_CLKCHIP, \\r | |
| 70 | SMBUS_ADDR_BRD_REV, \\r | |
| 71 | SMBUS_ADDR_DB803 \\r | |
| 72 | }\r | |
| 73 | \r | |
| 74 | //\r | |
| 75 | // Count of addresses present in PLATFORM_SMBUS_RSVD_ADDRESSES.\r | |
| 76 | //\r | |
| 77 | #define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 8\r | |
| 78 | \r | |
| 79 | //\r | |
| 80 | // CMOS usage\r | |
| 81 | //\r | |
| 82 | #define CMOS_CPU_BSP_SELECT 0x10\r | |
| 83 | #define CMOS_CPU_UP_MODE 0x11\r | |
| 84 | #define CMOS_CPU_RATIO_OFFSET 0x12\r | |
| 85 | #define CMOS_CPU_CORE_HT_OFFSET 0x13\r | |
| 86 | #define CMOS_EFI_DEBUG 0x14\r | |
| 87 | #define CMOS_CPU_BIST_OFFSET 0x15\r | |
| 88 | #define CMOS_CPU_VMX_OFFSET 0x16\r | |
| 89 | #define CMOS_ICH_PORT80_OFFSET 0x17\r | |
| 90 | #define CMOS_PLATFORM_DESIGNATOR 0x18 // Second bank CMOS location of Platform ID.\r | |
| 91 | #define CMOS_VALIDATION_TEST_BYTE 0x19 // BIT0 - Validation mailbox for UPonDP.\r | |
| 92 | #define CMOS_SERIAL_BAUD_RATE 0x1A // 0=115200; 1=57600; 2=38400; 3=19200; 4=9600\r | |
| 93 | #define CMOS_DCU_MODE_OFFSET 0x1B\r | |
| 94 | #define CMOS_VR11_SET_OFFSET 0x1C\r | |
| 95 | #define CMOS_SBSP_TO_AP_COMM 0x20 // SEC code use ONLY!!!\r | |
| 96 | #define CMOS_RESET_TYPE_BY_OS 0x52\r | |
| 97 | #define TCG_CMOS_MOR_AREA_OFFSET 0x65 // Also Change in Universal\Security\Tpm\PhysicalPresence\Dxe\PhysicalPresence.c &\r | |
| 98 | #define CMOS_S4_WAKEUP_FLAG_ADDRESS 0x6E\r | |
| 99 | #define ACPI_TPM_REQUEST 0x75\r | |
| 100 | #define ACPI_TPM_LAST_REQUEST 0x76\r | |
| 101 | #define CMOS_BOOT_FLAG_ADDRESS 0x7E\r | |
| 102 | \r | |
| 103 | //\r | |
| 104 | // GPIO Index Data Structure.\r | |
| 105 | //\r | |
| 106 | typedef struct {\r | |
| 107 | UINT8 Register;\r | |
| 108 | UINT32 Value;\r | |
| 109 | } ICH_GPIO_DEV;\r | |
| 110 | \r | |
| 111 | //\r | |
| 112 | // CPU Equates\r | |
| 113 | //\r | |
| 114 | #define MAX_THREAD 2\r | |
| 115 | #define MAX_CORE 1\r | |
| 116 | #define MAX_DIE 2\r | |
| 117 | #define MAX_CPU_SOCKET 1\r | |
| 118 | #define MAX_CPU_NUM (MAX_THREAD * MAX_CORE * MAX_DIE * MAX_CPU_SOCKET)\r | |
| 119 | \r | |
| 120 | #define MEM64_LEN 0x00100000000\r | |
| 121 | #define RES_MEM64_36_BASE 0x01000000000 - MEM64_LEN // 2^36\r | |
| 122 | #define RES_MEM64_36_LIMIT 0x01000000000 - 1 // 2^36\r | |
| 123 | #define RES_MEM64_39_BASE 0x08000000000 - MEM64_LEN // 2^39\r | |
| 124 | #define RES_MEM64_39_LIMIT 0x08000000000 - 1 // 2^39\r | |
| 125 | #define RES_MEM64_40_BASE 0x10000000000 - MEM64_LEN // 2^40\r | |
| 126 | #define RES_MEM64_40_LIMIT 0x10000000000 - 1 // 2^40\r | |
| 127 | \r | |
| 128 | #define PLATFORM_MAX_BUS_NUM 0x3f\r | |
| 129 | #define V_DEFAULT_SUBSYSTEM_DEVICE_ID 0x574d\r | |
| 130 | #define V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT 0x544b\r | |
| 131 | #define V_DEFAULT_SUBSYSTEM_VENDOR_ID 0x8086\r | |
| 132 | \r | |
| 133 | #endif\r |