[mirror_edk2.git] / Vlv2TbltDevicePkg / Library / EfiRegTableLib / EfiRegTableLib.c

/*++\r
\r
Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
                                                                                   \r\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
                                                                                   \r\r
\r
\r
Module Name:\r
\r
  EfiRegTableLib.c\r
\r
Abstract:\r
\r
  Lib function for table driven register initialization.\r
\r
Revision History\r
\r
--*/\r
\r
#include <Library/EfiRegTableLib.h>\r
#include <Library/S3BootScriptLib.h>\r
\r
//\r
// Local Functions\r
//\r
\r
/**\r
  Local worker function to process PCI_WRITE table entries.  Performs write and\r
  may also call BootScriptSave protocol if indicated in the Entry flags\r
\r
  @param Entry            A pointer to the PCI_WRITE entry to process\r
\r
  @param PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used\r
                          when processing the entry.\r
\r
  @retval Nothing.\r
\r
**/\r
STATIC\r
VOID\r
PciWrite (\r
  EFI_REG_TABLE_PCI_WRITE             *Entry,\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *PciRootBridgeIo\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  Status = PciRootBridgeIo->Pci.Write (\r
                                  PciRootBridgeIo,\r
                                  (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
                                  (UINT64) Entry->PciAddress,\r
                                  1,\r
                                  &Entry->Data\r
                                  );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {\r
    Status = S3BootScriptSavePciCfgWrite (\r
              (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
              (UINT64) Entry->PciAddress,\r
              1,\r
              &Entry->Data\r
              );\r
    ASSERT_EFI_ERROR (Status);\r
  }\r
}\r
\r
/**\r
  Local worker function to process PCI_READ_MODIFY_WRITE table entries.\r
  Performs RMW write and may also call BootScriptSave protocol if indicated in\r
  the Entry flags.\r
\r
  @param Entry            A pointer to the PCI_READ_MODIFY_WRITE entry to process.\r
\r
  @param PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used\r
                          when processing the entry.\r
\r
  @retval Nothing.\r
\r
**/\r
STATIC\r
VOID\r
PciReadModifyWrite (\r
  EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *Entry,\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *PciRootBridgeIo\r
  )\r
{\r
  EFI_STATUS  Status;\r
  UINT32      TempData;\r
\r
  Status = PciRootBridgeIo->Pci.Read (\r
                                  PciRootBridgeIo,\r
                                  (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
                                  (UINT64) Entry->PciAddress,\r
                                  1,\r
                                  &TempData\r
                                  );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  Entry->OrMask &= Entry->AndMask;\r
  TempData &= ~Entry->AndMask;\r
  TempData |= Entry->OrMask;\r
\r
  Status = PciRootBridgeIo->Pci.Write (\r
                                  PciRootBridgeIo,\r
                                  (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
                                  (UINT64) Entry->PciAddress,\r
                                  1,\r
                                  &TempData\r
                                  );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {\r
    Status = S3BootScriptSavePciCfgReadWrite (\r
              (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
              (UINT64) Entry->PciAddress,\r
              &Entry->OrMask,\r
              &Entry->AndMask\r
              );\r
    ASSERT_EFI_ERROR (Status);\r
  }\r
}\r
\r
/**\r
  Local worker function to process MEM_READ_MODIFY_WRITE table entries.\r
  Performs RMW write and may also call BootScriptSave protocol if indicated in\r
  the Entry flags.\r
\r
  @param Entry            A pointer to the MEM_READ_MODIFY_WRITE entry to process.\r
\r
  @param PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used\r
                          when processing the entry.\r
\r
  @retval Nothing.\r
\r
**/\r
STATIC\r
VOID\r
MemReadModifyWrite (\r
  EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *Entry,\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *PciRootBridgeIo\r
  )\r
{\r
  EFI_STATUS  Status;\r
  UINT32      TempData;\r
\r
  Status = PciRootBridgeIo->Mem.Read (\r
                                  PciRootBridgeIo,\r
                                  (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
                                  (UINT64) Entry->MemAddress,\r
                                  1,\r
                                  &TempData\r
                                  );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  Entry->OrMask &= Entry->AndMask;\r
  TempData &= ~Entry->AndMask;\r
  TempData |= Entry->OrMask;\r
\r
  Status = PciRootBridgeIo->Mem.Write (\r
                                  PciRootBridgeIo,\r
                                  (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
                                  (UINT64) Entry->MemAddress,\r
                                  1,\r
                                  &TempData\r
                                  );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {\r
    Status = S3BootScriptSaveMemReadWrite (\r
              (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
              Entry->MemAddress,\r
              &Entry->OrMask,\r
              &Entry->AndMask\r
              );\r
    ASSERT_EFI_ERROR (Status);\r
  }\r
}\r
\r
//\r
// Exported functions\r
//\r
\r
/**\r
  Processes register table assuming which may contain PCI, IO, MEM, and STALL\r
  entries.\r
\r
  No parameter checking is done so the caller must be careful about omitting\r
  values for PciRootBridgeIo or CpuIo parameters.  If the regtable does\r
  not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply\r
  NULL).  If the regtable does not contain any IO or Mem entries, it is safe to\r
  omit the CpuIo (supply NULL).\r
\r
  The RegTableEntry parameter is not checked, but is required.\r
\r
  gBS is assumed to have been defined and is used when processing stalls.\r
\r
  The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
  entry is encountered.\r
\r
  @param RegTableEntry    A pointer to the register table to process\r
\r
  @param PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used\r
                          when processing PCI table entries\r
\r
  @param CpuIo            A pointer to the instance of CpuIo that is used when processing IO and\r
                          MEM table entries\r
\r
  @retval Nothing.\r
\r
**/\r
VOID\r
ProcessRegTablePci (\r
  EFI_REG_TABLE                       *RegTableEntry,\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *PciRootBridgeIo,\r
  EFI_CPU_IO_PROTOCOL                 *CpuIo\r
  )\r
{\r
  while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {\r
    switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {\r
    case OP_PCI_WRITE:\r
      PciWrite ((EFI_REG_TABLE_PCI_WRITE *) RegTableEntry, PciRootBridgeIo);\r
      break;\r
\r
    case OP_PCI_READ_MODIFY_WRITE:\r
      PciReadModifyWrite ((EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);\r
      break;\r
\r
    case OP_MEM_READ_MODIFY_WRITE:\r
      MemReadModifyWrite ((EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);\r
      break;\r
\r
    default:\r
      DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));\r
      ASSERT (0);\r
      break;\r
    }\r
\r
    RegTableEntry++;\r
  }\r
}\r
\r
/**\r
  Processes register table assuming which may contain IO, MEM, and STALL\r
  entries, but must NOT contain any PCI entries.  Any PCI entries cause an\r
  ASSERT in a DEBUG build and are skipped in a free build.\r
\r
  No parameter checking is done.  Both RegTableEntry and CpuIo parameters are\r
  required.\r
\r
  gBS is assumed to have been defined and is used when processing stalls.\r
\r
  The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
  entry is encountered.\r
\r
  @param  RegTableEntry   A pointer to the register table to process\r
\r
  @param  CpuIo           A pointer to the instance of CpuIo that is used when processing IO and\r
                          MEM table entries\r
\r
  @retval Nothing.\r
\r
**/\r
VOID\r
ProcessRegTableCpu (\r
  EFI_REG_TABLE                       *RegTableEntry,\r
  EFI_CPU_IO_PROTOCOL                 *CpuIo\r
  )\r
{\r
  while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {\r
    switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {\r
    default:\r
      DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));\r
      ASSERT (0);\r
      break;\r
    }\r
\r
    RegTableEntry++;\r
  }\r
}\r
Commit	Line	Data
3cbfba02 DW	1	/*++\r
	2	\r
	3	Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
	4	\r\r
9dc8036d MK	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
9dc8036d MK	6	\r
3cbfba02 DW	7	\r\r
	8	\r
	9	\r
	10	Module Name:\r
	11	\r
	12	EfiRegTableLib.c\r
	13	\r
	14	Abstract:\r
	15	\r
	16	Lib function for table driven register initialization.\r
	17	\r
	18	Revision History\r
	19	\r
	20	--*/\r
	21	\r
	22	#include <Library/EfiRegTableLib.h>\r
	23	#include <Library/S3BootScriptLib.h>\r
	24	\r
	25	//\r
	26	// Local Functions\r
	27	//\r
	28	\r
	29	/**\r
	30	Local worker function to process PCI_WRITE table entries. Performs write and\r
	31	may also call BootScriptSave protocol if indicated in the Entry flags\r
	32	\r
	33	@param Entry A pointer to the PCI_WRITE entry to process\r
	34	\r
	35	@param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used\r
	36	when processing the entry.\r
	37	\r
	38	@retval Nothing.\r
	39	\r
	40	**/\r
	41	STATIC\r
	42	VOID\r
	43	PciWrite (\r
	44	EFI_REG_TABLE_PCI_WRITE *Entry,\r
	45	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo\r
	46	)\r
	47	{\r
	48	EFI_STATUS Status;\r
	49	\r
	50	Status = PciRootBridgeIo->Pci.Write (\r
	51	PciRootBridgeIo,\r
	52	(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
	53	(UINT64) Entry->PciAddress,\r
	54	1,\r
	55	&Entry->Data\r
	56	);\r
	57	ASSERT_EFI_ERROR (Status);\r
	58	\r
	59	if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {\r
	60	Status = S3BootScriptSavePciCfgWrite (\r
	61	(EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
	62	(UINT64) Entry->PciAddress,\r
	63	1,\r
	64	&Entry->Data\r
	65	);\r
	66	ASSERT_EFI_ERROR (Status);\r
	67	}\r
	68	}\r
	69	\r
	70	/**\r
71	Local worker function to process PCI_READ_MODIFY_WRITE table entries.\r
72	Performs RMW write and may also call BootScriptSave protocol if indicated in\r
73	the Entry flags.\r
74	\r
75	@param Entry A pointer to the PCI_READ_MODIFY_WRITE entry to process.\r
76	\r
77	@param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used\r
78	when processing the entry.\r
79	\r
80	@retval Nothing.\r
81	\r
82	**/\r
83	STATIC\r
84	VOID\r
85	PciReadModifyWrite (\r
86	EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *Entry,\r
87	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo\r
88	)\r
89	{\r
90	EFI_STATUS Status;\r
91	UINT32 TempData;\r
92	\r
93	Status = PciRootBridgeIo->Pci.Read (\r
94	PciRootBridgeIo,\r
95	(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
96	(UINT64) Entry->PciAddress,\r
97	1,\r
98	&TempData\r
99	);\r
100	ASSERT_EFI_ERROR (Status);\r
101	\r
102	Entry->OrMask &= Entry->AndMask;\r
103	TempData &= ~Entry->AndMask;\r
104	TempData \|= Entry->OrMask;\r
105	\r
106	Status = PciRootBridgeIo->Pci.Write (\r
107	PciRootBridgeIo,\r
108	(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
109	(UINT64) Entry->PciAddress,\r
110	1,\r
111	&TempData\r
112	);\r
113	ASSERT_EFI_ERROR (Status);\r
114	\r
115	if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {\r
116	Status = S3BootScriptSavePciCfgReadWrite (\r
117	(EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
118	(UINT64) Entry->PciAddress,\r
119	&Entry->OrMask,\r
120	&Entry->AndMask\r
121	);\r
122	ASSERT_EFI_ERROR (Status);\r
123	}\r
124	}\r
125	\r
126	/**\r
127	Local worker function to process MEM_READ_MODIFY_WRITE table entries.\r
128	Performs RMW write and may also call BootScriptSave protocol if indicated in\r
129	the Entry flags.\r
130	\r
131	@param Entry A pointer to the MEM_READ_MODIFY_WRITE entry to process.\r
132	\r
133	@param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used\r
134	when processing the entry.\r
135	\r
136	@retval Nothing.\r
137	\r
138	**/\r
139	STATIC\r
140	VOID\r
141	MemReadModifyWrite (\r
142	EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *Entry,\r
143	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo\r
144	)\r
145	{\r
146	EFI_STATUS Status;\r
147	UINT32 TempData;\r
148	\r
149	Status = PciRootBridgeIo->Mem.Read (\r
150	PciRootBridgeIo,\r
151	(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
152	(UINT64) Entry->MemAddress,\r
153	1,\r
154	&TempData\r
155	);\r
156	ASSERT_EFI_ERROR (Status);\r
157	\r
158	Entry->OrMask &= Entry->AndMask;\r
159	TempData &= ~Entry->AndMask;\r
160	TempData \|= Entry->OrMask;\r
161	\r
162	Status = PciRootBridgeIo->Mem.Write (\r
163	PciRootBridgeIo,\r
164	(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
165	(UINT64) Entry->MemAddress,\r
166	1,\r
167	&TempData\r
168	);\r
169	ASSERT_EFI_ERROR (Status);\r
170	\r
171	if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {\r
172	Status = S3BootScriptSaveMemReadWrite (\r
173	(EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
174	Entry->MemAddress,\r
175	&Entry->OrMask,\r
176	&Entry->AndMask\r
177	);\r
178	ASSERT_EFI_ERROR (Status);\r
179	}\r
180	}\r
181	\r
182	//\r
183	// Exported functions\r
184	//\r
185	\r
186	/**\r
187	Processes register table assuming which may contain PCI, IO, MEM, and STALL\r
188	entries.\r
189	\r
190	No parameter checking is done so the caller must be careful about omitting\r
191	values for PciRootBridgeIo or CpuIo parameters. If the regtable does\r
192	not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply\r
193	NULL). If the regtable does not contain any IO or Mem entries, it is safe to\r
194	omit the CpuIo (supply NULL).\r
195	\r
196	The RegTableEntry parameter is not checked, but is required.\r
197	\r
198	gBS is assumed to have been defined and is used when processing stalls.\r
199	\r
200	The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
201	entry is encountered.\r
202	\r
203	@param RegTableEntry A pointer to the register table to process\r
204	\r
205	@param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used\r
206	when processing PCI table entries\r
207	\r
208	@param CpuIo A pointer to the instance of CpuIo that is used when processing IO and\r
209	MEM table entries\r
210	\r
211	@retval Nothing.\r
212	\r
213	**/\r
214	VOID\r
215	ProcessRegTablePci (\r
216	EFI_REG_TABLE *RegTableEntry,\r
217	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
218	EFI_CPU_IO_PROTOCOL *CpuIo\r
219	)\r
220	{\r
221	while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {\r
222	switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {\r
223	case OP_PCI_WRITE:\r
224	PciWrite ((EFI_REG_TABLE_PCI_WRITE *) RegTableEntry, PciRootBridgeIo);\r
225	break;\r
226	\r
227	case OP_PCI_READ_MODIFY_WRITE:\r
228	PciReadModifyWrite ((EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);\r
229	break;\r
230	\r
231	case OP_MEM_READ_MODIFY_WRITE:\r
232	MemReadModifyWrite ((EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);\r
233	break;\r
234	\r
235	default:\r
236	DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));\r
237	ASSERT (0);\r
238	break;\r
239	}\r
240	\r
241	RegTableEntry++;\r
242	}\r
243	}\r
244	\r
245	/**\r
246	Processes register table assuming which may contain IO, MEM, and STALL\r
247	entries, but must NOT contain any PCI entries. Any PCI entries cause an\r
248	ASSERT in a DEBUG build and are skipped in a free build.\r
249	\r
250	No parameter checking is done. Both RegTableEntry and CpuIo parameters are\r
251	required.\r
252	\r
253	gBS is assumed to have been defined and is used when processing stalls.\r
254	\r
255	The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
256	entry is encountered.\r
257	\r
258	@param RegTableEntry A pointer to the register table to process\r
259	\r
260	@param CpuIo A pointer to the instance of CpuIo that is used when processing IO and\r
261	MEM table entries\r
262	\r
263	@retval Nothing.\r
264	\r
265	**/\r
266	VOID\r
267	ProcessRegTableCpu (\r
268	EFI_REG_TABLE *RegTableEntry,\r
269	EFI_CPU_IO_PROTOCOL *CpuIo\r
270	)\r
271	{\r
272	while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {\r
273	switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {\r
274	default:\r
275	DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));\r
276	ASSERT (0);\r
277	break;\r
278	}\r
279	\r
280	RegTableEntry++;\r
281	}\r
282	}\r