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[mirror_edk2.git] / Vlv2TbltDevicePkg / Library / FlashDeviceLib / SpiChipDefinitions.h
CommitLineData
7a0a32f1
JY		 1/** @file\r
2\r
3 Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>\r
4\r
9dc8036d 5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
3cbfba02 6\r
3cbfba02
DW		 7\r
8\r
9**/\r
10\r
11#include <Library/SpiFlash.H>\r
12\r
7a0a32f1 13#define FLASH_SIZE 0x400000\r
27f44846 14#define FLASH_DEVICE_BASE_ADDRESS (0xFFFFFFFF-FLASH_SIZE+1)\r
3cbfba02
DW		 15\r
16//\r
17// Serial Flash device initialization data table provided to the\r
18// Intel(R) SPI Host Controller Compatibility Interface.\r
19//\r
20SPI_INIT_TABLE mInitTable[] = {\r
21 {\r
22 SF_VENDOR_ID_WINBOND, // VendorId\r
23 SF_DEVICE_ID0_W25QXX, // DeviceId 0\r
24 SF_DEVICE_ID1_W25Q64, // DeviceId 1\r
25 {\r
26 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
27 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
28 },\r
29 {\r
30 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
31 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
32 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
33 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
34 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
35 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
36 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
37 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
38 },\r
39\r
40 //\r
41 // The offset of the start of the BIOS image in flash. This value is platform specific\r
42 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
43 //\r
44 ((WINBOND_W25Q64_SIZE >= FLASH_SIZE) ? WINBOND_W25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
45\r
46 //\r
47 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
48 //\r
49 FLASH_SIZE\r
50 },\r
51 {\r
52 SF_VENDOR_ID_ATMEL, // VendorId\r
53 SF_DEVICE_ID0_AT25DF321A, // DeviceId 0\r
54 SF_DEVICE_ID1_AT25DF321A, // DeviceId 1\r
55 {\r
56 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
57 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
58 },\r
59 {\r
60 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
61 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
62 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
63 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
64 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
65 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)\r
66 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
67 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
68 },\r
69\r
70 //\r
71 // The offset of the start of the BIOS image in flash. This value is platform specific\r
72 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
73 //\r
74 ((ATMEL_AT25DF321A_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF321A_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
75\r
76 //\r
77 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
78 //\r
79 FLASH_SIZE\r
80 },\r
81 {\r
82 SF_VENDOR_ID_ATMEL, // VendorId\r
83 SF_DEVICE_ID0_AT26DF321, // DeviceId 0\r
84 SF_DEVICE_ID1_AT26DF321, // DeviceId 1\r
85 {\r
86 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
87 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
88 },\r
89 {\r
90 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
91 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
92 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
93 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
94 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
95 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)\r
96 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
97 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
98 },\r
99\r
100 //\r
101 // The offset of the start of the BIOS image in flash. This value is platform specific\r
102 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
103 //\r
104 ((ATMEL_AT26DF321_SIZE >= FLASH_SIZE) ? ATMEL_AT26DF321_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
105\r
106 //\r
107 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
108 //\r
109 FLASH_SIZE\r
110 },\r
111 {\r
112 SF_VENDOR_ID_ATMEL, // VendorId\r
113 SF_DEVICE_ID0_AT25DF641, // DeviceId 0\r
114 SF_DEVICE_ID1_AT25DF641, // DeviceId 1\r
115 {\r
116 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
117 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
118 },\r
119 {\r
120 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
121 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
122 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
123 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
124 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
125 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)\r
126 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
127 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
128 },\r
129\r
130 //\r
131 // The offset of the start of the BIOS image in flash. This value is platform specific\r
132 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
133 //\r
134 ((ATMEL_AT25DF641_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF641_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
135\r
136 //\r
137 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
138 //\r
139 FLASH_SIZE\r
140 },\r
141 {\r
142 SF_VENDOR_ID_WINBOND, // VendorId\r
143 SF_DEVICE_ID0_W25QXX, // DeviceId 0\r
144 SF_DEVICE_ID1_W25Q16, // DeviceId 1\r
145 {\r
146 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
147 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
148 },\r
149 {\r
150 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
151 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
152 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
153 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
154 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
155 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
156 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
157 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
158 },\r
159\r
160 //\r
161 // The offset of the start of the BIOS image in flash. This value is platform specific\r
162 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
163 //\r
164 ((WINBOND_W25Q16_SIZE >= FLASH_SIZE) ? WINBOND_W25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
165\r
166 //\r
167 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
168 //\r
169 FLASH_SIZE\r
170 },\r
171 {\r
172 SF_VENDOR_ID_WINBOND, // VendorId\r
173 SF_DEVICE_ID0_W25QXX, // DeviceId 0\r
174 SF_DEVICE_ID1_W25Q32, // DeviceId 1\r
175 {\r
176 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
177 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register.\r
178 },\r
179 {\r
180 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
181 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
182 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
183 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
184 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
185 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
186 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
187 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
188 },\r
189\r
190 //\r
191 // The offset of the start of the BIOS image in flash. This value is platform specific\r
192 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
193 //\r
194 ((WINBOND_W25Q32_SIZE >= FLASH_SIZE) ? WINBOND_W25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
195\r
196 //\r
197 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
198 //\r
199 FLASH_SIZE\r
200 },\r
201 {\r
202 SF_VENDOR_ID_WINBOND, // VendorId\r
203 SF_DEVICE_ID0_W25XXX, // DeviceId 0\r
204 SF_DEVICE_ID1_W25X32, // DeviceId 1\r
205 {\r
206 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
207 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
208 },\r
209 {\r
210 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
211 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
212 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
213 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
214 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
215 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
216 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
217 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
218 },\r
219\r
220 //\r
221 // The offset of the start of the BIOS image in flash. This value is platform specific\r
222 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
223 //\r
224 ((WINBOND_W25X32_SIZE >= FLASH_SIZE) ? WINBOND_W25X32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
225\r
226 //\r
227 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
228 //\r
229 FLASH_SIZE\r
230 },\r
231 {\r
232 SF_VENDOR_ID_WINBOND, // VendorId\r
233 SF_DEVICE_ID0_W25XXX, // DeviceId 0\r
234 SF_DEVICE_ID1_W25X64, // DeviceId 1\r
235 {\r
236 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
237 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
238 },\r
239 {\r
240 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
241 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
242 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
243 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
244 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
245 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
246 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
247 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
248 },\r
249\r
250 //\r
251 // The offset of the start of the BIOS image in flash. This value is platform specific\r
252 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
253 //\r
254 ((WINBOND_W25X64_SIZE >= FLASH_SIZE) ? WINBOND_W25X64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
255\r
256 //\r
257 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
258 //\r
259 FLASH_SIZE\r
260 },\r
261 {\r
262 SF_VENDOR_ID_WINBOND, // VendorId\r
263 SF_DEVICE_ID0_W25QXX, // DeviceId 0\r
264 SF_DEVICE_ID1_W25Q128, // DeviceId 1\r
265 {\r
266 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
267 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
268 },\r
269 {\r
270 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
271 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
272 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
273 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
274 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
275 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
276 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
277 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
278 },\r
279\r
280 //\r
281 // The offset of the start of the BIOS image in flash. This value is platform specific\r
282 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
283 //\r
284 ((WINBOND_W25Q128_SIZE >= FLASH_SIZE) ? WINBOND_W25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
285\r
286 //\r
287 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
288 //\r
289 FLASH_SIZE\r
290 },\r
291 {\r
292 SF_VENDOR_ID_MACRONIX, // VendorId\r
293 SF_DEVICE_ID0_MX25LXX, // DeviceId 0\r
294 SF_DEVICE_ID1_MX25L16, // DeviceId 1\r
295 {\r
296 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
297 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
298 },\r
299 {\r
300 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
301 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
302 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
303 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
304 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
305 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
306 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
307 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
308 },\r
309\r
310 //\r
311 // The offset of the start of the BIOS image in flash. This value is platform specific\r
312 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
313 //\r
314 ((MACRONIX_MX25L16_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
315\r
316 //\r
317 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
318 //\r
319 FLASH_SIZE\r
320 },\r
321 {\r
322 SF_VENDOR_ID_MACRONIX, // VendorId\r
323 SF_DEVICE_ID0_MX25LXX, // DeviceId 0\r
324 SF_DEVICE_ID1_MX25L32, // DeviceId 1\r
325 {\r
326 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
327 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
328 },\r
329 {\r
330 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
331 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
332 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
333 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
334 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
335 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
336 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
337 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
338 },\r
339\r
340 //\r
341 // The offset of the start of the BIOS image in flash. This value is platform specific\r
342 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
343 //\r
344 ((MACRONIX_MX25L32_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
345\r
346 //\r
347 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
348 //\r
349 FLASH_SIZE\r
350 },\r
351 {\r
352 SF_VENDOR_ID_MACRONIX, // VendorId\r
353 SF_DEVICE_ID0_MX25LXX, // DeviceId 0\r
354 SF_DEVICE_ID1_MX25L64, // DeviceId 1\r
355 {\r
356 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
357 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
358 },\r
359 {\r
360 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
361 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
362 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
363 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
364 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
365 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
366 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
367 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
368 },\r
369\r
370 //\r
371 // The offset of the start of the BIOS image in flash. This value is platform specific\r
372 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
373 //\r
374 ((MACRONIX_MX25L64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
375\r
376 //\r
377 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
378 //\r
379 FLASH_SIZE\r
380 },\r
381 {\r
382 SF_VENDOR_ID_MACRONIX, // VendorId\r
383 SF_DEVICE_ID0_MX25LXX, // DeviceId 0\r
384 SF_DEVICE_ID1_MX25L128, // DeviceId 1\r
385 {\r
386 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
387 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
388 },\r
389 {\r
390 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
391 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
392 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
393 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
394 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
395 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
396 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
397 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
398 },\r
399\r
400 //\r
401 // The offset of the start of the BIOS image in flash. This value is platform specific\r
402 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
403 //\r
404 ((MACRONIX_MX25L128_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L128_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
405\r
406 //\r
407 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
408 //\r
409 FLASH_SIZE\r
410 },\r
411 {\r
412 SF_VENDOR_ID_MACRONIX, // VendorId\r
413 SF_DEVICE_ID0_MX25UXX, // DeviceId 0\r
414 SF_DEVICE_ID1_MX25U6435F, // DeviceId 1\r
415 {\r
416 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
417 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
418 },\r
419 {\r
420 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
421 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
422 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
423 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
424 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
425 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
426 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
427 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
428 },\r
429\r
430 //\r
431 // The offset of the start of the BIOS image in flash. This value is platform specific\r
432 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
433 //\r
434 ((MACRONIX_MX25U64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25U64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
435\r
436 //\r
437 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
438 //\r
439 FLASH_SIZE\r
440 },\r
441 {\r
442 SF_VENDOR_ID_SST, // VendorId\r
443 SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0\r
444 SF_DEVICE_ID1_SST25VF016B,// DeviceId 1\r
445 {\r
446 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
447 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
448 },\r
449 {\r
450 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
451 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
452 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
453 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
454 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
455 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)\r
456 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
457 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
458 },\r
459\r
460 //\r
461 // The offset of the start of the BIOS image in flash. This value is platform specific\r
462 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
463 //\r
464 ((SST_SST25VF016B_SIZE >= FLASH_SIZE) ? SST_SST25VF016B_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
465\r
466 //\r
467 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
468 //\r
469 FLASH_SIZE\r
470 },\r
471 {\r
472 SF_VENDOR_ID_SST, // VendorId\r
473 SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0\r
474 SF_DEVICE_ID1_SST25VF064C,// DeviceId 1\r
475 {\r
476 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
477 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
478 },\r
479 {\r
480 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
481 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
482 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
483 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
484 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
485 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)\r
486 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
487 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
488 },\r
489\r
490 //\r
491 // The offset of the start of the BIOS image in flash. This value is platform specific\r
492 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
493 //\r
494 ((SST_SST25VF064C_SIZE >= FLASH_SIZE) ? SST_SST25VF064C_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
495\r
496 //\r
497 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
498 //\r
499 FLASH_SIZE\r
500 },\r
501 {\r
502 //\r
503 // Minnow2 SPI type\r
504 //\r
505 SF_VENDOR_ID_NUMONYX, // VendorId\r
506 SF_DEVICE_ID0_N25Q064, // DeviceId 0\r
507 SF_DEVICE_ID1_N25Q064, // DeviceId 1\r
508 {\r
509 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
510 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
511 },\r
512 {\r
513 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle20MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
514 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
515 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle20MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
516 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle20MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
517 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle20MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
518 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle20MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
519 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle20MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
520 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle20MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
521 },\r
522\r
523 //\r
524 // The offset of the start of the BIOS image in flash. This value is platform specific\r
525 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
526 //\r
527 ((NUMONYX_N25Q064_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q064_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
528\r
529 //\r
530 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
531 //\r
532 FLASH_SIZE\r
533 },\r
534 {\r
535 SF_VENDOR_ID_NUMONYX, // VendorId\r
536 SF_DEVICE_ID0_M25PXXX, // DeviceId 0\r
537 SF_DEVICE_ID1_M25PX16, // DeviceId 1\r
538 {\r
539 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
540 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
541 },\r
542 {\r
543 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
544 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
545 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
546 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
547 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
548 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
549 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
550 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
551 },\r
552\r
553 //\r
554 // The offset of the start of the BIOS image in flash. This value is platform specific\r
555 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
556 //\r
557 ((NUMONYX_M25PX16_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
558\r
559 //\r
560 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
561 //\r
562 FLASH_SIZE\r
563 },\r
564 {\r
565 SF_VENDOR_ID_NUMONYX, // VendorId\r
566 SF_DEVICE_ID0_N25QXXX, // DeviceId 0\r
567 SF_DEVICE_ID1_N25Q032, // DeviceId 1\r
568 {\r
569 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
570 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
571 },\r
572 {\r
573 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
574 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
575 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
576 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
577 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
578 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
579 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
580 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
581 },\r
582\r
583 //\r
584 // The offset of the start of the BIOS image in flash. This value is platform specific\r
585 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
586 //\r
587 ((NUMONYX_N25Q032_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q032_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
588\r
589 //\r
590 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
591 //\r
592 FLASH_SIZE\r
593 },\r
594 {\r
595 SF_VENDOR_ID_NUMONYX, // VendorId\r
596 SF_DEVICE_ID0_M25PXXX, // DeviceId 0\r
597 SF_DEVICE_ID1_M25PX32, // DeviceId 1\r
598 {\r
599 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
600 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
601 },\r
602 {\r
603 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
604 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
605 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
606 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
607 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
608 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
609 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
610 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
611 },\r
612\r
613 //\r
614 // The offset of the start of the BIOS image in flash. This value is platform specific\r
615 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
616 //\r
617 ((NUMONYX_M25PX32_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
618\r
619 //\r
620 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
621 //\r
622 FLASH_SIZE\r
623 },\r
624 {\r
625 SF_VENDOR_ID_NUMONYX, // VendorId\r
626 SF_DEVICE_ID0_M25PXXX, // DeviceId 0\r
627 SF_DEVICE_ID1_M25PX64, // DeviceId 1\r
628 {\r
629 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
630 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
631 },\r
632 {\r
633 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
634 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
635 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
636 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
637 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
638 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
639 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
640 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
641 },\r
642\r
643 //\r
644 // The offset of the start of the BIOS image in flash. This value is platform specific\r
645 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
646 //\r
647 ((NUMONYX_M25PX64_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
648\r
649 //\r
650 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
651 //\r
652 FLASH_SIZE\r
653 },\r
654 {\r
655 SF_VENDOR_ID_NUMONYX, // VendorId\r
656 SF_DEVICE_ID0_N25QXXX, // DeviceId 0\r
657 SF_DEVICE_ID1_N25Q128, // DeviceId 1\r
658 {\r
659 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
660 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
661 },\r
662 {\r
663 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
664 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
665 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
666 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
667 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
668 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
669 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
670 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
671 },\r
672\r
673 //\r
674 // The offset of the start of the BIOS image in flash. This value is platform specific\r
675 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
676 //\r
677 ((NUMONYX_N25Q128_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
678\r
679 //\r
680 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
681 //\r
682 FLASH_SIZE\r
683 },\r
684 {\r
685 SF_VENDOR_ID_EON, // VendorId\r
686 SF_DEVICE_ID0_EN25QXX, // DeviceId 0\r
687 SF_DEVICE_ID1_EN25Q16, // DeviceId 1\r
688 {\r
689 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
690 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
691 },\r
692 {\r
693 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
694 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
695 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
696 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
697 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
698 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
699 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
700 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
701 },\r
702\r
703 //\r
704 // The offset of the start of the BIOS image in flash. This value is platform specific\r
705 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
706 //\r
707 ((EON_EN25Q16_SIZE >= FLASH_SIZE) ? EON_EN25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
708\r
709 //\r
710 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
711 //\r
712 FLASH_SIZE\r
713 },\r
714 {\r
715 SF_VENDOR_ID_EON, // VendorId\r
716 SF_DEVICE_ID0_EN25QXX, // DeviceId 0\r
717 SF_DEVICE_ID1_EN25Q32, // DeviceId 1\r
718 {\r
719 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
720 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
721 },\r
722 {\r
723 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
724 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
725 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
726 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
727 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
728 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
729 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
730 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
731 },\r
732\r
733 //\r
734 // The offset of the start of the BIOS image in flash. This value is platform specific\r
735 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
736 //\r
737 ((EON_EN25Q32_SIZE >= FLASH_SIZE) ? EON_EN25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
738\r
739 //\r
740 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
741 //\r
742 FLASH_SIZE\r
743 },\r
744 {\r
745 SF_VENDOR_ID_EON, // VendorId\r
746 SF_DEVICE_ID0_EN25QXX, // DeviceId 0\r
747 SF_DEVICE_ID1_EN25Q64, // DeviceId 1\r
748 {\r
749 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
750 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
751 },\r
752 {\r
753 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
754 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
755 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
756 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
757 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
758 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
759 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
760 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
761 },\r
762\r
763 //\r
764 // The offset of the start of the BIOS image in flash. This value is platform specific\r
765 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
766 //\r
767 ((EON_EN25Q64_SIZE >= FLASH_SIZE) ? EON_EN25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
768\r
769 //\r
770 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
771 //\r
772 FLASH_SIZE\r
773 },\r
774 {\r
775 SF_VENDOR_ID_EON, // VendorId\r
776 SF_DEVICE_ID0_EN25QXX, // DeviceId 0\r
777 SF_DEVICE_ID1_EN25Q128, // DeviceId 1\r
778 {\r
779 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
780 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
781 },\r
782 {\r
783 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
784 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
785 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
786 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
787 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
788 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
789 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
790 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
791 },\r
792\r
793 //\r
794 // The offset of the start of the BIOS image in flash. This value is platform specific\r
795 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
796 //\r
797 ((EON_EN25Q128_SIZE >= FLASH_SIZE) ? EON_EN25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
798\r
799 //\r
800 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
801 //\r
802 FLASH_SIZE\r
803 },\r
804 {\r
805 SF_VENDOR_ID_AMIC, // VendorId\r
806 SF_DEVICE_ID0_A25L016, // DeviceId 0\r
807 SF_DEVICE_ID1_A25L016, // DeviceId 1\r
808 {\r
809 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
810 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
811 },\r
812 {\r
813 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
814 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
815 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
816 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
817 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
818 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
819 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
820 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
821 },\r
822\r
823 //\r
824 // The offset of the start of the BIOS image in flash. This value is platform specific\r
825 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
826 //\r
827 ((AMIC_A25L16_SIZE >= FLASH_SIZE) ? AMIC_A25L16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
828\r
829 //\r
830 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
831 //\r
832 FLASH_SIZE\r
833 }\r
834};\r
7a0a32f1 835\r
EFI Development Kit II mirror for PVE