[mirror_edk2.git] / Vlv2TbltDevicePkg / Library / MultiPlatformLib / BoardGpios / BoardGpios.c

/** @file\r
  Gpio setting for multiplatform..\r
\r
  Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
                                                                                   \r\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
                                                                                   \r\r
\r
**/\r
\r
#include <BoardGpios.h>\r
#include <Guid/SetupVariable.h>\r
\r
//\r
//AlpineValley platform ocde begin\r
//\r
#define AV_SC_REG_GPIOS_MUXES_SEL0 0x48\r
#define AV_SC_REG_GPIOS_MUXES_SEL1 0x4C\r
#define AV_SC_REG_GPIOS_MUXES_SEL2 0x50\r
#define AV_SC_REG_GPIOS_MUXES_EN0  0x54\r
#define AV_SC_REG_GPIOS_MUXES_EN1  0x58\r
#define AV_SC_REG_GPIOS_MUXES_EN2  0x5C\r
//\r
//AlpineValley platform code end\r
//\r
\r
EFI_GUID  gPeiSmbusPpiGuid               = EFI_PEI_SMBUS_PPI_GUID;\r
\r
/**\r
  @param None\r
\r
  @retval EFI_SUCCESS    The function completed successfully.\r
\r
**/\r
EFI_STATUS\r
ConfigurePlatformSysCtrlGpio (\r
  IN EFI_PEI_SERVICES                   **PeiServices,\r
  IN EFI_PEI_NOTIFY_DESCRIPTOR          *NotifyDescriptor,\r
  IN VOID                               *SmbusPpi\r
  )\r
{\r
  //\r
  //AlpineValley platform code begin\r
  //\r
  // Initialize GPIO Settings:\r
  //\r
  UINT32        Status;\r
  EFI_PLATFORM_INFO_HOB               *PlatformInfoHob;\r
\r
   DEBUG ((EFI_D_INFO, "ConfigurePlatformSysCtrlGpio()...\n"));\r
\r
  //\r
  // Obtain Platform Info from HOB.\r
  //\r
  Status = GetPlatformInfoHob ((const EFI_PEI_SERVICES **)PeiServices, &PlatformInfoHob);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // The GPIO settings are dependent upon the platform.  Obtain the Board ID through\r
  // the EC to determine the current platform.\r
  //\r
   DEBUG ((EFI_D_INFO, "Platform Flavor | Board ID = 0x%X | 0x%X\n", PlatformInfoHob->PlatformFlavor, PlatformInfoHob->BoardId));\r
\r
\r
\r
  Status = (**PeiServices).LocatePpi (\r
                            (const EFI_PEI_SERVICES **)PeiServices,\r
                            &gPeiSmbusPpiGuid,\r
                            0,\r
                            NULL,\r
                            (void **)&SmbusPpi\r
                            );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Select/modify the GPIO initialization data based on the Board ID.\r
  //\r
  switch (PlatformInfoHob->BoardId)\r
  {\r
    default:\r
      Status = EFI_SUCCESS;\r
\r
      //\r
      // Do nothing for other RVP boards.\r
      //\r
      break;\r
  }\r
  return Status;\r
}\r
\r
static EFI_PEI_NOTIFY_DESCRIPTOR    mNotifyList[] = {\r
  {\r
    EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
    &gEfiPeiSmbusPpiGuid,\r
    ConfigurePlatformSysCtrlGpio\r
  }\r
};\r
\r
EFI_STATUS\r
InstallPlatformSysCtrlGPIONotify (\r
  IN CONST EFI_PEI_SERVICES           **PeiServices\r
  )\r
{\r
  EFI_STATUS                    Status;\r
\r
  DEBUG ((EFI_D_INFO, "InstallPlatformSysCtrlGPIONotify()...\n"));\r
\r
  Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);\r
  ASSERT_EFI_ERROR (Status);\r
  return EFI_SUCCESS;\r
\r
}\r
\r
#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3             BIT3 // UART IRQ3 Enable\r
\r
/**\r
  Returns the Correct GPIO table for Mobile/Desktop respectively.\r
  Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.\r
\r
  @param PeiServices             General purpose services available to every PEIM.\r
  @param PlatformInfoHob         PlatformInfoHob pointer with PlatformFlavor specified.\r
  @param BoardId                 BoardId ID as determined through the EC.\r
\r
  @retval EFI_SUCCESS            The function completed successfully.\r
  @retval EFI_DEVICE_ERROR       KSC fails to respond.\r
\r
**/\r
EFI_STATUS\r
MultiPlatformGpioTableInit (\r
  IN CONST EFI_PEI_SERVICES     **PeiServices,\r
  IN EFI_PLATFORM_INFO_HOB      *PlatformInfoHob\r
  )\r
{\r
  EFI_STATUS                      Status;\r
  EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiReadOnlyVarPpi;\r
  UINTN                           VarSize;\r
  SYSTEM_CONFIGURATION            SystemConfiguration;\r
\r
  DEBUG ((EFI_D_INFO, "MultiPlatformGpioTableInit()...\n"));\r
\r
  //\r
  // Select/modify the GPIO initialization data based on the Board ID.\r
  //\r
  switch (PlatformInfoHob->BoardId) {\r
\r
  case BOARD_ID_MINNOW2: // Minnow2\r
  case BOARD_ID_MINNOW2_TURBOT: \r
   Status = (**PeiServices).LocatePpi (\r
                             PeiServices,\r
                             &gEfiPeiReadOnlyVariable2PpiGuid,\r
                             0,\r
                             NULL,\r
                             (void **)&PeiReadOnlyVarPpi\r
                             );\r
    ASSERT_EFI_ERROR (Status);\r
   \r
    VarSize = sizeof (SYSTEM_CONFIGURATION);\r
    Status = PeiReadOnlyVarPpi->GetVariable ( \r
                                  PeiReadOnlyVarPpi, \r
                                  PLATFORM_SETUP_VARIABLE_NAME, \r
                                  &gEfiSetupVariableGuid,\r
                                  NULL,\r
                                  &VarSize,\r
                                  &SystemConfiguration\r
                                  );\r
                                                                       \r
     if (SystemConfiguration.GpioWakeCapability == 1) {\r
      PlatformInfoHob->PlatformCfioData     = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2CfioInitData2;\r
     }\r
     else {\r
      PlatformInfoHob->PlatformCfioData     = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2CfioInitData;\r
     }	\r
	 \r
     PlatformInfoHob->PlatformGpioData_NC  = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_NC[0];\r
     PlatformInfoHob->PlatformGpioData_SC  = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_SC[0];\r
     PlatformInfoHob->PlatformGpioData_SUS = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_SUS[0];\r
     break;\r
\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
UINT32\r
GPIORead32 (\r
  IN  UINT32 mmio_conf\r
  )\r
{\r
  UINT32 conf_val;\r
  UINT32 i;\r
  conf_val = MmioRead32(mmio_conf);\r
  for(i=0;i<5;i++){\r
    if(conf_val == 0xffffffff)\r
      conf_val = MmioRead32(mmio_conf);\r
      else\r
        break;\r
  }\r
\r
  return conf_val;\r
}\r
\r
/**\r
\r
  Set GPIO CONF0 and PAD_VAL registers for NC/SC/SUS GPIO clusters\r
\r
  @param Gpio_Mmio_Offset          GPIO_SCORE_OFFSET or GPIO_NCORE_OFFSET or GPIO_SSUS_OFFSET.\r
  @param Gpio_Pin_Num              Pin numbers to config for each GPIO clusters.\r
  @param Gpio_Conf_Data            GPIO_CONF_PAD_INIT data array for each GPIO clusters.\r
\r
**/\r
VOID\r
InternalGpioConfig (\r
  IN UINT32             Gpio_Mmio_Offset,\r
  IN UINT32             Gpio_Pin_Num,\r
  GPIO_CONF_PAD_INIT*   Gpio_Conf_Data\r
  )\r
{\r
  UINT32    index;\r
  UINT32    mmio_conf0;\r
  UINT32    mmio_padval;\r
  PAD_CONF0 conf0_val;\r
  PAD_VAL   pad_val;\r
\r
  //\r
  // GPIO WELL -- Memory base registers\r
  //\r
\r
  // A0 BIOS Spec doesn't mention it although X0 does. comment out now.\r
  // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900\r
  //\r
  for(index=0; index < Gpio_Pin_Num; index++)\r
  {\r
  	//\r
    // Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.\r
    //\r
    mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;\r
    mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL   + Gpio_Conf_Data[index].offset * 16;\r
\r
#ifdef EFI_DEBUG\r
    DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));\r
\r
#endif\r
    DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",\r
      Gpio_Conf_Data[index].usage,\r
      Gpio_Conf_Data[index].func,\r
      Gpio_Conf_Data[index].int_type,\r
      Gpio_Conf_Data[index].pull,\r
      mmio_conf0));\r
\r
    //\r
    // Step 1: PadVal Programming.\r
    //\r
    pad_val.dw = GPIORead32(mmio_padval);\r
\r
    //\r
    // Config PAD_VAL only for GPIO (Non-Native) Pin\r
    //\r
    if(Native != Gpio_Conf_Data[index].usage)\r
    {\r
      pad_val.dw &= ~0x6; // Clear bits 1:2\r
      pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6);  // Set bits 1:2 according to PadVal\r
\r
        //\r
        // set GPO default value\r
        //\r
        if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)\r
        {\r
        pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;\r
        }\r
    }\r
\r
\r
    DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));\r
\r
    MmioWrite32(mmio_padval, pad_val.dw);\r
\r
    //\r
    // Step 2: CONF0 Programming\r
    // Read GPIO default CONF0 value, which is assumed to be default value after reset.\r
    //\r
    conf0_val.dw = GPIORead32(mmio_conf0);\r
\r
    //\r
    // Set Function #\r
    //\r
    conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;\r
\r
    if(GPO == Gpio_Conf_Data[index].usage)\r
    {\r
      //\r
      // If used as GPO, then internal pull need to be disabled.\r
      //\r
      conf0_val.r.Pull_assign = 0;  // Non-pull\r
    }\r
    else\r
    {\r
      //\r
      // Set PullUp / PullDown\r
      //\r
      if(P_20K_H == Gpio_Conf_Data[index].pull)\r
      {\r
        conf0_val.r.Pull_assign = 0x1;  // PullUp\r
        conf0_val.r.Pull_strength = 0x2;// 20K\r
      }\r
      else if(P_20K_L == Gpio_Conf_Data[index].pull)\r
      {\r
        conf0_val.r.Pull_assign = 0x2;  // PullDown\r
        conf0_val.r.Pull_strength = 0x2;// 20K\r
      }\r
      else if(P_10K_H == Gpio_Conf_Data[index].pull)\r
      {\r
        conf0_val.r.Pull_assign = 0x1; 	// PullUp\r
        conf0_val.r.Pull_strength = 0x1;// 10K\r
      }\r
      else if(P_10K_L == Gpio_Conf_Data[index].pull)\r
      {\r
        conf0_val.r.Pull_assign = 0x2; 	// PullDown\r
        conf0_val.r.Pull_strength = 0x1;// 10K\r
      }\r
      else if(P_2K_H == Gpio_Conf_Data[index].pull)\r
      {\r
        conf0_val.r.Pull_assign = 0x1;  // PullUp\r
        conf0_val.r.Pull_strength = 0x0;// 2K\r
      }\r
      else if(P_2K_L == Gpio_Conf_Data[index].pull)\r
      {\r
        conf0_val.r.Pull_assign = 0x2;  // PullDown\r
        conf0_val.r.Pull_strength = 0x0;// 2K\r
      }\r
      else if(P_NONE == Gpio_Conf_Data[index].pull)\r
      {\r
        conf0_val.r.Pull_assign = 0;	// Non-pull\r
      }\r
      else\r
      {\r
        ASSERT(FALSE);  // Invalid value\r
      }\r
    }\r
\r
\r
    //\r
    // Set INT Trigger Type\r
    //\r
    conf0_val.dw &= ~0x0f000000;  // Clear bits 27:24\r
\r
    //\r
    // Set INT Trigger Type\r
    //\r
    if(TRIG_ == Gpio_Conf_Data[index].int_type)\r
    {\r
      //\r
      // Interrupt not capable, clear bits 27:24\r
      //\r
    }\r
    else\r
    {\r
      conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;\r
    }\r
\r
    DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));\r
\r
    //\r
    // Write back the targeted GPIO config value according to platform (board) GPIO setting.\r
    //\r
    MmioWrite32 (mmio_conf0, conf0_val.dw);\r
  }\r
\r
  //\r
  // A0 BIOS Spec doesn't mention it although X0 does. comment out now.\r
  // GPIO SCORE write 0x01001002 to IOBASE + 0x0900\r
  //\r
}\r
\r
/**\r
  Returns the Correct GPIO table for Mobile/Desktop respectively.\r
  Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.\r
\r
  @param PeiServices               General purpose services available to every PEIM.\r
  @param PlatformInfoHob           PlatformInfoHob pointer with PlatformFlavor specified.\r
  @param BoardId                   BoardId ID as determined through the EC.\r
\r
  @retval EFI_SUCCESS              The function completed successfully.\r
  @retval EFI_DEVICE_ERROR         KSC fails to respond.\r
\r
**/\r
EFI_STATUS\r
MultiPlatformGpioProgram (\r
  IN CONST EFI_PEI_SERVICES     **PeiServices,\r
  IN EFI_PLATFORM_INFO_HOB      *PlatformInfoHob\r
  )\r
{\r
#if !_SIMIC_\r
  CFIO_INIT_STRUCT*           PlatformCfioDataPtr;\r
\r
  PlatformCfioDataPtr = (CFIO_INIT_STRUCT *) (UINTN) PlatformInfoHob->PlatformCfioData;\r
  DEBUG ((EFI_D_INFO, "MultiPlatformGpioProgram()...\n"));\r
\r
  //\r
  //  SCORE GPIO WELL -- IO base registers\r
  //\r
\r
  //\r
  // GPIO_USE_SEL Register -> 1 = GPIO 0 = Native\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL, PlatformCfioDataPtr->Use_Sel_SC0);\r
\r
  //\r
  // Set GP_LVL Register\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL , PlatformCfioDataPtr->GP_Lvl_SC0);\r
\r
  //\r
  // GP_IO_SEL Register -> 1 = Input 0 = Output.  If Native Mode don't care\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL, PlatformCfioDataPtr->Io_Sel_SC0);\r
\r
  //\r
  // GPIO Triger Positive Edge Enable Register\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TPE, PlatformCfioDataPtr->TPE_SC0);\r
\r
  //\r
  //  GPIO Trigger Negative Edge Enable Register\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TNE, PlatformCfioDataPtr->TNE_SC0);\r
\r
  //\r
  //  GPIO Trigger Status\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TS, PlatformCfioDataPtr->TS_SC0);\r
\r
  //\r
  // GPIO_USE_SEL2 Register -> 1 = GPIO 0 = Native\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL2, PlatformCfioDataPtr->Use_Sel_SC1);\r
\r
  //\r
  // Set GP_LVL2 Register\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL2, PlatformCfioDataPtr->GP_Lvl_SC1);\r
\r
  //\r
  // GP_IO_SEL2 Register -> 1 = Input 0 = Output.  If Native Mode don't care\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL2, PlatformCfioDataPtr->Io_Sel_SC1);\r
\r
  //\r
  // GPIO_USE_SEL3 Register -> 1 = GPIO 0 = Native\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL3, PlatformCfioDataPtr->Use_Sel_SC2);\r
\r
  //\r
  // Set GP_LVL3 Register\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL3, PlatformCfioDataPtr->GP_Lvl_SC2);\r
\r
  //\r
  // GP_IO_SEL3 Register -> 1 = Input 0 = Output if Native Mode don't care\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL3, PlatformCfioDataPtr->Io_Sel_SC2);\r
\r
  //\r
  //  SUS GPIO WELL -- IO base registers\r
  //\r
\r
  //\r
  // GPIO_USE_SEL Register -> 1 = GPIO 0 = Native\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_USE_SEL, PlatformCfioDataPtr->Use_Sel_SS);\r
\r
  //\r
  // Set GP_LVL Register\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_LVL , PlatformCfioDataPtr->GP_Lvl_SS);\r
\r
  //\r
  // GP_IO_SEL Register -> 1 = Input 0 = Output.  If Native Mode don't care.\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_IO_SEL, PlatformCfioDataPtr->Io_Sel_SS);\r
\r
  //\r
  // GPIO Triger Positive Edge Enable Register.\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TPE, PlatformCfioDataPtr->TPE_SS);\r
\r
  //\r
  //  GPIO Trigger Negative Edge Enable Register.\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TNE, PlatformCfioDataPtr->TNE_SS);\r
\r
  //\r
  //  GPIO Trigger Status.\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TS, PlatformCfioDataPtr->TS_SS);\r
\r
  //\r
  //  GPIO Wake Enable.\r
  //\r
  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_WAKE_EN, PlatformCfioDataPtr->WE_SS);\r
\r
  //\r
  // Config SC/NC/SUS GPIO Pins\r
  //\r
  switch (PlatformInfoHob->BoardId) {\r
    case BOARD_ID_MINNOW2:\r
    case BOARD_ID_MINNOW2_TURBOT:\r
      DEBUG ((EFI_D_INFO, "Start to config Minnow2 GPIO pins\n"));\r
      InternalGpioConfig(GPIO_SCORE_OFFSET, sizeof(mMinnow2_GpioInitData_SC)/sizeof(mMinnow2_GpioInitData_SC[0]),   (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_SC);\r
      InternalGpioConfig(GPIO_NCORE_OFFSET, sizeof(mMinnow2_GpioInitData_NC)/sizeof(mMinnow2_GpioInitData_NC[0]),   (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_NC);\r
      InternalGpioConfig(GPIO_SSUS_OFFSET,  sizeof(mMinnow2_GpioInitData_SUS)/sizeof(mMinnow2_GpioInitData_SUS[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_SUS);\r
      break;\r
    default:\r
\r
      break;\r
  }\r
\r
   //\r
   // configure the CFIO Pnp settings\r
   //\r
   if (PlatformInfoHob->CfioEnabled) {\r
     if (PlatformInfoHob->BoardId == BOARD_ID_MINNOW2 || PlatformInfoHob->BoardId == BOARD_ID_MINNOW2_TURBOT){\r
       InternalGpioConfig(GPIO_SCORE_OFFSET, sizeof(mNB_BB_FAB3_GpioInitData_SC_TRI)/sizeof(mNB_BB_FAB3_GpioInitData_SC_TRI[0]), (GPIO_CONF_PAD_INIT *) (UINTN)PlatformInfoHob->PlatformGpioData_SC_TRI);\r
     }\r
   }\r
#else\r
   DEBUG ((EFI_D_INFO, "Skip MultiPlatformGpioProgram()...for SIMICS or HYB model\n"));\r
#endif\r
  return EFI_SUCCESS;\r
}\r
\r
Commit	Line	Data
3cbfba02 DW	1	/** @file\r
	2	Gpio setting for multiplatform..\r
	3	\r
	4	Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
	5	\r\r
9dc8036d MK	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
9dc8036d MK	7	\r
3cbfba02 DW	8	\r\r
	9	\r
	10	**/\r
	11	\r
	12	#include <BoardGpios.h>\r
	13	#include <Guid/SetupVariable.h>\r
	14	\r
	15	//\r
	16	//AlpineValley platform ocde begin\r
	17	//\r
	18	#define AV_SC_REG_GPIOS_MUXES_SEL0 0x48\r
	19	#define AV_SC_REG_GPIOS_MUXES_SEL1 0x4C\r
	20	#define AV_SC_REG_GPIOS_MUXES_SEL2 0x50\r
	21	#define AV_SC_REG_GPIOS_MUXES_EN0 0x54\r
	22	#define AV_SC_REG_GPIOS_MUXES_EN1 0x58\r
	23	#define AV_SC_REG_GPIOS_MUXES_EN2 0x5C\r
	24	//\r
	25	//AlpineValley platform code end\r
	26	//\r
	27	\r
	28	EFI_GUID gPeiSmbusPpiGuid = EFI_PEI_SMBUS_PPI_GUID;\r
	29	\r
	30	/**\r
	31	@param None\r
	32	\r
	33	@retval EFI_SUCCESS The function completed successfully.\r
	34	\r
	35	**/\r
	36	EFI_STATUS\r
	37	ConfigurePlatformSysCtrlGpio (\r
	38	IN EFI_PEI_SERVICES **PeiServices,\r
	39	IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
	40	IN VOID *SmbusPpi\r
	41	)\r
	42	{\r
	43	//\r
	44	//AlpineValley platform code begin\r
	45	//\r
	46	// Initialize GPIO Settings:\r
	47	//\r
	48	UINT32 Status;\r
	49	EFI_PLATFORM_INFO_HOB *PlatformInfoHob;\r
	50	\r
	51	DEBUG ((EFI_D_INFO, "ConfigurePlatformSysCtrlGpio()...\n"));\r
	52	\r
	53	//\r
	54	// Obtain Platform Info from HOB.\r
	55	//\r
	56	Status = GetPlatformInfoHob ((const EFI_PEI_SERVICES **)PeiServices, &PlatformInfoHob);\r
	57	ASSERT_EFI_ERROR (Status);\r
	58	\r
	59	//\r
	60	// The GPIO settings are dependent upon the platform. Obtain the Board ID through\r
	61	// the EC to determine the current platform.\r
	62	//\r
	63	DEBUG ((EFI_D_INFO, "Platform Flavor \| Board ID = 0x%X \| 0x%X\n", PlatformInfoHob->PlatformFlavor, PlatformInfoHob->BoardId));\r
	64	\r
	65	\r
	66	\r
	67	Status = (**PeiServices).LocatePpi (\r
	68	(const EFI_PEI_SERVICES **)PeiServices,\r
	69	&gPeiSmbusPpiGuid,\r
	70	0,\r
	71	NULL,\r
72	(void **)&SmbusPpi\r
73	);\r
74	ASSERT_EFI_ERROR (Status);\r
75	\r
76	//\r
77	// Select/modify the GPIO initialization data based on the Board ID.\r
78	//\r
79	switch (PlatformInfoHob->BoardId)\r
80	{\r
81	default:\r
82	Status = EFI_SUCCESS;\r
83	\r
84	//\r
85	// Do nothing for other RVP boards.\r
86	//\r
87	break;\r
88	}\r
89	return Status;\r
90	}\r
91	\r
92	static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {\r
93	{\r
94	EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK\| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
95	&gEfiPeiSmbusPpiGuid,\r
96	ConfigurePlatformSysCtrlGpio\r
97	}\r
98	};\r
99	\r
100	EFI_STATUS\r
101	InstallPlatformSysCtrlGPIONotify (\r
102	IN CONST EFI_PEI_SERVICES **PeiServices\r
103	)\r
104	{\r
105	EFI_STATUS Status;\r
106	\r
107	DEBUG ((EFI_D_INFO, "InstallPlatformSysCtrlGPIONotify()...\n"));\r
108	\r
109	Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);\r
110	ASSERT_EFI_ERROR (Status);\r
111	return EFI_SUCCESS;\r
112	\r
113	}\r
114	\r
115	#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3 Enable\r
116	\r
117	/**\r
118	Returns the Correct GPIO table for Mobile/Desktop respectively.\r
119	Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.\r
120	\r
121	@param PeiServices General purpose services available to every PEIM.\r
122	@param PlatformInfoHob PlatformInfoHob pointer with PlatformFlavor specified.\r
123	@param BoardId BoardId ID as determined through the EC.\r
124	\r
125	@retval EFI_SUCCESS The function completed successfully.\r
126	@retval EFI_DEVICE_ERROR KSC fails to respond.\r
127	\r
128	**/\r
129	EFI_STATUS\r
130	MultiPlatformGpioTableInit (\r
131	IN CONST EFI_PEI_SERVICES **PeiServices,\r
132	IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob\r
133	)\r
134	{\r
135	EFI_STATUS Status;\r
136	EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiReadOnlyVarPpi;\r
137	UINTN VarSize;\r
138	SYSTEM_CONFIGURATION SystemConfiguration;\r
139	\r
140	DEBUG ((EFI_D_INFO, "MultiPlatformGpioTableInit()...\n"));\r
141	\r
142	//\r
143	// Select/modify the GPIO initialization data based on the Board ID.\r
144	//\r
145	switch (PlatformInfoHob->BoardId) {\r
146	\r
147	case BOARD_ID_MINNOW2: // Minnow2\r
8b7a63e7	148	case BOARD_ID_MINNOW2_TURBOT: \r
3cbfba02 DW	149	Status = (**PeiServices).LocatePpi (\r
	150	PeiServices,\r
	151	&gEfiPeiReadOnlyVariable2PpiGuid,\r
	152	0,\r
	153	NULL,\r
	154	(void **)&PeiReadOnlyVarPpi\r
	155	);\r
	156	ASSERT_EFI_ERROR (Status);\r
	157	\r
	158	VarSize = sizeof (SYSTEM_CONFIGURATION);\r
	159	Status = PeiReadOnlyVarPpi->GetVariable ( \r
	160	PeiReadOnlyVarPpi, \r
	161	PLATFORM_SETUP_VARIABLE_NAME, \r
	162	&gEfiSetupVariableGuid,\r
	163	NULL,\r
	164	&VarSize,\r
	165	&SystemConfiguration\r
	166	);\r
	167	\r
	168	if (SystemConfiguration.GpioWakeCapability == 1) {\r
	169	PlatformInfoHob->PlatformCfioData = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2CfioInitData2;\r
	170	}\r
	171	else {\r
	172	PlatformInfoHob->PlatformCfioData = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2CfioInitData;\r
	173	} \r
	174	\r
	175	PlatformInfoHob->PlatformGpioData_NC = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_NC[0];\r
	176	PlatformInfoHob->PlatformGpioData_SC = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_SC[0];\r
	177	PlatformInfoHob->PlatformGpioData_SUS = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_SUS[0];\r
	178	break;\r
	179	\r
	180	}\r
	181	\r
	182	return EFI_SUCCESS;\r
	183	}\r
	184	\r
	185	UINT32\r
	186	GPIORead32 (\r
	187	IN UINT32 mmio_conf\r
	188	)\r
	189	{\r
	190	UINT32 conf_val;\r
	191	UINT32 i;\r
	192	conf_val = MmioRead32(mmio_conf);\r
	193	for(i=0;i<5;i++){\r
	194	if(conf_val == 0xffffffff)\r
	195	conf_val = MmioRead32(mmio_conf);\r
	196	else\r
	197	break;\r
	198	}\r
	199	\r
	200	return conf_val;\r
	201	}\r
	202	\r
	203	/**\r
	204	\r
	205	Set GPIO CONF0 and PAD_VAL registers for NC/SC/SUS GPIO clusters\r
	206	\r
	207	@param Gpio_Mmio_Offset GPIO_SCORE_OFFSET or GPIO_NCORE_OFFSET or GPIO_SSUS_OFFSET.\r
	208	@param Gpio_Pin_Num Pin numbers to config for each GPIO clusters.\r
	209	@param Gpio_Conf_Data GPIO_CONF_PAD_INIT data array for each GPIO clusters.\r
	210	\r
	211	**/\r
	212	VOID\r
213	InternalGpioConfig (\r
214	IN UINT32 Gpio_Mmio_Offset,\r
215	IN UINT32 Gpio_Pin_Num,\r
216	GPIO_CONF_PAD_INIT* Gpio_Conf_Data\r
217	)\r
218	{\r
219	UINT32 index;\r
220	UINT32 mmio_conf0;\r
221	UINT32 mmio_padval;\r
222	PAD_CONF0 conf0_val;\r
223	PAD_VAL pad_val;\r
224	\r
225	//\r
226	// GPIO WELL -- Memory base registers\r
227	//\r
228	\r
229	// A0 BIOS Spec doesn't mention it although X0 does. comment out now.\r
230	// GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900\r
231	//\r
232	for(index=0; index < Gpio_Pin_Num; index++)\r
233	{\r
234	//\r
235	// Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.\r
236	//\r
237	mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;\r
238	mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;\r
239	\r
240	#ifdef EFI_DEBUG\r
241	DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));\r
242	\r
243	#endif\r
244	DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",\r
245	Gpio_Conf_Data[index].usage,\r
246	Gpio_Conf_Data[index].func,\r
247	Gpio_Conf_Data[index].int_type,\r
248	Gpio_Conf_Data[index].pull,\r
249	mmio_conf0));\r
250	\r
251	//\r
252	// Step 1: PadVal Programming.\r
253	//\r
254	pad_val.dw = GPIORead32(mmio_padval);\r
255	\r
256	//\r
257	// Config PAD_VAL only for GPIO (Non-Native) Pin\r
258	//\r
259	if(Native != Gpio_Conf_Data[index].usage)\r
260	{\r
261	pad_val.dw &= ~0x6; // Clear bits 1:2\r
262	pad_val.dw \|= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal\r
263	\r
264	//\r
265	// set GPO default value\r
266	//\r
267	if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)\r
268	{\r
269	pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;\r
270	}\r
271	}\r
272	\r
273	\r
274	DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));\r
275	\r
276	MmioWrite32(mmio_padval, pad_val.dw);\r
277	\r
278	//\r
279	// Step 2: CONF0 Programming\r
280	// Read GPIO default CONF0 value, which is assumed to be default value after reset.\r
281	//\r
282	conf0_val.dw = GPIORead32(mmio_conf0);\r
283	\r
284	//\r
285	// Set Function #\r
286	//\r
287	conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;\r
288	\r
289	if(GPO == Gpio_Conf_Data[index].usage)\r
290	{\r
291	//\r
292	// If used as GPO, then internal pull need to be disabled.\r
293	//\r
294	conf0_val.r.Pull_assign = 0; // Non-pull\r
295	}\r
296	else\r
297	{\r
298	//\r
299	// Set PullUp / PullDown\r
300	//\r
301	if(P_20K_H == Gpio_Conf_Data[index].pull)\r
302	{\r
303	conf0_val.r.Pull_assign = 0x1; // PullUp\r
304	conf0_val.r.Pull_strength = 0x2;// 20K\r
305	}\r
306	else if(P_20K_L == Gpio_Conf_Data[index].pull)\r
307	{\r
308	conf0_val.r.Pull_assign = 0x2; // PullDown\r
309	conf0_val.r.Pull_strength = 0x2;// 20K\r
310	}\r
311	else if(P_10K_H == Gpio_Conf_Data[index].pull)\r
312	{\r
313	conf0_val.r.Pull_assign = 0x1; // PullUp\r
314	conf0_val.r.Pull_strength = 0x1;// 10K\r
315	}\r
316	else if(P_10K_L == Gpio_Conf_Data[index].pull)\r
317	{\r
318	conf0_val.r.Pull_assign = 0x2; // PullDown\r
319	conf0_val.r.Pull_strength = 0x1;// 10K\r
320	}\r
321	else if(P_2K_H == Gpio_Conf_Data[index].pull)\r
322	{\r
323	conf0_val.r.Pull_assign = 0x1; // PullUp\r
324	conf0_val.r.Pull_strength = 0x0;// 2K\r
325	}\r
326	else if(P_2K_L == Gpio_Conf_Data[index].pull)\r
327	{\r
328	conf0_val.r.Pull_assign = 0x2; // PullDown\r
329	conf0_val.r.Pull_strength = 0x0;// 2K\r
330	}\r
331	else if(P_NONE == Gpio_Conf_Data[index].pull)\r
332	{\r
333	conf0_val.r.Pull_assign = 0; // Non-pull\r
334	}\r
335	else\r
336	{\r
337	ASSERT(FALSE); // Invalid value\r
338	}\r
339	}\r
340	\r
341	\r
342	//\r
343	// Set INT Trigger Type\r
344	//\r
345	conf0_val.dw &= ~0x0f000000; // Clear bits 27:24\r
346	\r
347	//\r
348	// Set INT Trigger Type\r
349	//\r
350	if(TRIG_ == Gpio_Conf_Data[index].int_type)\r
351	{\r
352	//\r
353	// Interrupt not capable, clear bits 27:24\r
354	//\r
355	}\r
356	else\r
357	{\r
358	conf0_val.dw \|= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;\r
359	}\r
360	\r
361	DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));\r
362	\r
363	//\r
364	// Write back the targeted GPIO config value according to platform (board) GPIO setting.\r
365	//\r
366	MmioWrite32 (mmio_conf0, conf0_val.dw);\r
367	}\r
368	\r
369	//\r
370	// A0 BIOS Spec doesn't mention it although X0 does. comment out now.\r
371	// GPIO SCORE write 0x01001002 to IOBASE + 0x0900\r
372	//\r
373	}\r
374	\r
375	/**\r
376	Returns the Correct GPIO table for Mobile/Desktop respectively.\r
377	Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.\r
378	\r
379	@param PeiServices General purpose services available to every PEIM.\r
380	@param PlatformInfoHob PlatformInfoHob pointer with PlatformFlavor specified.\r
381	@param BoardId BoardId ID as determined through the EC.\r
382	\r
383	@retval EFI_SUCCESS The function completed successfully.\r
384	@retval EFI_DEVICE_ERROR KSC fails to respond.\r
385	\r
386	**/\r
387	EFI_STATUS\r
388	MultiPlatformGpioProgram (\r
389	IN CONST EFI_PEI_SERVICES **PeiServices,\r
390	IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob\r
391	)\r
392	{\r
393	#if !_SIMIC_\r
394	CFIO_INIT_STRUCT* PlatformCfioDataPtr;\r
395	\r
396	PlatformCfioDataPtr = (CFIO_INIT_STRUCT *) (UINTN) PlatformInfoHob->PlatformCfioData;\r
397	DEBUG ((EFI_D_INFO, "MultiPlatformGpioProgram()...\n"));\r
398	\r
399	//\r
400	// SCORE GPIO WELL -- IO base registers\r
401	//\r
402	\r
403	//\r
404	// GPIO_USE_SEL Register -> 1 = GPIO 0 = Native\r
405	//\r
406	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL, PlatformCfioDataPtr->Use_Sel_SC0);\r
407	\r
408	//\r
409	// Set GP_LVL Register\r
410	//\r
411	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL , PlatformCfioDataPtr->GP_Lvl_SC0);\r
412	\r
413	//\r
414	// GP_IO_SEL Register -> 1 = Input 0 = Output. If Native Mode don't care\r
415	//\r
416	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL, PlatformCfioDataPtr->Io_Sel_SC0);\r
417	\r
418	//\r
419	// GPIO Triger Positive Edge Enable Register\r
420	//\r
421	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TPE, PlatformCfioDataPtr->TPE_SC0);\r
422	\r
423	//\r
424	// GPIO Trigger Negative Edge Enable Register\r
425	//\r
426	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TNE, PlatformCfioDataPtr->TNE_SC0);\r
427	\r
428	//\r
429	// GPIO Trigger Status\r
430	//\r
431	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TS, PlatformCfioDataPtr->TS_SC0);\r
432	\r
433	//\r
434	// GPIO_USE_SEL2 Register -> 1 = GPIO 0 = Native\r
435	//\r
436	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL2, PlatformCfioDataPtr->Use_Sel_SC1);\r
437	\r
438	//\r
439	// Set GP_LVL2 Register\r
440	//\r
441	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL2, PlatformCfioDataPtr->GP_Lvl_SC1);\r
442	\r
443	//\r
444	// GP_IO_SEL2 Register -> 1 = Input 0 = Output. If Native Mode don't care\r
445	//\r
446	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL2, PlatformCfioDataPtr->Io_Sel_SC1);\r
447	\r
448	//\r
449	// GPIO_USE_SEL3 Register -> 1 = GPIO 0 = Native\r
450	//\r
451	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL3, PlatformCfioDataPtr->Use_Sel_SC2);\r
452	\r
453	//\r
454	// Set GP_LVL3 Register\r
455	//\r
456	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL3, PlatformCfioDataPtr->GP_Lvl_SC2);\r
457	\r
458	//\r
459	// GP_IO_SEL3 Register -> 1 = Input 0 = Output if Native Mode don't care\r
460	//\r
461	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL3, PlatformCfioDataPtr->Io_Sel_SC2);\r
462	\r
463	//\r
464	// SUS GPIO WELL -- IO base registers\r
465	//\r
466	\r
467	//\r
468	// GPIO_USE_SEL Register -> 1 = GPIO 0 = Native\r
469	//\r
470	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_USE_SEL, PlatformCfioDataPtr->Use_Sel_SS);\r
471	\r
472	//\r
473	// Set GP_LVL Register\r
474	//\r
475	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_LVL , PlatformCfioDataPtr->GP_Lvl_SS);\r
476	\r
477	//\r
478	// GP_IO_SEL Register -> 1 = Input 0 = Output. If Native Mode don't care.\r
479	//\r
480	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_IO_SEL, PlatformCfioDataPtr->Io_Sel_SS);\r
481	\r
482	//\r
483	// GPIO Triger Positive Edge Enable Register.\r
484	//\r
485	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TPE, PlatformCfioDataPtr->TPE_SS);\r
486	\r
487	//\r
488	// GPIO Trigger Negative Edge Enable Register.\r
489	//\r
490	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TNE, PlatformCfioDataPtr->TNE_SS);\r
491	\r
492	//\r
493	// GPIO Trigger Status.\r
494	//\r
495	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TS, PlatformCfioDataPtr->TS_SS);\r
496	\r
497	//\r
498	// GPIO Wake Enable.\r
499	//\r
500	IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_WAKE_EN, PlatformCfioDataPtr->WE_SS);\r
501	\r
502	//\r
503	// Config SC/NC/SUS GPIO Pins\r
504	//\r
505	switch (PlatformInfoHob->BoardId) {\r
506	case BOARD_ID_MINNOW2:\r
8b7a63e7	507	case BOARD_ID_MINNOW2_TURBOT:\r
3cbfba02 DW	508	DEBUG ((EFI_D_INFO, "Start to config Minnow2 GPIO pins\n"));\r
	509	InternalGpioConfig(GPIO_SCORE_OFFSET, sizeof(mMinnow2_GpioInitData_SC)/sizeof(mMinnow2_GpioInitData_SC[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_SC);\r
	510	InternalGpioConfig(GPIO_NCORE_OFFSET, sizeof(mMinnow2_GpioInitData_NC)/sizeof(mMinnow2_GpioInitData_NC[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_NC);\r
	511	InternalGpioConfig(GPIO_SSUS_OFFSET, sizeof(mMinnow2_GpioInitData_SUS)/sizeof(mMinnow2_GpioInitData_SUS[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_SUS);\r
	512	break;\r
	513	default:\r
	514	\r
	515	break;\r
	516	}\r
	517	\r
	518	//\r
	519	// configure the CFIO Pnp settings\r
	520	//\r
	521	if (PlatformInfoHob->CfioEnabled) {\r
8b7a63e7	522	if (PlatformInfoHob->BoardId == BOARD_ID_MINNOW2 \|\| PlatformInfoHob->BoardId == BOARD_ID_MINNOW2_TURBOT){\r
3cbfba02 DW	523	InternalGpioConfig(GPIO_SCORE_OFFSET, sizeof(mNB_BB_FAB3_GpioInitData_SC_TRI)/sizeof(mNB_BB_FAB3_GpioInitData_SC_TRI[0]), (GPIO_CONF_PAD_INIT *) (UINTN)PlatformInfoHob->PlatformGpioData_SC_TRI);\r
	524	}\r
	525	}\r
	526	#else\r
	527	DEBUG ((EFI_D_INFO, "Skip MultiPlatformGpioProgram()...for SIMICS or HYB model\n"));\r
	528	#endif\r
	529	return EFI_SUCCESS;\r
	530	}\r
	531	\r