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1 | /** @file\r |
2 | Multiplatform initialization.\r | |
3 | \r | |
4 | Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
5 | \r\r | |
6 | This program and the accompanying materials are licensed and made available under\r\r | |
7 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
8 | The full text of the license may be found at \r\r | |
9 | http://opensource.org/licenses/bsd-license.php. \r\r | |
10 | \r\r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
13 | \r\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #include <MultiPlatformLib.h>\r | |
18 | \r | |
19 | /**\r | |
20 | Platform Type detection. Because the PEI globle variable\r | |
21 | is in the flash, it could not change directly.So use\r | |
22 | 2 PPIs to distinguish the platform type.\r | |
23 | \r | |
24 | @param FfsHeader Pointer to Firmware File System file header.\r | |
25 | @param PeiServices General purpose services available to every PEIM.\r | |
26 | \r | |
27 | @retval EFI_SUCCESS Memory initialization completed successfully.\r | |
28 | @retval Others All other error conditions encountered result in an ASSERT.\r | |
29 | \r | |
30 | **/\r | |
31 | EFI_STATUS\r | |
32 | MultiPlatformInfoInit (\r | |
33 | IN CONST EFI_PEI_SERVICES **PeiServices,\r | |
34 | IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob\r | |
35 | )\r | |
36 | {\r | |
b3a4a852 | 37 | UINT32 PcieLength;\r |
3cbfba02 DW |
38 | \r |
39 | \r | |
40 | PlatformInfoHob->IohSku = MmPci16(0, MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET);\r | |
41 | \r | |
42 | PlatformInfoHob->IohRevision = MmPci8(0, MC_BUS, MC_DEV, MC_FUN, PCI_REVISION_ID_OFFSET);\r | |
43 | \r | |
44 | //\r | |
45 | // Update ICH Type\r | |
46 | //\r | |
47 | //\r | |
48 | // Device ID\r | |
49 | //\r | |
50 | PlatformInfoHob->IchSku = PchLpcPciCfg16(PCI_DEVICE_ID_OFFSET);\r | |
51 | \r | |
52 | PlatformInfoHob->IchRevision = PchLpcPciCfg8(PCI_REVISION_ID_OFFSET);\r | |
53 | \r | |
b3a4a852 GL |
54 | //\r |
55 | //64MB\r | |
56 | //\r | |
57 | PcieLength = 0x04000000;\r | |
3cbfba02 DW |
58 | \r |
59 | //\r | |
60 | // Don't support BASE above 4GB currently.\r | |
61 | //\r | |
62 | PlatformInfoHob->PciData.PciExpressSize = PcieLength;\r | |
63 | PlatformInfoHob->PciData.PciExpressBase = PcdGet64 (PcdPciExpressBaseAddress);\r | |
64 | \r | |
65 | PlatformInfoHob->PciData.PciResourceMem32Base = (UINT32) (PlatformInfoHob->PciData.PciExpressBase - RES_MEM32_MIN_LEN);\r | |
66 | PlatformInfoHob->PciData.PciResourceMem32Limit = (UINT32) (PlatformInfoHob->PciData.PciExpressBase -1);\r | |
67 | \r | |
68 | PlatformInfoHob->PciData.PciResourceMem64Base = RES_MEM64_36_BASE;\r | |
69 | PlatformInfoHob->PciData.PciResourceMem64Limit = RES_MEM64_36_LIMIT;\r | |
70 | PlatformInfoHob->CpuData.CpuAddressWidth = 36;\r | |
71 | \r | |
72 | PlatformInfoHob->MemData.MemMir0 = PlatformInfoHob->PciData.PciResourceMem64Base;\r | |
73 | PlatformInfoHob->MemData.MemMir1 = PlatformInfoHob->PciData.PciResourceMem64Limit + 1;\r | |
74 | \r | |
75 | PlatformInfoHob->PciData.PciResourceMinSecBus = 1; //can be changed by SystemConfiguration->PciMinSecondaryBus;\r | |
76 | \r | |
77 | //\r | |
78 | // Set MemMaxTolm to the lowest address between PCIe Base and PCI32 Base.\r | |
79 | //\r | |
80 | if (PlatformInfoHob->PciData.PciExpressBase > PlatformInfoHob->PciData.PciResourceMem32Base ) {\r | |
81 | PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciResourceMem32Base;\r | |
82 | } else {\r | |
83 | PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciExpressBase;\r | |
84 | }\r | |
85 | PlatformInfoHob->MemData.MemTolm = PlatformInfoHob->MemData.MemMaxTolm;\r | |
86 | \r | |
87 | //\r | |
88 | // Platform PCI MMIO Size in unit of 1MB.\r | |
89 | //\r | |
90 | PlatformInfoHob->MemData.MmioSize = 0x1000 - (UINT16)(PlatformInfoHob->MemData.MemMaxTolm >> 20);\r | |
91 | \r | |
92 | //\r | |
93 | // Enable ICH IOAPIC\r | |
94 | //\r | |
95 | PlatformInfoHob->SysData.SysIoApicEnable = ICH_IOAPIC;\r | |
96 | \r | |
b3a4a852 GL |
97 | DEBUG ((EFI_D_ERROR, "PlatformFlavor is %x (%x=tablet,%x=mobile,%x=desktop)\n",\r |
98 | PlatformInfoHob->PlatformFlavor,\r | |
99 | FlavorTablet,\r | |
100 | FlavorMobile,\r | |
101 | FlavorDesktop));\r | |
3cbfba02 | 102 | \r |
b3a4a852 GL |
103 | //\r |
104 | // Get Platform Info and fill the Hob.\r | |
105 | //\r | |
106 | PlatformInfoHob->RevisonId = PLATFORM_INFO_HOB_REVISION;\r | |
3cbfba02 | 107 | \r |
b3a4a852 GL |
108 | //\r |
109 | // Get GPIO table\r | |
110 | //\r | |
111 | MultiPlatformGpioTableInit (PeiServices, PlatformInfoHob);\r | |
3cbfba02 | 112 | \r |
b3a4a852 GL |
113 | //\r |
114 | // Program GPIO\r | |
115 | //\r | |
116 | MultiPlatformGpioProgram (PeiServices, PlatformInfoHob);\r | |
3cbfba02 | 117 | \r |
b3a4a852 GL |
118 | //\r |
119 | // Update OemId\r | |
120 | //\r | |
121 | InitializeBoardOemId (PeiServices, PlatformInfoHob);\r | |
122 | InitializeBoardSsidSvid (PeiServices, PlatformInfoHob);\r | |
3cbfba02 | 123 | \r |
b3a4a852 | 124 | return EFI_SUCCESS;\r |
3cbfba02 | 125 | }\r |