projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /**\r |
| 2 | \r | |
| 3 | Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r | |
| 4 | \r\r | |
| 9dc8036d MK |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 6 | \r | |
| 3cbfba02 DW |
7 | \r\r |
| 8 | \r | |
| 9 | @file\r | |
| 10 | PchPlatformLib.c\r | |
| 11 | \r | |
| 12 | @brief\r | |
| 13 | PCH Platform Lib implementation.\r | |
| 14 | \r | |
| 15 | **/\r | |
| 16 | \r | |
| 17 | #include "PchPlatformLibrary.h"\r | |
| 18 | \r | |
| 19 | //\r | |
| 20 | // Silicon Steppings\r | |
| 21 | //\r | |
| 22 | /**\r | |
| 23 | Return Pch stepping type\r | |
| 24 | \r | |
| 25 | @param[in] None\r | |
| 26 | \r | |
| 27 | @retval PCH_STEPPING Pch stepping type\r | |
| 28 | \r | |
| 29 | **/\r | |
| 30 | PCH_STEPPING\r | |
| 31 | EFIAPI\r | |
| 32 | PchStepping (\r | |
| 33 | VOID\r | |
| 34 | )\r | |
| 35 | {\r | |
| 36 | UINT8 RevId;\r | |
| 37 | \r | |
| 38 | RevId = MmioRead8 (\r | |
| 39 | MmPciAddress (0,\r | |
| 40 | DEFAULT_PCI_BUS_NUMBER_PCH,\r | |
| 41 | PCI_DEVICE_NUMBER_PCH_LPC,\r | |
| 42 | PCI_FUNCTION_NUMBER_PCH_LPC,\r | |
| 43 | R_PCH_LPC_RID_CC)\r | |
| 44 | );\r | |
| 45 | \r | |
| 46 | switch (RevId) {\r | |
| 47 | case V_PCH_LPC_RID_0:\r | |
| 48 | case V_PCH_LPC_RID_1:\r | |
| 49 | return PchA0;\r | |
| 50 | break;\r | |
| 51 | \r | |
| 52 | case V_PCH_LPC_RID_2:\r | |
| 53 | case V_PCH_LPC_RID_3:\r | |
| 54 | return PchA1;\r | |
| 55 | break;\r | |
| 56 | \r | |
| 57 | case V_PCH_LPC_RID_4:\r | |
| 58 | case V_PCH_LPC_RID_5:\r | |
| 59 | return PchB0;\r | |
| 60 | break;\r | |
| 61 | \r | |
| 62 | case V_PCH_LPC_RID_6:\r | |
| 63 | case V_PCH_LPC_RID_7:\r | |
| 64 | return PchB1;\r | |
| 65 | break;\r | |
| 66 | \r | |
| 67 | case V_PCH_LPC_RID_8:\r | |
| 68 | case V_PCH_LPC_RID_9:\r | |
| 69 | return PchB2;\r | |
| 70 | break;\r | |
| 71 | \r | |
| 72 | case V_PCH_LPC_RID_A:\r | |
| 73 | case V_PCH_LPC_RID_B:\r | |
| 74 | return PchB3;\r | |
| 75 | break;\r | |
| 76 | \r | |
| 77 | case V_PCH_LPC_RID_C:\r | |
| 78 | case V_PCH_LPC_RID_D:\r | |
| 79 | return PchC0;\r | |
| 80 | break;\r | |
| 8268a01d SL |
81 | \r |
| 82 | case V_PCH_LPC_RID_E:\r | |
| 83 | case V_PCH_LPC_RID_F:\r | |
| 84 | return PchD0;\r | |
| 85 | break;\r | |
| 86 | \r | |
| 3cbfba02 DW |
87 | default:\r |
| 88 | return PchSteppingMax;\r | |
| 89 | break;\r | |
| 90 | \r | |
| 91 | }\r | |
| 92 | }\r | |
| 93 | \r | |
| 94 | /**\r | |
| 95 | Determine if PCH is supported\r | |
| 96 | \r | |
| 97 | @param[in] None\r | |
| 98 | \r | |
| 99 | @retval TRUE PCH is supported\r | |
| 100 | @retval FALSE PCH is not supported\r | |
| 101 | \r | |
| 102 | **/\r | |
| 103 | BOOLEAN\r | |
| 104 | IsPchSupported (\r | |
| 105 | VOID\r | |
| 106 | )\r | |
| 107 | {\r | |
| 108 | UINT32 Identifiers;\r | |
| 109 | UINT16 PcuVendorId;\r | |
| 110 | UINT16 PcuDeviceId;\r | |
| 111 | \r | |
| 112 | Identifiers = MmioRead32 (\r | |
| 113 | MmPciAddress (0,\r | |
| 114 | DEFAULT_PCI_BUS_NUMBER_PCH,\r | |
| 115 | PCI_DEVICE_NUMBER_PCH_LPC,\r | |
| 116 | PCI_FUNCTION_NUMBER_PCH_LPC,\r | |
| 117 | R_PCH_LPC_REG_ID)\r | |
| 118 | );\r | |
| 119 | \r | |
| 120 | PcuDeviceId = (UINT16) ((Identifiers & B_PCH_LPC_DEVICE_ID) >> 16);\r | |
| 121 | PcuVendorId = (UINT16) (Identifiers & B_PCH_LPC_VENDOR_ID);\r | |
| 122 | \r | |
| 123 | //\r | |
| 124 | // Verify that this is a supported chipset\r | |
| 125 | //\r | |
| 126 | if (PcuVendorId != (UINT16) V_PCH_LPC_VENDOR_ID || !IS_PCH_VLV_LPC_DEVICE_ID (PcuDeviceId)) {\r | |
| 127 | DEBUG ((EFI_D_ERROR, "VLV SC code doesn't support the PcuDeviceId: 0x%04x!\n", PcuDeviceId));\r | |
| 128 | return FALSE;\r | |
| 129 | }\r | |
| 130 | return TRUE;\r | |
| 131 | }\r |