projects / mirror_edk2.git / blame
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|---|---|---|
| 3cbfba02 DW |
1 | /** @file\r |
| 2 | Header file of Serial port hardware definition.\r | |
| 3 | \r | |
| 4 | Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
| 5 | \r\r | |
| 6 | This program and the accompanying materials are licensed and made available under\r\r | |
| 7 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
| 8 | The full text of the license may be found at \r\r | |
| 9 | http://opensource.org/licenses/bsd-license.php. \r\r | |
| 10 | \r\r | |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
| 13 | \r\r | |
| 14 | This software and associated documentation\r | |
| 15 | (if any) is furnished under a license and may only be used or\r | |
| 16 | copied in accordance with the terms of the license. Except as\r | |
| 17 | permitted by such license, no part of this software or\r | |
| 18 | documentation may be reproduced, stored in a retrieval system, or\r | |
| 19 | transmitted in any form or by any means without the express written\r | |
| 20 | consent of Intel Corporation.\r | |
| 21 | \r | |
| 22 | Module Name: PlatformSerialPortLib.h\r | |
| 23 | \r | |
| 24 | **/\r | |
| 25 | \r | |
| 26 | #ifndef __PLATFORM_SERIAL_PORT_LIB_H_\r | |
| 27 | #define __PLATFORM_SERIAL_PORT_LIB_H_\r | |
| 28 | \r | |
| 29 | #include <Base.h>\r | |
| 30 | #include <Library/BaseLib.h>\r | |
| 31 | #include <Library/IoLib.h>\r | |
| 32 | #include <Library/PcdLib.h>\r | |
| 33 | #include <Library/SerialPortLib.h>\r | |
| 34 | \r | |
| 35 | //\r | |
| 36 | // UART Register Offsets\r | |
| 37 | //\r | |
| 38 | #define BAUD_LOW_OFFSET 0x00\r | |
| 39 | #define BAUD_HIGH_OFFSET 0x01\r | |
| 40 | #define IER_OFFSET 0x01\r | |
| 41 | #define LCR_SHADOW_OFFSET 0x01\r | |
| 42 | #define FCR_SHADOW_OFFSET 0x02\r | |
| 43 | #define IR_CONTROL_OFFSET 0x02\r | |
| 44 | #define FCR_OFFSET 0x02\r | |
| 45 | #define EIR_OFFSET 0x02\r | |
| 46 | #define BSR_OFFSET 0x03\r | |
| 47 | #define LCR_OFFSET 0x03\r | |
| 48 | #define MCR_OFFSET 0x04\r | |
| 49 | #define LSR_OFFSET 0x05\r | |
| 50 | #define MSR_OFFSET 0x06\r | |
| 51 | \r | |
| 52 | //\r | |
| 53 | // UART Register Bit Defines\r | |
| 54 | //\r | |
| 55 | #define LSR_TXRDY 0x20\r | |
| 56 | #define LSR_RXDA 0x01\r | |
| 57 | #define DLAB 0x01\r | |
| 58 | \r | |
| 59 | #define UART_DATA 8\r | |
| 60 | #define UART_STOP 1\r | |
| 61 | #define UART_PARITY 0\r | |
| 62 | #define UART_BREAK_SET 0\r | |
| 63 | \r | |
| 64 | VOID\r | |
| 65 | InitializeSio (\r | |
| 66 | VOID\r | |
| 67 | );\r | |
| 68 | \r | |
| 69 | #endif\r |