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Add TpmInitializationDonePpi to TPM PEI module.
[mirror_edk2.git] / Vlv2TbltDevicePkg / PlatformDxe / Platform.c
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3cbfba02
DW		 1/** @file\r
2\r
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
4 \r\r
5 This program and the accompanying materials are licensed and made available under\r\r
6 the terms and conditions of the BSD License that accompanies this distribution. \r\r
7 The full text of the license may be found at \r\r
8 http://opensource.org/licenses/bsd-license.php. \r\r
9 \r\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r
12 \r\r
13\r
14Module Name:\r
15\r
16\r
17 Platform.c\r
18\r
19Abstract:\r
20\r
21 Platform Initialization Driver.\r
22\r
23\r
24--*/\r
25\r
26#include "PlatformDxe.h"\r
27#include "Platform.h"\r
28#include "PchCommonDefinitions.h"\r
29#include <Protocol/UsbPolicy.h>\r
30#include <Protocol/PchPlatformPolicy.h>\r
31#include <Protocol/TpmMp.h>\r
32#include <Protocol/CpuIo2.h>\r
33#include <Library/S3BootScriptLib.h>\r
34#include <Guid/PciLanInfo.h>\r
35#include <Guid/ItkData.h>\r
36#include <Library/PciLib.h>\r
37#include <PlatformBootMode.h>\r
38#include <Guid/EventGroup.h>\r
39#include <Guid/Vlv2Variable.h>\r
40#include <Protocol/GlobalNvsArea.h>\r
41#include <Protocol/IgdOpRegion.h>\r
42#include <Library/PcdLib.h>\r
43\r
44//\r
45// VLV2 GPIO GROUP OFFSET\r
46//\r
47#define GPIO_SCORE_OFFSET 0x0000\r
48#define GPIO_NCORE_OFFSET 0x1000\r
49#define GPIO_SSUS_OFFSET 0x2000\r
50\r
51typedef struct {\r
52 UINT32 offset;\r
53 UINT32 val;\r
54} CFIO_PNP_INIT;\r
55\r
56GPIO_CONF_PAD_INIT mTB_BL_GpioInitData_SC_TRI_Exit_boot_Service[] =\r
57{\r
58// Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset\r
59 GPIO_INIT_ITEM("LPC_CLKOUT0 GPIOC_47 " ,TRISTS ,NA ,F0 , , ,NONE ,0x47),\r
60 GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,TRISTS ,NA ,F0 , , ,NONE ,0x41),\r
61};\r
62\r
63\r
64EFI_GUID mSystemHiiExportDatabase = EFI_HII_EXPORT_DATABASE_GUID;\r
65EFI_GUID mPlatformDriverGuid = EFI_PLATFORM_DRIVER_GUID;\r
66SYSTEM_CONFIGURATION mSystemConfiguration;\r
67SYSTEM_PASSWORDS mSystemPassword;\r
68EFI_HANDLE mImageHandle;\r
69BOOLEAN mMfgMode = FALSE;\r
70VOID *mDxePlatformStringPack;\r
71UINT32 mPlatformBootMode = PLATFORM_NORMAL_MODE;\r
72extern CHAR16 gItkDataVarName[];\r
73\r
74\r
75EFI_PLATFORM_INFO_HOB mPlatformInfo;\r
76EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;\r
77EFI_EVENT mReadyToBootEvent;\r
78\r
79UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;\r
80UINT8 mNumberSmbusAddress = sizeof( mSmbusRsvdAddresses ) / sizeof( mSmbusRsvdAddresses[0] );\r
81UINT32 mSubsystemVidDid;\r
82UINT32 mSubsystemAudioVidDid;\r
83\r
84UINTN mPciLanCount = 0;\r
85VOID *mPciLanInfo = NULL;\r
86UINTN SpiBase;\r
87\r
88static EFI_SPEAKER_IF_PROTOCOL mSpeakerInterface = {\r
89 ProgramToneFrequency,\r
90 GenerateBeepTone\r
91};\r
92\r
93EFI_USB_POLICY_PROTOCOL mUsbPolicyData = {0};\r
94\r
95\r
96CFIO_PNP_INIT mTB_BL_GpioInitData_SC_TRI_S0ix_Exit_boot_Service[] =\r
97{\r
98 {0x410 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pconf0\r
99 {0x470 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pconf0\r
100 {0x560 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pconf0\r
101 {0x450 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pconf0\r
102 {0x480 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pconf0\r
103 {0x420 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pconf0\r
104 {0x430 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pconf0\r
105 {0x440 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pconf0\r
106 {0x460 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pconf0\r
107 {0x418 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pad_val\r
108 {0x478 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pad_val\r
109 {0x568 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pad_val\r
110 {0x458 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pad_val\r
111 {0x488 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pad_val\r
112 {0x428 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pad_val\r
113 {0x438 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pad_val\r
114 {0x448 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pad_val\r
115 {0x468 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pad_val\r
116};\r
117\r
118VOID\r
119EfiOrMem (\r
120 IN VOID *Destination,\r
121 IN VOID *Source,\r
122 IN UINTN Length\r
123 );\r
124\r
125#if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)\r
126STATIC\r
127VOID\r
128InitFirmwareId();\r
129#endif\r
130\r
131\r
132VOID\r
133InitializeClockRouting(\r
134 );\r
135\r
136VOID\r
137InitializeSlotInfo (\r
138 );\r
139\r
140#if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0\r
141VOID\r
142InitializeSensorInfoVariable (\r
143 );\r
144#endif\r
145\r
146VOID\r
147InitTcoReset (\r
148 );\r
149\r
150VOID\r
151InitExI ();\r
152\r
153VOID\r
154InitItk();\r
155\r
156VOID\r
157InitPlatformBootMode();\r
158\r
159VOID\r
160InitMfgAndConfigModeStateVar();\r
161\r
162VOID\r
163InitPchPlatformPolicy (\r
164 IN EFI_PLATFORM_INFO_HOB *PlatformInfo\r
165 );\r
166\r
167VOID\r
168InitVlvPlatformPolicy (\r
169 );\r
170\r
171VOID\r
172InitSioPlatformPolicy(\r
173 );\r
174\r
175VOID\r
176PchInitBeforeBoot(\r
177 );\r
178\r
179VOID\r
180UpdateDVMTSetup(\r
181 );\r
182\r
183VOID\r
184InitPlatformUsbPolicy (\r
185 VOID\r
186 );\r
187\r
188VOID\r
189InitRC6Policy(\r
190 VOID\r
191 );\r
192\r
193\r
194VOID\r
195TristateLpcGpioConfig (\r
196 IN UINT32 Gpio_Mmio_Offset,\r
197 IN UINT32 Gpio_Pin_Num,\r
198 GPIO_CONF_PAD_INIT* Gpio_Conf_Data\r
199 )\r
200\r
201{\r
202 UINT32 index;\r
203 UINT32 mmio_conf0;\r
204 UINT32 mmio_padval;\r
205 PAD_CONF0 conf0_val;\r
206 PAD_VAL pad_val;\r
207\r
208 //\r
209 // GPIO WELL -- Memory base registers\r
210 //\r
211\r
212 //\r
213 // A0 BIOS Spec doesn't mention it although X0 does. comment out now.\r
214 // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900\r
215 //\r
216\r
217 for(index=0; index < Gpio_Pin_Num; index++)\r
218 {\r
219 //\r
220 // Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.\r
221 //\r
222 mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;\r
223 mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;\r
224\r
225#ifdef EFI_DEBUG\r
226 DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));\r
227\r
228#endif\r
229 DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",\r
230 Gpio_Conf_Data[index].usage,\r
231 Gpio_Conf_Data[index].func,\r
232 Gpio_Conf_Data[index].int_type,\r
233 Gpio_Conf_Data[index].pull,\r
234 mmio_conf0));\r
235\r
236 //\r
237 // Step 1: PadVal Programming\r
238 //\r
239 pad_val.dw = MmioRead32(mmio_padval);\r
240\r
241 //\r
242 // Config PAD_VAL only for GPIO (Non-Native) Pin\r
243 //\r
244 if(Native != Gpio_Conf_Data[index].usage)\r
245 {\r
246 pad_val.dw &= ~0x6; // Clear bits 1:2\r
247 pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal\r
248\r
249 //\r
250 // set GPO default value\r
251 //\r
252 if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)\r
253 {\r
254 pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;\r
255 }\r
256 }\r
257\r
258\r
259 DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));\r
260\r
261 MmioWrite32(mmio_padval, pad_val.dw);\r
262\r
263 //\r
264 // Step 2: CONF0 Programming\r
265 // Read GPIO default CONF0 value, which is assumed to be default value after reset.\r
266 //\r
267 conf0_val.dw = MmioRead32(mmio_conf0);\r
268\r
269 //\r
270 // Set Function #\r
271 //\r
272 conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;\r
273\r
274 if(GPO == Gpio_Conf_Data[index].usage)\r
275 {\r
276 //\r
277 // If used as GPO, then internal pull need to be disabled\r
278 //\r
279 conf0_val.r.Pull_assign = 0; // Non-pull\r
280 }\r
281 else\r
282 {\r
283 //\r
284 // Set PullUp / PullDown\r
285 //\r
286 if(P_20K_H == Gpio_Conf_Data[index].pull)\r
287 {\r
288 conf0_val.r.Pull_assign = 0x1; // PullUp\r
289 conf0_val.r.Pull_strength = 0x2;// 20K\r
290 }\r
291 else if(P_20K_L == Gpio_Conf_Data[index].pull)\r
292 {\r
293 conf0_val.r.Pull_assign = 0x2; // PullDown\r
294 conf0_val.r.Pull_strength = 0x2;// 20K\r
295 }\r
296 else if(P_NONE == Gpio_Conf_Data[index].pull)\r
297 {\r
298 conf0_val.r.Pull_assign = 0; // Non-pull\r
299 }\r
300 else\r
301 {\r
302 ASSERT(FALSE); // Invalid value\r
303 }\r
304 }\r
305\r
306 //\r
307 // Set INT Trigger Type\r
308 //\r
309 conf0_val.dw &= ~0x0f000000; // Clear bits 27:24\r
310\r
311 //\r
312 // Set INT Trigger Type\r
313 //\r
314 if(TRIG_ == Gpio_Conf_Data[index].int_type)\r
315 {\r
316 //\r
317 // Interrupt not capable, clear bits 27:24\r
318 //\r
319 }\r
320 else\r
321 {\r
322 conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;\r
323 }\r
324\r
325 DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));\r
326\r
327 //\r
328 // Write back the targeted GPIO config value according to platform (board) GPIO setting\r
329 //\r
330 MmioWrite32 (mmio_conf0, conf0_val.dw);\r
331 }\r
332\r
333 // A0 BIOS Spec doesn't mention it although X0 does. comment out now.\r
334 // GPIO SCORE write 0x01001002 to IOBASE + 0x0900\r
335 //\r
336}\r
337\r
338VOID\r
339EFIAPI\r
340SpiBiosProtectionFunction(\r
341 EFI_EVENT Event,\r
342 VOID *Context\r
343 )\r
344{\r
345\r
346 UINTN mPciD31F0RegBase;\r
347 UINTN BiosFlaLower = 0;\r
348 UINTN BiosFlaLimit = 0x7fffff;\r
349\r
350 BiosFlaLower = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);\r
351\r
352\r
353 mPciD31F0RegBase = MmPciAddress (0,\r
354 DEFAULT_PCI_BUS_NUMBER_PCH,\r
355 PCI_DEVICE_NUMBER_PCH_LPC,\r
356 PCI_FUNCTION_NUMBER_PCH_LPC,\r
357 0\r
358 );\r
359 SpiBase = MmioRead32(mPciD31F0RegBase + R_PCH_LPC_SPI_BASE) & B_PCH_LPC_SPI_BASE_BAR;\r
360\r
361 //\r
362 //Set SMM_BWP, WPD and LE bit\r
363 //\r
364 MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_SMM_BWP);\r
365 MmioAnd32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8)(~B_PCH_SPI_BCR_BIOSWE));\r
366 MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_BLE);\r
367\r
368 //\r
369 //First check if FLOCKDN or PR0FLOCKDN is set. No action if either of them set already.\r
370 //\r
371 if( (MmioRead16(SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) != 0 ||\r
372 (MmioRead32(SpiBase + R_PCH_SPI_IND_LOCK)& B_PCH_SPI_IND_LOCK_PR0) != 0) {\r
373 //\r
374 //Already locked. we could take no action here\r
375 //\r
376 DEBUG((EFI_D_INFO, "PR0 already locked down. Stop configuring PR0.\n"));\r
377 return;\r
378 }\r
379\r
380 //\r
381 //Set PR0\r
382 //\r
383 MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),\r
384 B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\\r
385 (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit>>12)<<16));\r
386\r
387 //\r
388 //Lock down PR0\r
389 //\r
390 MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));\r
391\r
392 //\r
393 // Verify if it's really locked.\r
394 //\r
395 if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {\r
396 DEBUG((EFI_D_ERROR, "Failed to lock down PR0.\n"));\r
397 }\r
398\r
399 return;\r
400\r
401}\r
402\r
403VOID\r
404EFIAPI\r
405InitPciDevPME (\r
406 EFI_EVENT Event,\r
407 VOID *Context\r
408 )\r
409{\r
410 UINTN VarSize;\r
411 EFI_STATUS Status;\r
412\r
413 VarSize = sizeof(SYSTEM_CONFIGURATION);\r
414 Status = gRT->GetVariable(\r
415 NORMAL_SETUP_NAME,\r
416 &gEfiNormalSetupGuid,\r
417 NULL,\r
418 &VarSize,\r
419 &mSystemConfiguration\r
420 );\r
421\r
422 //\r
423 //Program HDA PME_EN\r
424 //\r
425 PchAzaliaPciCfg32Or (R_PCH_HDA_PCS, B_PCH_HDA_PCS_PMEE);\r
426\r
427 //\r
428 //Program SATA PME_EN\r
429 //\r
430 PchSataPciCfg32Or (R_PCH_SATA_PMCS, B_PCH_SATA_PMCS_PMEE);\r
431\r
432 DEBUG ((EFI_D_INFO, "InitPciDevPME mSystemConfiguration.EhciPllCfgEnable = 0x%x \n",mSystemConfiguration.EhciPllCfgEnable));\r
433 if (mSystemConfiguration.EhciPllCfgEnable != 1) {\r
434 //\r
435 //Program EHCI PME_EN\r
436 //\r
437 PchMmPci32Or (\r
438 0,\r
439 0,\r
440 PCI_DEVICE_NUMBER_PCH_USB,\r
441 PCI_FUNCTION_NUMBER_PCH_EHCI,\r
442 R_PCH_EHCI_PWR_CNTL_STS,\r
443 B_PCH_EHCI_PWR_CNTL_STS_PME_EN\r
444 );\r
445 }\r
446 {\r
447 UINTN EhciPciMmBase;\r
448 UINT32 Buffer32 = 0;\r
449\r
450 EhciPciMmBase = MmPciAddress (0,\r
451 0,\r
452 PCI_DEVICE_NUMBER_PCH_USB,\r
453 PCI_FUNCTION_NUMBER_PCH_EHCI,\r
454 0\r
455 );\r
456 DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() EhciPciMmBase = 0x%x \n",EhciPciMmBase));\r
457 Buffer32 = MmioRead32(EhciPciMmBase + R_PCH_EHCI_PWR_CNTL_STS);\r
458 DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() R_PCH_EHCI_PWR_CNTL_STS = 0x%x \n",Buffer32));\r
459 }\r
460}\r
461\r
462#if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY\r
463\r
464#endif\r
465\r
466\r
467EFI_STATUS\r
468EFIAPI\r
469TristateLpcGpioS0i3Config (\r
470 UINT32 Gpio_Mmio_Offset,\r
471 UINT32 Gpio_Pin_Num,\r
472 CFIO_PNP_INIT* Gpio_Conf_Data\r
473 )\r
474{\r
475\r
476 UINT32 index;\r
477 UINT32 mmio_reg;\r
478 UINT32 mmio_val;\r
479\r
480 DEBUG ((DEBUG_INFO, "TristateLpcGpioS0i3Config\n"));\r
481\r
482 for(index=0; index < Gpio_Pin_Num; index++)\r
483 {\r
484 mmio_reg = IO_BASE_ADDRESS + Gpio_Mmio_Offset + Gpio_Conf_Data[index].offset;\r
485\r
486 MmioWrite32(mmio_reg, Gpio_Conf_Data[index].val);\r
487 mmio_val = 0;\r
488 mmio_val = MmioRead32(mmio_reg);\r
489\r
490 DEBUG ((EFI_D_INFO, "Set MMIO=0x%08x PAD_VAL = 0x%08x,\n", mmio_reg, mmio_val));\r
491 }\r
492\r
493 return EFI_SUCCESS;\r
494}\r
495\r
496\r
497EFI_BOOT_SCRIPT_SAVE_PROTOCOL *mBootScriptSave;\r
498\r
499/**\r
500 Event Notification during exit boot service to enabel ACPI mode\r
501\r
502 Disable SW SMI Timer, SMI from USB & Intel Specific USB 2\r
503\r
504 Clear all ACPI event status and disable all ACPI events\r
505 Disable PM sources except power button\r
506 Clear status bits\r
507\r
508 Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")\r
509\r
510 Update EC to disable SMI and enable SCI\r
511\r
512 Enable SCI\r
513\r
514 Enable PME_B0_EN in GPE0a_EN\r
515\r
516 @param Event - EFI Event Handle\r
517 @param Context - Pointer to Notify Context\r
518\r
519 @retval Nothing\r
520\r
521**/\r
522VOID\r
523EFIAPI\r
524EnableAcpiCallback (\r
525 IN EFI_EVENT Event,\r
526 IN VOID *Context\r
527 )\r
528{\r
529 UINT32 RegData32;\r
530 UINT16 Pm1Cnt;\r
531 UINT16 AcpiBase;\r
532 UINT32 Gpe0aEn;\r
533\r
534 AcpiBase = MmioRead16 (\r
535 PchPciDeviceMmBase (DEFAULT_PCI_BUS_NUMBER_PCH,\r
536 PCI_DEVICE_NUMBER_PCH_LPC,\r
537 PCI_FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_ACPI_BASE\r
538 ) & B_PCH_LPC_ACPI_BASE_BAR;\r
539\r
540 DEBUG ((EFI_D_INFO, "EnableAcpiCallback: AcpiBase = %x\n", AcpiBase));\r
541\r
542 //\r
543 // Disable SW SMI Timer, SMI from USB & Intel Specific USB 2\r
544 //\r
545 RegData32 = IoRead32(AcpiBase + R_PCH_SMI_EN);\r
546 RegData32 &= ~(B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_INTEL_USB2);\r
547 IoWrite32(AcpiBase + R_PCH_SMI_EN, RegData32);\r
548\r
549 RegData32 = IoRead32(AcpiBase + R_PCH_SMI_STS);\r
550 RegData32 |= B_PCH_SMI_STS_SWSMI_TMR;\r
551 IoWrite32(AcpiBase + R_PCH_SMI_STS, RegData32);\r
552\r
553 //\r
554 // Disable PM sources except power button\r
555 // power button is enabled only for PCAT. Disabled it on Tablet platform\r
556 //\r
557\r
558 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);\r
559 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_STS, 0xffff);\r
560\r
561 //\r
562 // Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")\r
563 // Clear Status D reg VM bit, Date of month Alarm to make Data in CMOS RAM is no longer Valid\r
564 //\r
565 IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);\r
566 IoWrite8 (PCAT_RTC_DATA_REGISTER, 0x0);\r
567\r
568 RegData32 = IoRead32(AcpiBase + R_PCH_ALT_GP_SMI_EN);\r
569 RegData32 &= ~(BIT7);\r
570 IoWrite32((AcpiBase + R_PCH_ALT_GP_SMI_EN), RegData32);\r
571\r
572 //\r
573 // Enable SCI\r
574 //\r
575 Pm1Cnt = IoRead16(AcpiBase + R_PCH_ACPI_PM1_CNT);\r
576 Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;\r
577 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);\r
578\r
579 IoWrite8(0x80, 0xA0); //SW_SMI_ACPI_ENABLE\r
580\r
581 //\r
582 // Enable PME_B0_EN in GPE0a_EN\r
583 // Caution: Enable PME_B0_EN must be placed after enabling SCI.\r
584 // Otherwise, USB PME could not be handled as SMI event since no handler is there.\r
585 //\r
586 Gpe0aEn = IoRead32 (AcpiBase + R_PCH_ACPI_GPE0a_EN);\r
587 Gpe0aEn |= B_PCH_ACPI_GPE0a_EN_PME_B0;\r
588 IoWrite32(AcpiBase + R_PCH_ACPI_GPE0a_EN, Gpe0aEn);\r
589\r
590}\r
591\r
592/**\r
593\r
594 Routine Description:\r
595\r
596 This is the standard EFI driver point for the Driver. This\r
597 driver is responsible for setting up any platform specific policy or\r
598 initialization information.\r
599\r
600 @param ImageHandle Handle for the image of this driver.\r
601 @param SystemTable Pointer to the EFI System Table.\r
602\r
603 @retval EFI_SUCCESS Policy decisions set.\r
604\r
605**/\r
606EFI_STATUS\r
607EFIAPI\r
608InitializePlatform (\r
609 IN EFI_HANDLE ImageHandle,\r
610 IN EFI_SYSTEM_TABLE *SystemTable\r
611 )\r
612{\r
613 EFI_STATUS Status;\r
614 UINTN VarSize;\r
615 EFI_HANDLE Handle = NULL;\r
616\r
617 EFI_EVENT mEfiExitBootServicesEvent;\r
618\r
619 //\r
620mImageHandle = ImageHandle;\r
621\r
622 Status = gBS->InstallProtocolInterface (\r
623 &Handle,\r
624 &gEfiSpeakerInterfaceProtocolGuid,\r
625 EFI_NATIVE_INTERFACE,\r
626 &mSpeakerInterface\r
627 );\r
628\r
629 Status = gBS->LocateProtocol (\r
630 &gEfiPciRootBridgeIoProtocolGuid,\r
631 NULL,\r
632 (VOID **) &mPciRootBridgeIo\r
633 );\r
634 ASSERT_EFI_ERROR (Status);\r
635\r
636 VarSize = sizeof(EFI_PLATFORM_INFO_HOB);\r
637 Status = gRT->GetVariable(\r
638 L"PlatformInfo",\r
639 &gEfiVlv2VariableGuid,\r
640 NULL,\r
641 &VarSize,\r
642 &mPlatformInfo\r
643 );\r
644\r
645 //\r
646 // Initialize Product Board ID variable\r
647 //\r
648 InitMfgAndConfigModeStateVar();\r
649 InitPlatformBootMode();\r
650\r
651 //\r
652 // Install Observable protocol\r
653 //\r
654 InitializeObservableProtocol();\r
655\r
656\r
657 VarSize = sizeof(SYSTEM_CONFIGURATION);\r
658 Status = gRT->GetVariable(\r
659 NORMAL_SETUP_NAME,\r
660 &gEfiNormalSetupGuid,\r
661 NULL,\r
662 &VarSize,\r
663 &mSystemConfiguration\r
664 );\r
665\r
666\r
667 Status = EfiCreateEventReadyToBootEx (\r
668 TPL_CALLBACK,\r
669 ReadyToBootFunction,\r
670 NULL,\r
671 &mReadyToBootEvent\r
672 );\r
673\r
674 //\r
675 // Create a ReadyToBoot Event to run the PME init process\r
676 //\r
677 Status = EfiCreateEventReadyToBootEx (\r
678 TPL_CALLBACK,\r
679 InitPciDevPME,\r
680 NULL,\r
681 &mReadyToBootEvent\r
682 );\r
683 //\r
684 // Create a ReadyToBoot Event to run enable PR0 and lock down\r
685 //\r
686 if(mSystemConfiguration.SpiRwProtect==1) {\r
687 Status = EfiCreateEventReadyToBootEx (\r
688 TPL_CALLBACK,\r
689 SpiBiosProtectionFunction,\r
690 NULL,\r
691 &mReadyToBootEvent\r
692 );\r
693 }\r
694\r
695 ReportStatusCodeEx (\r
696 EFI_PROGRESS_CODE,\r
697 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP1,\r
698 0,\r
699 &gEfiCallerIdGuid,\r
700 NULL,\r
701 NULL,\r
702 0\r
703 );\r
704\r
705#if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0\r
706 //\r
707 // Initialize Sensor Info variable\r
708 //\r
709 InitializeSensorInfoVariable();\r
710#endif\r
711 InitPchPlatformPolicy(&mPlatformInfo);\r
712 InitVlvPlatformPolicy();\r
713\r
714 //\r
715 // Add usb policy\r
716 //\r
717 InitPlatformUsbPolicy();\r
718 InitSioPlatformPolicy();\r
719 InitializeClockRouting();\r
720 InitializeSlotInfo();\r
721 InitTcoReset();\r
722\r
723 //\r
724 //Init ExI\r
725 //\r
726 InitExI();\r
727\r
728 ReportStatusCodeEx (\r
729 EFI_PROGRESS_CODE,\r
730 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP2,\r
731 0,\r
732 &gEfiCallerIdGuid,\r
733 NULL,\r
734 NULL,\r
735 0\r
736 );\r
737\r
738 //\r
739 // Install PCI Bus Driver Hook\r
740 //\r
741 PciBusDriverHook();\r
742\r
743 InitItk();\r
744\r
745 ReportStatusCodeEx (\r
746 EFI_PROGRESS_CODE,\r
747 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP3,\r
748 0,\r
749 &gEfiCallerIdGuid,\r
750 NULL,\r
751 NULL,\r
752 0\r
753 );\r
754\r
755\r
756 //\r
757 // Initialize Password States and Callbacks\r
758 //\r
759 PchInitBeforeBoot();\r
760\r
761#if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY\r
762\r
763#endif\r
764\r
765#if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)\r
766 //\r
767 // Re-write Firmware ID if it is changed\r
768 //\r
769 InitFirmwareId();\r
770#endif\r
771\r
772 ReportStatusCodeEx (\r
773 EFI_PROGRESS_CODE,\r
774 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP4,\r
775 0,\r
776 &gEfiCallerIdGuid,\r
777 NULL,\r
778 NULL,\r
779 0\r
780 );\r
781\r
782\r
783 Status = gBS->CreateEventEx (\r
784 EVT_NOTIFY_SIGNAL,\r
785 TPL_NOTIFY,\r
786 EnableAcpiCallback,\r
787 NULL,\r
788 &gEfiEventExitBootServicesGuid,\r
789 &mEfiExitBootServicesEvent\r
790 );\r
791\r
792\r
793//\r
794// Tristae Lpc pins at last moment\r
795//\r
796if (mSystemConfiguration.TristateLpc == 1)\r
797{\r
798}\r
799\r
800 return EFI_SUCCESS;\r
801}\r
802\r
803/**\r
804 Source Or Destination with Length bytes.\r
805\r
806 @param[in] Destination Target memory\r
807 @param[in] Source Source memory\r
808 @param[in] Length Number of bytes\r
809\r
810 @retval None\r
811\r
812**/\r
813VOID\r
814EfiOrMem (\r
815 IN VOID *Destination,\r
816 IN VOID *Source,\r
817 IN UINTN Length\r
818 )\r
819{\r
820 CHAR8 *Destination8;\r
821 CHAR8 *Source8;\r
822\r
823 if (Source < Destination) {\r
824 Destination8 = (CHAR8 *) Destination + Length - 1;\r
825 Source8 = (CHAR8 *) Source + Length - 1;\r
826 while (Length--) {\r
827 *(Destination8--) |= *(Source8--);\r
828 }\r
829 } else {\r
830 Destination8 = (CHAR8 *) Destination;\r
831 Source8 = (CHAR8 *) Source;\r
832 while (Length--) {\r
833 *(Destination8++) |= *(Source8++);\r
834 }\r
835 }\r
836}\r
837\r
838VOID\r
839PchInitBeforeBoot()\r
840{\r
841 //\r
842 // Saved SPI Opcode menu to fix EFI variable unable to write after S3 resume.\r
843 //\r
844 S3BootScriptSaveMemWrite (\r
845 EfiBootScriptWidthUint32,\r
846 (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)),\r
847 1,\r
848 (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)));\r
849\r
850 S3BootScriptSaveMemWrite (\r
851 EfiBootScriptWidthUint32,\r
852 (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)),\r
853 1,\r
854 (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)));\r
855\r
856 S3BootScriptSaveMemWrite (\r
857 EfiBootScriptWidthUint16,\r
858 (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE),\r
859 1,\r
860 (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE));\r
861\r
862 S3BootScriptSaveMemWrite (\r
863 EfiBootScriptWidthUint16,\r
864 (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP),\r
865 1,\r
866 (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP));\r
867\r
868 //\r
869 // Saved MTPMC_1 for S3 resume.\r
870 //\r
871 S3BootScriptSaveMemWrite (\r
872 EfiBootScriptWidthUint32,\r
873 (UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1),\r
874 1,\r
875 (VOID *)(UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1));\r
876 return;\r
877}\r
878\r
879VOID\r
880EFIAPI\r
881ReadyToBootFunction (\r
882 EFI_EVENT Event,\r
883 VOID *Context\r
884 )\r
885{\r
886 EFI_STATUS Status;\r
887 EFI_ISA_ACPI_PROTOCOL *IsaAcpi;\r
888 EFI_ISA_ACPI_DEVICE_ID IsaDevice;\r
889 UINTN Size;\r
890 UINT16 State;\r
891 EFI_TPM_MP_DRIVER_PROTOCOL *TpmMpDriver;\r
892 EFI_CPU_IO_PROTOCOL *CpuIo;\r
893 UINT8 Data;\r
894 UINT8 ReceiveBuffer [64];\r
895 UINT32 ReceiveBufferSize;\r
896\r
897 UINT8 TpmForceClearCommand [] = {0x00, 0xC1,\r
898 0x00, 0x00, 0x00, 0x0A,\r
899 0x00, 0x00, 0x00, 0x5D};\r
900 UINT8 TpmPhysicalPresenceCommand [] = {0x00, 0xC1,\r
901 0x00, 0x00, 0x00, 0x0C,\r
902 0x40, 0x00, 0x00, 0x0A,\r
903 0x00, 0x00};\r
904 UINT8 TpmPhysicalDisableCommand [] = {0x00, 0xC1,\r
905 0x00, 0x00, 0x00, 0x0A,\r
906 0x00, 0x00, 0x00, 0x70};\r
907 UINT8 TpmPhysicalEnableCommand [] = {0x00, 0xC1,\r
908 0x00, 0x00, 0x00, 0x0A,\r
909 0x00, 0x00, 0x00, 0x6F};\r
910 UINT8 TpmPhysicalSetDeactivatedCommand [] = {0x00, 0xC1,\r
911 0x00, 0x00, 0x00, 0x0B,\r
912 0x00, 0x00, 0x00, 0x72,\r
913 0x00};\r
914 UINT8 TpmSetOwnerInstallCommand [] = {0x00, 0xC1,\r
915 0x00, 0x00, 0x00, 0x0B,\r
916 0x00, 0x00, 0x00, 0x71,\r
917 0x00};\r
918\r
919 Size = sizeof(UINT16);\r
920 Status = gRT->GetVariable (\r
921 VAR_EQ_FLOPPY_MODE_DECIMAL_NAME,\r
922 &gEfiNormalSetupGuid,\r
923 NULL,\r
924 &Size,\r
925 &State\r
926 );\r
927\r
928 //\r
929 // Disable Floppy Controller if needed\r
930 //\r
931 Status = gBS->LocateProtocol (&gEfiIsaAcpiProtocolGuid, NULL, (VOID **) &IsaAcpi);\r
932 if (!EFI_ERROR(Status) && (State == 0x00)) {\r
933 IsaDevice.HID = EISA_PNP_ID(0x604);\r
934 IsaDevice.UID = 0;\r
935 Status = IsaAcpi->EnableDevice(IsaAcpi, &IsaDevice, FALSE);\r
936 }\r
937\r
938 //\r
939 // save LAN info to a variable\r
940 //\r
941 if (NULL != mPciLanInfo) {\r
942 gRT->SetVariable (\r
943 L"PciLanInfo",\r
944 &gEfiPciLanInfoGuid,\r
945 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,\r
946 mPciLanCount * sizeof(PCI_LAN_INFO),\r
947 mPciLanInfo\r
948 );\r
949 }\r
950\r
951 if (NULL != mPciLanInfo) {\r
952 gBS->FreePool (mPciLanInfo);\r
953 mPciLanInfo = NULL;\r
954 }\r
955 \r
956\r
957 //\r
958 // Handle ACPI OS TPM requests here\r
959 //\r
960 Status = gBS->LocateProtocol (\r
961 &gEfiCpuIoProtocolGuid,\r
962 NULL,\r
963 (VOID **)&CpuIo\r
964 );\r
965 Status = gBS->LocateProtocol (\r
966 &gEfiTpmMpDriverProtocolGuid,\r
967 NULL,\r
968 (VOID **)&TpmMpDriver\r
969 );\r
970 if (!EFI_ERROR (Status))\r
971 {\r
972 Data = ReadCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST);\r
973\r
974 //\r
975 // Clear pending ACPI TPM request indicator\r
976 //\r
977 WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0x00);\r
978 if (Data != 0)\r
979 {\r
980 WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, Data);\r
981\r
982 //\r
983 // Assert Physical Presence for these commands\r
984 //\r
985 TpmPhysicalPresenceCommand [11] = 0x20;\r
986 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
987 Status = TpmMpDriver->Transmit (\r
988 TpmMpDriver, TpmPhysicalPresenceCommand,\r
989 sizeof (TpmPhysicalPresenceCommand),\r
990 ReceiveBuffer, &ReceiveBufferSize\r
991 );\r
992 //\r
993 // PF PhysicalPresence = TRUE\r
994 //\r
995 TpmPhysicalPresenceCommand [11] = 0x08;\r
996 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
997 Status = TpmMpDriver->Transmit (\r
998 TpmMpDriver, TpmPhysicalPresenceCommand,\r
999 sizeof (TpmPhysicalPresenceCommand),\r
1000 ReceiveBuffer,\r
1001 &ReceiveBufferSize\r
1002 );\r
1003 if (Data == 0x01)\r
1004 {\r
1005 //\r
1006 // TPM_PhysicalEnable\r
1007 //\r
1008 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1009 Status = TpmMpDriver->Transmit (\r
1010 TpmMpDriver, TpmPhysicalEnableCommand,\r
1011 sizeof (TpmPhysicalEnableCommand),\r
1012 ReceiveBuffer, &ReceiveBufferSize\r
1013 );\r
1014 }\r
1015 if (Data == 0x02)\r
1016 {\r
1017 //\r
1018 // TPM_PhysicalDisable\r
1019 //\r
1020 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1021 Status = TpmMpDriver->Transmit (\r
1022 TpmMpDriver, TpmPhysicalDisableCommand,\r
1023 sizeof (TpmPhysicalDisableCommand),\r
1024 ReceiveBuffer,\r
1025 &ReceiveBufferSize\r
1026 );\r
1027 }\r
1028 if (Data == 0x03)\r
1029 {\r
1030 //\r
1031 // TPM_PhysicalSetDeactivated=FALSE\r
1032 //\r
1033 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1034 TpmPhysicalSetDeactivatedCommand [10] = 0x00;\r
1035 Status = TpmMpDriver->Transmit (\r
1036 TpmMpDriver,\r
1037 TpmPhysicalSetDeactivatedCommand,\r
1038 sizeof (TpmPhysicalSetDeactivatedCommand),\r
1039 ReceiveBuffer, &ReceiveBufferSize\r
1040 );\r
1041 gRT->ResetSystem (EfiResetWarm, EFI_SUCCESS, 0, NULL);\r
1042 }\r
1043 if (Data == 0x04)\r
1044 {\r
1045 //\r
1046 // TPM_PhysicalSetDeactivated=TRUE\r
1047 //\r
1048 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1049 TpmPhysicalSetDeactivatedCommand [10] = 0x01;\r
1050 Status = TpmMpDriver->Transmit (\r
1051 TpmMpDriver,\r
1052 TpmPhysicalSetDeactivatedCommand,\r
1053 sizeof (TpmPhysicalSetDeactivatedCommand),\r
1054 ReceiveBuffer,\r
1055 &ReceiveBufferSize\r
1056 );\r
1057 gRT->ResetSystem (\r
1058 EfiResetWarm,\r
1059 EFI_SUCCESS,\r
1060 0,\r
1061 NULL\r
1062 );\r
1063 }\r
1064 if (Data == 0x05)\r
1065 {\r
1066 //\r
1067 // TPM_ForceClear\r
1068 //\r
1069 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1070 Status = TpmMpDriver->Transmit (\r
1071 TpmMpDriver,\r
1072 TpmForceClearCommand,\r
1073 sizeof (TpmForceClearCommand),\r
1074 ReceiveBuffer,\r
1075 &ReceiveBufferSize\r
1076 );\r
1077 gRT->ResetSystem (\r
1078 EfiResetWarm,\r
1079 EFI_SUCCESS,\r
1080 0,\r
1081 NULL\r
1082 );\r
1083 }\r
1084 if (Data == 0x06)\r
1085 {\r
1086 //\r
1087 // TPM_PhysicalEnable\r
1088 //\r
1089 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1090 Status = TpmMpDriver->Transmit (\r
1091 TpmMpDriver,\r
1092 TpmPhysicalEnableCommand,\r
1093 sizeof (TpmPhysicalEnableCommand),\r
1094 ReceiveBuffer,\r
1095 &ReceiveBufferSize\r
1096 );\r
1097 //\r
1098 // TPM_PhysicalSetDeactivated=FALSE\r
1099 //\r
1100 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1101 TpmPhysicalSetDeactivatedCommand [10] = 0x00;\r
1102 Status = TpmMpDriver->Transmit (\r
1103 TpmMpDriver,\r
1104 TpmPhysicalSetDeactivatedCommand,\r
1105 sizeof (TpmPhysicalSetDeactivatedCommand),\r
1106 ReceiveBuffer,\r
1107 &ReceiveBufferSize\r
1108 );\r
1109 gRT->ResetSystem (\r
1110 EfiResetWarm,\r
1111 EFI_SUCCESS,\r
1112 0,\r
1113 NULL\r
1114 );\r
1115 }\r
1116 if (Data == 0x07)\r
1117 {\r
1118 //\r
1119 // TPM_PhysicalSetDeactivated=TRUE\r
1120 //\r
1121 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1122 TpmPhysicalSetDeactivatedCommand [10] = 0x01;\r
1123 Status = TpmMpDriver->Transmit (\r
1124 TpmMpDriver,\r
1125 TpmPhysicalSetDeactivatedCommand,\r
1126 sizeof (TpmPhysicalSetDeactivatedCommand),\r
1127 ReceiveBuffer,\r
1128 &ReceiveBufferSize\r
1129 );\r
1130 //\r
1131 // TPM_PhysicalDisable\r
1132 //\r
1133 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1134 Status = TpmMpDriver->Transmit (\r
1135 TpmMpDriver,\r
1136 TpmPhysicalDisableCommand,\r
1137 sizeof (TpmPhysicalDisableCommand),\r
1138 ReceiveBuffer,\r
1139 &ReceiveBufferSize\r
1140 );\r
1141 gRT->ResetSystem (\r
1142 EfiResetWarm,\r
1143 EFI_SUCCESS,\r
1144 0,\r
1145 NULL\r
1146 );\r
1147 }\r
1148 if (Data == 0x08)\r
1149 {\r
1150 //\r
1151 // TPM_SetOwnerInstall=TRUE\r
1152 //\r
1153 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1154 TpmSetOwnerInstallCommand [10] = 0x01;\r
1155 Status = TpmMpDriver->Transmit (\r
1156 TpmMpDriver,\r
1157 TpmSetOwnerInstallCommand,\r
1158 sizeof (TpmSetOwnerInstallCommand),\r
1159 ReceiveBuffer,\r
1160 &ReceiveBufferSize\r
1161 );\r
1162 }\r
1163 if (Data == 0x09)\r
1164 {\r
1165 //\r
1166 // TPM_SetOwnerInstall=FALSE\r
1167 //\r
1168 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1169 TpmSetOwnerInstallCommand [10] = 0x00;\r
1170 Status = TpmMpDriver->Transmit (\r
1171 TpmMpDriver,\r
1172 TpmSetOwnerInstallCommand,\r
1173 sizeof (TpmSetOwnerInstallCommand),\r
1174 ReceiveBuffer,\r
1175 &ReceiveBufferSize\r
1176 );\r
1177 }\r
1178 if (Data == 0x0A)\r
1179 {\r
1180 //\r
1181 // TPM_PhysicalEnable\r
1182 //\r
1183 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1184 Status = TpmMpDriver->Transmit (\r
1185 TpmMpDriver,\r
1186 TpmPhysicalEnableCommand,\r
1187 sizeof (TpmPhysicalEnableCommand),\r
1188 ReceiveBuffer,\r
1189 &ReceiveBufferSize\r
1190 );\r
1191 //\r
1192 // TPM_PhysicalSetDeactivated=FALSE\r
1193 //\r
1194 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1195 TpmPhysicalSetDeactivatedCommand [10] = 0x00;\r
1196 Status = TpmMpDriver->Transmit (\r
1197 TpmMpDriver,\r
1198 TpmPhysicalSetDeactivatedCommand,\r
1199 sizeof (TpmPhysicalSetDeactivatedCommand),\r
1200 ReceiveBuffer,\r
1201 &ReceiveBufferSize\r
1202 );\r
1203 //\r
1204 // Do TPM_SetOwnerInstall=TRUE on next reboot\r
1205 //\r
1206\r
1207 WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0xF0);\r
1208\r
1209 gRT->ResetSystem (\r
1210 EfiResetWarm,\r
1211 EFI_SUCCESS,\r
1212 0,\r
1213 NULL\r
1214 );\r
1215 }\r
1216 if (Data == 0x0B)\r
1217 {\r
1218 //\r
1219 // TPM_SetOwnerInstall=FALSE\r
1220 //\r
1221 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1222 TpmSetOwnerInstallCommand [10] = 0x00;\r
1223 Status = TpmMpDriver->Transmit (\r
1224 TpmMpDriver,\r
1225 TpmSetOwnerInstallCommand,\r
1226 sizeof (TpmSetOwnerInstallCommand),\r
1227 ReceiveBuffer,\r
1228 &ReceiveBufferSize\r
1229 );\r
1230 //\r
1231 // TPM_PhysicalSetDeactivated=TRUE\r
1232 //\r
1233 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1234 TpmPhysicalSetDeactivatedCommand [10] = 0x01;\r
1235 Status = TpmMpDriver->Transmit (\r
1236 TpmMpDriver,\r
1237 TpmPhysicalSetDeactivatedCommand,\r
1238 sizeof (TpmPhysicalSetDeactivatedCommand),\r
1239 ReceiveBuffer,\r
1240 &ReceiveBufferSize\r
1241 );\r
1242 //\r
1243 // TPM_PhysicalDisable\r
1244 //\r
1245 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1246 Status = TpmMpDriver->Transmit (\r
1247 TpmMpDriver,\r
1248 TpmPhysicalDisableCommand,\r
1249 sizeof (TpmPhysicalDisableCommand),\r
1250 ReceiveBuffer,\r
1251 &ReceiveBufferSize\r
1252 );\r
1253 gRT->ResetSystem (\r
1254 EfiResetWarm,\r
1255 EFI_SUCCESS,\r
1256 0,\r
1257 NULL\r
1258 );\r
1259 }\r
1260 if (Data == 0x0E)\r
1261 {\r
1262 //\r
1263 // TPM_ForceClear\r
1264 //\r
1265 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1266 Status = TpmMpDriver->Transmit (\r
1267 TpmMpDriver,\r
1268 TpmForceClearCommand,\r
1269 sizeof (TpmForceClearCommand),\r
1270 ReceiveBuffer,\r
1271 &ReceiveBufferSize\r
1272 );\r
1273 //\r
1274 // TPM_PhysicalEnable\r
1275 //\r
1276 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1277 Status = TpmMpDriver->Transmit (\r
1278 TpmMpDriver,\r
1279 TpmPhysicalEnableCommand,\r
1280 sizeof (TpmPhysicalEnableCommand),\r
1281 ReceiveBuffer,\r
1282 &ReceiveBufferSize\r
1283 );\r
1284 //\r
1285 // TPM_PhysicalSetDeactivated=FALSE\r
1286 //\r
1287 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1288 TpmPhysicalSetDeactivatedCommand [10] = 0x00;\r
1289 Status = TpmMpDriver->Transmit (\r
1290 TpmMpDriver,\r
1291 TpmPhysicalSetDeactivatedCommand,\r
1292 sizeof (TpmPhysicalSetDeactivatedCommand),\r
1293 ReceiveBuffer,\r
1294 &ReceiveBufferSize\r
1295 );\r
1296 gRT->ResetSystem (\r
1297 EfiResetWarm,\r
1298 EFI_SUCCESS,\r
1299 0,\r
1300 NULL\r
1301 );\r
1302 }\r
1303 if (Data == 0xF0)\r
1304 {\r
1305 //\r
1306 // Second part of ACPI TPM request 0x0A: OEM custom TPM_SetOwnerInstall=TRUE\r
1307 //\r
1308 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1309 TpmSetOwnerInstallCommand [10] = 0x01;\r
1310 Status = TpmMpDriver->Transmit (\r
1311 TpmMpDriver,\r
1312 TpmSetOwnerInstallCommand,\r
1313 sizeof (TpmSetOwnerInstallCommand),\r
1314 ReceiveBuffer,\r
1315 &ReceiveBufferSize\r
1316 );\r
1317 WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, 0x0A);\r
1318 }\r
1319 //\r
1320 // Deassert Physical Presence\r
1321 //\r
1322 TpmPhysicalPresenceCommand [11] = 0x10;\r
1323 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1324 Status = TpmMpDriver->Transmit (\r
1325 TpmMpDriver,\r
1326 TpmPhysicalPresenceCommand,\r
1327 sizeof (TpmPhysicalPresenceCommand),\r
1328 ReceiveBuffer,\r
1329 &ReceiveBufferSize\r
1330 );\r
1331 }\r
1332 }\r
1333\r
1334 return;\r
1335}\r
1336\r
1337/**\r
1338\r
1339 Initializes manufacturing and config mode setting.\r
1340\r
1341**/\r
1342VOID\r
1343InitMfgAndConfigModeStateVar()\r
1344{\r
1345 EFI_PLATFORM_SETUP_ID *BootModeBuffer;\r
1346 VOID *HobList;\r
1347 UINT16 State;\r
1348\r
1349 //\r
1350 // Variable initialization\r
1351 //\r
1352 State = FALSE;\r
1353\r
1354 HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);\r
1355 if (HobList != NULL) {\r
1356 BootModeBuffer = GET_GUID_HOB_DATA (HobList);\r
1357\r
1358 //\r
1359 // Check if in Manufacturing mode\r
1360 //\r
1361 if ( !CompareMem (\r
1362 &BootModeBuffer->SetupName,\r
1363 MANUFACTURE_SETUP_NAME,\r
1364 StrSize (MANUFACTURE_SETUP_NAME)\r
1365 ) ) {\r
1366 mMfgMode = TRUE;\r
1367 }\r
1368\r
1369 //\r
1370 // Check if in safe mode\r
1371 //\r
1372 if ( !CompareMem (\r
1373 &BootModeBuffer->SetupName,\r
1374 SAFE_SETUP_NAME,\r
1375 StrSize (SAFE_SETUP_NAME)\r
1376 ) ) {\r
1377 State = TRUE;\r
1378 }\r
1379 }\r
1380\r
1381}\r
1382\r
1383/**\r
1384\r
1385 Initializes manufacturing and config mode setting.\r
1386\r
1387**/\r
1388VOID\r
1389InitPlatformBootMode()\r
1390{\r
1391 EFI_PLATFORM_SETUP_ID *BootModeBuffer;\r
1392 VOID *HobList;\r
1393\r
1394 HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);\r
1395 if (HobList != NULL) {\r
1396 BootModeBuffer = GET_GUID_HOB_DATA (HobList);\r
1397 mPlatformBootMode = BootModeBuffer->PlatformBootMode;\r
1398 }\r
1399}\r
1400\r
1401/**\r
1402\r
1403 Initializes ITK.\r
1404\r
1405**/\r
1406VOID\r
1407InitItk(\r
1408 )\r
1409{\r
1410 EFI_STATUS Status;\r
1411 UINT16 ItkModBiosState;\r
1412 UINT8 Value;\r
1413 UINTN DataSize;\r
1414 UINT32 Attributes;\r
1415\r
1416 //\r
1417 // Setup local variable according to ITK variable\r
1418 //\r
1419 //\r
1420 // Read ItkBiosModVar to determine if BIOS has been modified by ITK\r
1421 // If ItkBiosModVar = 0 or if variable hasn't been initialized then BIOS has not been modified by ITK modified\r
1422 // Set local variable VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME=0 if BIOS has not been modified by ITK\r
1423 //\r
1424 DataSize = sizeof (Value);\r
1425 Status = gRT->GetVariable (\r
1426 ITK_BIOS_MOD_VAR_NAME,\r
1427 &gItkDataVarGuid,\r
1428 &Attributes,\r
1429 &DataSize,\r
1430 &Value\r
1431 );\r
1432 if (Status == EFI_NOT_FOUND) {\r
1433 //\r
1434 // Variable not found, hasn't been initialized, intialize to 0\r
1435 //\r
1436 Value=0x00;\r
1437 //\r
1438 // Write variable to flash.\r
1439 //\r
1440 gRT->SetVariable (\r
1441 ITK_BIOS_MOD_VAR_NAME,\r
1442 &gItkDataVarGuid,\r
1443 EFI_VARIABLE_RUNTIME_ACCESS |\r
1444 EFI_VARIABLE_NON_VOLATILE |\r
1445 EFI_VARIABLE_BOOTSERVICE_ACCESS,\r
1446 sizeof (Value),\r
1447 &Value\r
1448 );\r
1449\r
1450}\r
1451 if ( (!EFI_ERROR (Status)) || (Status == EFI_NOT_FOUND) ) {\r
1452 if (Value == 0x00) {\r
1453 ItkModBiosState = 0x00;\r
1454 } else {\r
1455 ItkModBiosState = 0x01;\r
1456 }\r
1457 gRT->SetVariable (\r
1458 VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME,\r
1459 &gEfiNormalSetupGuid,\r
1460 EFI_VARIABLE_BOOTSERVICE_ACCESS,\r
1461 2,\r
1462 (void *)&ItkModBiosState\r
1463 );\r
1464 }\r
1465}\r
1466\r
1467#if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)\r
1468\r
1469/**\r
1470\r
1471 Initializes the BIOS FIRMWARE ID from the FIRMWARE_ID build variable.\r
1472\r
1473**/\r
1474STATIC\r
1475VOID\r
1476InitFirmwareId(\r
1477 )\r
1478{\r
1479 EFI_STATUS Status;\r
1480 CHAR16 FirmwareIdNameWithPassword[] = FIRMWARE_ID_NAME_WITH_PASSWORD;\r
1481\r
1482 //\r
1483 // First try writing the variable without a password in case we are\r
1484 // upgrading from a BIOS without password protection on the FirmwareId\r
1485 //\r
1486 Status = gRT->SetVariable(\r
1487 (CHAR16 *)&gFirmwareIdName,\r
1488 &gFirmwareIdGuid,\r
1489 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |\r
1490 EFI_VARIABLE_RUNTIME_ACCESS,\r
1491 sizeof( FIRMWARE_ID ) - 1,\r
1492 FIRMWARE_ID\r
1493 );\r
1494\r
1495 if (Status == EFI_INVALID_PARAMETER) {\r
1496\r
1497 //\r
1498 // Since setting the firmware id without the password failed,\r
1499 // a password must be required.\r
1500 //\r
1501 Status = gRT->SetVariable(\r
1502 (CHAR16 *)&FirmwareIdNameWithPassword,\r
1503 &gFirmwareIdGuid,\r
1504 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |\r
1505 EFI_VARIABLE_RUNTIME_ACCESS,\r
1506 sizeof( FIRMWARE_ID ) - 1,\r
1507 FIRMWARE_ID\r
1508 );\r
1509 }\r
1510}\r
1511#endif\r
1512\r
1513VOID\r
1514UpdateDVMTSetup(\r
1515 )\r
1516{\r
1517 //\r
1518 // Workaround to support IIA bug.\r
1519 // IIA request to change option value to 4, 5 and 7 relatively\r
1520 // instead of 1, 2, and 3 which follow Lakeport Specs.\r
1521 // Check option value, temporary hardcode GraphicsDriverMemorySize\r
1522 // Option value to fulfill IIA requirment. So that user no need to\r
1523 // load default and update setupvariable after update BIOS.\r
1524 // Option value hardcoded as: 1 to 4, 2 to 5, 3 to 7.\r
1525 // *This is for broadwater and above product only.\r
1526 //\r
1527\r
1528 SYSTEM_CONFIGURATION SystemConfiguration;\r
1529 UINTN VarSize;\r
1530 EFI_STATUS Status;\r
1531\r
1532 VarSize = sizeof(SYSTEM_CONFIGURATION);\r
1533 Status = gRT->GetVariable(\r
1534 NORMAL_SETUP_NAME,\r
1535 &gEfiNormalSetupGuid,\r
1536 NULL,\r
1537 &VarSize,\r
1538 &SystemConfiguration\r
1539 );\r
1540\r
1541 if((SystemConfiguration.GraphicsDriverMemorySize < 4) && !EFI_ERROR(Status) ) {\r
1542 switch (SystemConfiguration.GraphicsDriverMemorySize){\r
1543 case 1:\r
1544 SystemConfiguration.GraphicsDriverMemorySize = 4;\r
1545 break;\r
1546 case 2:\r
1547 SystemConfiguration.GraphicsDriverMemorySize = 5;\r
1548 break;\r
1549 case 3:\r
1550 SystemConfiguration.GraphicsDriverMemorySize = 7;\r
1551 break;\r
1552 default:\r
1553 break;\r
1554 }\r
1555\r
1556 Status = gRT->SetVariable (\r
1557 NORMAL_SETUP_NAME,\r
1558 &gEfiNormalSetupGuid,\r
1559 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,\r
1560 sizeof(SYSTEM_CONFIGURATION),\r
1561 &SystemConfiguration\r
1562 );\r
1563 }\r
1564}\r
1565\r
1566VOID\r
1567InitPlatformUsbPolicy (\r
1568 VOID\r
1569 )\r
1570\r
1571{\r
1572 EFI_HANDLE Handle;\r
1573 EFI_STATUS Status;\r
1574\r
1575 Handle = NULL;\r
1576\r
1577 mUsbPolicyData.Version = (UINT8)USB_POLICY_PROTOCOL_REVISION_2;\r
1578 mUsbPolicyData.UsbMassStorageEmulationType = mSystemConfiguration.UsbBIOSINT13DeviceEmulation;\r
1579 if(mUsbPolicyData.UsbMassStorageEmulationType == 3) {\r
1580 mUsbPolicyData.UsbEmulationSize = mSystemConfiguration.UsbBIOSINT13DeviceEmulationSize;\r
1581 } else {\r
1582 mUsbPolicyData.UsbEmulationSize = 0;\r
1583 }\r
1584 mUsbPolicyData.UsbZipEmulationType = mSystemConfiguration.UsbZipEmulation;\r
1585 mUsbPolicyData.UsbOperationMode = HIGH_SPEED;\r
1586\r
1587 //\r
1588 // Some chipset need Period smi, 0 = LEGACY_PERIOD_UN_SUPP\r
1589 //\r
1590 mUsbPolicyData.USBPeriodSupport = LEGACY_PERIOD_UN_SUPP;\r
1591\r
1592 //\r
1593 // Some platform need legacyfree, 0 = LEGACY_FREE_UN_SUPP\r
1594 //\r
1595 mUsbPolicyData.LegacyFreeSupport = LEGACY_FREE_UN_SUPP;\r
1596\r
1597 //\r
1598 // Set Code base , TIANO_CODE_BASE =0x01, ICBD =0x00\r
1599 //\r
1600 mUsbPolicyData.CodeBase = (UINT8)ICBD_CODE_BASE;\r
1601\r
1602 //\r
1603 // Some chispet 's LpcAcpibase are diffrent,set by platform or chipset,\r
1604 // default is Ich acpibase =0x040. acpitimerreg=0x08.\r
1605 mUsbPolicyData.LpcAcpiBase = 0x40;\r
1606 mUsbPolicyData.AcpiTimerReg = 0x08;\r
1607\r
1608 //\r
1609 // Set for reduce usb post time\r
1610 //\r
1611 mUsbPolicyData.UsbTimeTue = 0x00;\r
1612 mUsbPolicyData.InternelHubExist = 0x00; //TigerPoint doesn't have RMH\r
1613 mUsbPolicyData.EnumWaitPortStableStall = 100;\r
1614\r
1615\r
1616 Status = gBS->InstallProtocolInterface (\r
1617 &Handle,\r
1618 &gUsbPolicyGuid,\r
1619 EFI_NATIVE_INTERFACE,\r
1620 &mUsbPolicyData\r
1621 );\r
1622 ASSERT_EFI_ERROR(Status);\r
1623\r
1624}\r
1625\r
1626UINT8\r
1627ReadCmosBank1Byte (\r
1628 IN EFI_CPU_IO_PROTOCOL *CpuIo,\r
1629 IN UINT8 Index\r
1630 )\r
1631{\r
1632 UINT8 Data;\r
1633\r
1634 CpuIo->Io.Write (CpuIo, EfiCpuIoWidthUint8, 0x72, 1, &Index);\r
1635 CpuIo->Io.Read (CpuIo, EfiCpuIoWidthUint8, 0x73, 1, &Data);\r
1636 return Data;\r
1637}\r
1638\r
1639VOID\r
1640WriteCmosBank1Byte (\r
1641 IN EFI_CPU_IO_PROTOCOL *CpuIo,\r
1642 IN UINT8 Index,\r
1643 IN UINT8 Data\r
1644 )\r
1645{\r
1646 CpuIo->Io.Write (\r
1647 CpuIo,\r
1648 EfiCpuIoWidthUint8,\r
1649 0x72,\r
1650 1,\r
1651 &Index\r
1652 );\r
1653 CpuIo->Io.Write (\r
1654 CpuIo,\r
1655 EfiCpuIoWidthUint8,\r
1656 0x73,\r
1657 1,\r
1658 &Data\r
1659 );\r
1660}\r
1661\r
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