[mirror_edk2.git] / Vlv2TbltDevicePkg / PlatformInitPei / MemoryCallback.c

/** @file\r
\r
  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
                                                                                   \r\r
  This program and the accompanying materials are licensed and made available under\r\r
  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
  The full text of the license may be found at                                     \r\r
  http://opensource.org/licenses/bsd-license.php.                                  \r\r
                                                                                   \r\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
                                                                                   \r\r
\r
Module Name:\r
\r
  MemoryCallback.c\r
\r
Abstract:\r
\r
  EFI 2.0 PEIM to provide the platform support functionality on the Bridgeport.\r
\r
--*/\r
\r
#include "PlatformEarlyInit.h"\r
\r
\r
VOID\r
UpdateDefaultSetupValue (\r
  IN  EFI_PLATFORM_INFO_HOB       *PlatformInfo\r
  )\r
{\r
return;\r
}\r
\r
/**\r
  PEI termination callback.\r
\r
  @param PeiServices         General purpose services available to every PEIM.\r
  @param NotifyDescriptor    Not uesed.\r
  @param Ppi                 Not uesed.\r
\r
  @retval EFI_SUCCESS        If the interface could be successfully\r
                             installed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI    \r
EndOfPeiPpiNotifyCallback (\r
  IN CONST EFI_PEI_SERVICES           **PeiServices,\r
  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
  IN VOID                       *Ppi\r
  )\r
{\r
  EFI_STATUS                  Status;\r
  UINT64                      LowUncableBase;\r
  EFI_PLATFORM_INFO_HOB       *PlatformInfo;\r
  UINT32                      HecBaseHigh;\r
  EFI_BOOT_MODE               BootMode;\r
  EFI_PEI_HOB_POINTERS        Hob;\r
\r
  Status = (*PeiServices)->GetBootMode(\r
                             PeiServices,\r
                             &BootMode\r
                             );\r
\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Set the some PCI and chipset range as UC\r
  // And align to 1M at leaset\r
  //\r
  Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r
  ASSERT (Hob.Raw != NULL);\r
  PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);\r
\r
  UpdateDefaultSetupValue (PlatformInfo);\r
\r
  DEBUG ((EFI_D_ERROR, "Memory TOLM: %X\n", PlatformInfo->MemData.MemTolm));\r
  DEBUG ((EFI_D_ERROR, "PCIE OSBASE: %lX\n", PlatformInfo->PciData.PciExpressBase));\r
  DEBUG (\r
    (EFI_D_ERROR,\r
    "PCIE   BASE: %lX     Size : %X\n",\r
    PlatformInfo->PciData.PciExpressBase,\r
    PlatformInfo->PciData.PciExpressSize)\r
    );\r
  DEBUG (\r
    (EFI_D_ERROR,\r
    "PCI32  BASE: %X     Limit: %X\n",\r
    PlatformInfo->PciData.PciResourceMem32Base,\r
    PlatformInfo->PciData.PciResourceMem32Limit)\r
    );\r
  DEBUG (\r
    (EFI_D_ERROR,\r
    "PCI64  BASE: %lX     Limit: %lX\n",\r
    PlatformInfo->PciData.PciResourceMem64Base,\r
    PlatformInfo->PciData.PciResourceMem64Limit)\r
    );\r
  DEBUG ((EFI_D_ERROR, "UC    START: %lX     End  : %lX\n", PlatformInfo->MemData.MemMir0, PlatformInfo->MemData.MemMir1));\r
\r
  LowUncableBase = PlatformInfo->MemData.MemMaxTolm;\r
  LowUncableBase &= (0x0FFF00000);\r
\r
  if (BootMode != BOOT_ON_S3_RESUME) {\r
    //\r
    // In BIOS, HECBASE will be always below 4GB\r
    //\r
    HecBaseHigh = (UINT32) RShiftU64 (PlatformInfo->PciData.PciExpressBase, 28);\r
    ASSERT (HecBaseHigh < 16);\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Install Firmware Volume Hob's once there is main memory\r
\r
  @param PeiServices       General purpose services available to every PEIM.\r
  @param NotifyDescriptor  Notify that this module published.\r
  @param Ppi               PPI that was installed.\r
\r
  @retval EFI_SUCCESS     The function completed successfully.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
MemoryDiscoveredPpiNotifyCallback (\r
  IN CONST EFI_PEI_SERVICES           **PeiServices,\r
  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
  IN VOID                       *Ppi\r
  )\r
{\r
  EFI_STATUS                  Status;\r
  EFI_BOOT_MODE               BootMode;\r
  EFI_CPUID_REGISTER          FeatureInfo;\r
  UINT8                       CpuAddressWidth;\r
  UINT16                      Pm1Cnt;\r
  EFI_PEI_HOB_POINTERS        Hob;\r
  EFI_PLATFORM_INFO_HOB       *PlatformInfo;\r
  UINT32                      RootComplexBar;\r
  UINT32                      PmcBase;\r
  UINT32                      IoBase;\r
  UINT32                      IlbBase;\r
  UINT32                      SpiBase;\r
  UINT32                      MphyBase;\r
\r
  //\r
  // Get Platform Info HOB\r
  //\r
  Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r
  ASSERT (Hob.Raw != NULL);\r
  PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);\r
\r
  Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);\r
\r
  //\r
  // Check if user wants to turn off in PEI phase\r
  //\r
  if ((BootMode != BOOT_ON_S3_RESUME) && (BootMode != BOOT_ON_FLASH_UPDATE)) {\r
    CheckPowerOffNow();\r
  } else {\r
    Pm1Cnt  = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);\r
    Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP;\r
    IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);\r
  }\r
\r
  #ifndef MINNOW2_FSP_BUILD\r
  //\r
  // Set PEI cache mode here\r
  //\r
  SetPeiCacheMode (PeiServices);\r
  #endif\r
\r
  //\r
  //  Pulish memory tyoe info\r
  //\r
  PublishMemoryTypeInfo ();\r
\r
  //\r
  // Work done if on a S3 resume\r
  //\r
  if (BootMode == BOOT_ON_S3_RESUME) {\r
    //\r
    //Program the side band packet register to send a sideband message to Punit\r
    //To indicate that DRAM has been initialized and PUNIT FW base address in memory.\r
    //\r
    return EFI_SUCCESS;\r
  }\r
\r
  RootComplexBar = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_RCBA ) & B_PCH_LPC_RCBA_BAR;\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    RootComplexBar,\r
    0x1000\r
    );\r
  DEBUG ((EFI_D_INFO, "RootComplexBar     : 0x%x\n", RootComplexBar));\r
\r
  PmcBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_PMC_BASE ) & B_PCH_LPC_PMC_BASE_BAR;\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    PmcBase,\r
    0x1000\r
    );\r
  DEBUG ((EFI_D_INFO, "PmcBase            : 0x%x\n", PmcBase));\r
\r
  IoBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE ) & B_PCH_LPC_IO_BASE_BAR;\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    IoBase,\r
    0x4000\r
    );\r
  DEBUG ((EFI_D_INFO, "IoBase             : 0x%x\n", IoBase));\r
\r
  IlbBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ILB_BASE ) & B_PCH_LPC_ILB_BASE_BAR;\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    IlbBase,\r
    0x1000\r
    );\r
  DEBUG ((EFI_D_INFO, "IlbBase            : 0x%x\n", IlbBase));\r
\r
  SpiBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_SPI_BASE ) & B_PCH_LPC_SPI_BASE_BAR;\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    SpiBase,\r
    0x1000\r
    );\r
  DEBUG ((EFI_D_INFO, "SpiBase            : 0x%x\n", SpiBase));\r
\r
  MphyBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_MPHY_BASE ) & B_PCH_LPC_MPHY_BASE_BAR;\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    MphyBase,\r
    0x100000\r
    );\r
  DEBUG ((EFI_D_INFO, "MphyBase           : 0x%x\n", MphyBase));\r
\r
  //\r
  // Local APIC\r
  //\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    LOCAL_APIC_ADDRESS,\r
    0x1000\r
  );\r
  DEBUG ((EFI_D_INFO, "LOCAL_APIC_ADDRESS : 0x%x\n", LOCAL_APIC_ADDRESS));\r
\r
  //\r
  // IO APIC\r
  //\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    IO_APIC_ADDRESS,\r
    0x1000\r
  );\r
  DEBUG ((EFI_D_INFO, "IO_APIC_ADDRESS    : 0x%x\n", IO_APIC_ADDRESS));\r
\r
  //\r
  // Adding the PCIE Express area to the E820 memory table as type 2 memory.\r
  //\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    PlatformInfo->PciData.PciExpressBase,\r
    PlatformInfo->PciData.PciExpressSize\r
    );\r
  DEBUG ((EFI_D_INFO, "PciExpressBase     : 0x%x\n", PlatformInfo->PciData.PciExpressBase));\r
\r
  //\r
  // Adding the Flashpart to the E820 memory table as type 2 memory.\r
  //\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_FIRMWARE_DEVICE,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    FixedPcdGet32 (PcdFlashAreaBaseAddress),\r
    FixedPcdGet32 (PcdFlashAreaSize)\r
    );\r
  DEBUG ((EFI_D_INFO, "FLASH_BASE_ADDRESS : 0x%x\n", FixedPcdGet32 (PcdFlashAreaBaseAddress)));\r
\r
  //\r
  // Create a CPU hand-off information\r
  //\r
  CpuAddressWidth = 32;\r
  AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);\r
  if (FeatureInfo.RegEax >= EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE) {\r
    AsmCpuid (EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);\r
    CpuAddressWidth = (UINT8) (FeatureInfo.RegEax & 0xFF);\r
  }\r
\r
  BuildCpuHob(CpuAddressWidth, 16);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  return Status;\r
\r
}\r
\r
\r
EFI_STATUS\r
ValidateFvHeader (\r
  IN EFI_FIRMWARE_VOLUME_HEADER            *FwVolHeader\r
  )\r
{\r
  UINT16  *Ptr;\r
  UINT16  HeaderLength;\r
  UINT16  Checksum;\r
\r
  //\r
  // Verify the header revision, header signature, length\r
  // Length of FvBlock cannot be 2**64-1\r
  // HeaderLength cannot be an odd number\r
  //\r
  if ((FwVolHeader->Revision != EFI_FVH_REVISION) ||\r
      (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||\r
      (FwVolHeader->FvLength == ((UINT64) -1)) ||\r
      ((FwVolHeader->HeaderLength & 0x01) != 0)\r
      ) {\r
    return EFI_NOT_FOUND;\r
  }\r
\r
  //\r
  // Verify the header checksum\r
  //\r
  HeaderLength  = (UINT16) (FwVolHeader->HeaderLength / 2);\r
  Ptr           = (UINT16 *) FwVolHeader;\r
  Checksum      = 0;\r
  while (HeaderLength > 0) {\r
    Checksum = *Ptr++;\r
    HeaderLength--;\r
  }\r
\r
  if (Checksum != 0) {\r
    return EFI_NOT_FOUND;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
Commit	Line	Data
3cbfba02 DW	1	/** @file\r
	2	\r
	3	Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
	4	\r\r
	5	This program and the accompanying materials are licensed and made available under\r\r
	6	the terms and conditions of the BSD License that accompanies this distribution. \r\r
	7	The full text of the license may be found at \r\r
	8	http://opensource.org/licenses/bsd-license.php. \r\r
	9	\r\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r
	12	\r\r
	13	\r
	14	Module Name:\r
	15	\r
	16	MemoryCallback.c\r
	17	\r
	18	Abstract:\r
	19	\r
	20	EFI 2.0 PEIM to provide the platform support functionality on the Bridgeport.\r
	21	\r
	22	--*/\r
	23	\r
	24	#include "PlatformEarlyInit.h"\r
	25	\r
	26	\r
	27	VOID\r
	28	UpdateDefaultSetupValue (\r
	29	IN EFI_PLATFORM_INFO_HOB *PlatformInfo\r
	30	)\r
	31	{\r
	32	return;\r
	33	}\r
	34	\r
	35	/**\r
	36	PEI termination callback.\r
	37	\r
	38	@param PeiServices General purpose services available to every PEIM.\r
	39	@param NotifyDescriptor Not uesed.\r
	40	@param Ppi Not uesed.\r
	41	\r
	42	@retval EFI_SUCCESS If the interface could be successfully\r
	43	installed.\r
	44	\r
	45	**/\r
	46	EFI_STATUS\r
	47	EFIAPI \r
	48	EndOfPeiPpiNotifyCallback (\r
	49	IN CONST EFI_PEI_SERVICES **PeiServices,\r
	50	IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
	51	IN VOID *Ppi\r
	52	)\r
	53	{\r
	54	EFI_STATUS Status;\r
3cbfba02 DW	55	UINT64 LowUncableBase;\r
	56	EFI_PLATFORM_INFO_HOB *PlatformInfo;\r
	57	UINT32 HecBaseHigh;\r
	58	EFI_BOOT_MODE BootMode;\r
	59	EFI_PEI_HOB_POINTERS Hob;\r
	60	\r
	61	Status = (*PeiServices)->GetBootMode(\r
	62	PeiServices,\r
	63	&BootMode\r
	64	);\r
	65	\r
	66	ASSERT_EFI_ERROR (Status);\r
	67	\r
	68	//\r
	69	// Set the some PCI and chipset range as UC\r
	70	// And align to 1M at leaset\r
	71	//\r
	72	Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r
	73	ASSERT (Hob.Raw != NULL);\r
	74	PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);\r
	75	\r
	76	UpdateDefaultSetupValue (PlatformInfo);\r
	77	\r
	78	DEBUG ((EFI_D_ERROR, "Memory TOLM: %X\n", PlatformInfo->MemData.MemTolm));\r
	79	DEBUG ((EFI_D_ERROR, "PCIE OSBASE: %lX\n", PlatformInfo->PciData.PciExpressBase));\r
	80	DEBUG (\r
	81	(EFI_D_ERROR,\r
	82	"PCIE BASE: %lX Size : %X\n",\r
	83	PlatformInfo->PciData.PciExpressBase,\r
	84	PlatformInfo->PciData.PciExpressSize)\r
	85	);\r
	86	DEBUG (\r
	87	(EFI_D_ERROR,\r
	88	"PCI32 BASE: %X Limit: %X\n",\r
	89	PlatformInfo->PciData.PciResourceMem32Base,\r
	90	PlatformInfo->PciData.PciResourceMem32Limit)\r
	91	);\r
	92	DEBUG (\r
	93	(EFI_D_ERROR,\r
	94	"PCI64 BASE: %lX Limit: %lX\n",\r
	95	PlatformInfo->PciData.PciResourceMem64Base,\r
	96	PlatformInfo->PciData.PciResourceMem64Limit)\r
	97	);\r
	98	DEBUG ((EFI_D_ERROR, "UC START: %lX End : %lX\n", PlatformInfo->MemData.MemMir0, PlatformInfo->MemData.MemMir1));\r
	99	\r
	100	LowUncableBase = PlatformInfo->MemData.MemMaxTolm;\r
	101	LowUncableBase &= (0x0FFF00000);\r
3cbfba02 DW	102	\r
	103	if (BootMode != BOOT_ON_S3_RESUME) {\r
	104	//\r
	105	// In BIOS, HECBASE will be always below 4GB\r
	106	//\r
	107	HecBaseHigh = (UINT32) RShiftU64 (PlatformInfo->PciData.PciExpressBase, 28);\r
	108	ASSERT (HecBaseHigh < 16);\r
	109	}\r
	110	\r
	111	return Status;\r
	112	}\r
	113	\r
	114	/**\r
	115	Install Firmware Volume Hob's once there is main memory\r
	116	\r
	117	@param PeiServices General purpose services available to every PEIM.\r
	118	@param NotifyDescriptor Notify that this module published.\r
	119	@param Ppi PPI that was installed.\r
	120	\r
	121	@retval EFI_SUCCESS The function completed successfully.\r
	122	\r
	123	**/\r
	124	EFI_STATUS\r
	125	EFIAPI\r
	126	MemoryDiscoveredPpiNotifyCallback (\r
	127	IN CONST EFI_PEI_SERVICES **PeiServices,\r
	128	IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
	129	IN VOID *Ppi\r
	130	)\r
	131	{\r
	132	EFI_STATUS Status;\r
	133	EFI_BOOT_MODE BootMode;\r
	134	EFI_CPUID_REGISTER FeatureInfo;\r
	135	UINT8 CpuAddressWidth;\r
	136	UINT16 Pm1Cnt;\r
	137	EFI_PEI_HOB_POINTERS Hob;\r
	138	EFI_PLATFORM_INFO_HOB *PlatformInfo;\r
	139	UINT32 RootComplexBar;\r
	140	UINT32 PmcBase;\r
	141	UINT32 IoBase;\r
	142	UINT32 IlbBase;\r
	143	UINT32 SpiBase;\r
	144	UINT32 MphyBase;\r
	145	\r
	146	//\r
	147	// Get Platform Info HOB\r
	148	//\r
	149	Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r
	150	ASSERT (Hob.Raw != NULL);\r
	151	PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);\r
	152	\r
	153	Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);\r
	154	\r
	155	//\r
	156	// Check if user wants to turn off in PEI phase\r
	157	//\r
	158	if ((BootMode != BOOT_ON_S3_RESUME) && (BootMode != BOOT_ON_FLASH_UPDATE)) {\r
	159	CheckPowerOffNow();\r
	160	} else {\r
	161	Pm1Cnt = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);\r
	162	Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP;\r
	163	IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);\r
	164	}\r
	165	\r
166	#ifndef MINNOW2_FSP_BUILD\r
167	//\r
168	// Set PEI cache mode here\r
169	//\r
170	SetPeiCacheMode (PeiServices);\r
171	#endif\r
172	\r
173	//\r
174	// Pulish memory tyoe info\r
175	//\r
176	PublishMemoryTypeInfo ();\r
177	\r
178	//\r
179	// Work done if on a S3 resume\r
180	//\r
181	if (BootMode == BOOT_ON_S3_RESUME) {\r
182	//\r
183	//Program the side band packet register to send a sideband message to Punit\r
184	//To indicate that DRAM has been initialized and PUNIT FW base address in memory.\r
185	//\r
186	return EFI_SUCCESS;\r
187	}\r
188	\r
189	RootComplexBar = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_RCBA ) & B_PCH_LPC_RCBA_BAR;\r
190	BuildResourceDescriptorHob (\r
191	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
192	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
193	RootComplexBar,\r
194	0x1000\r
195	);\r
196	DEBUG ((EFI_D_INFO, "RootComplexBar : 0x%x\n", RootComplexBar));\r
197	\r
198	PmcBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_PMC_BASE ) & B_PCH_LPC_PMC_BASE_BAR;\r
199	BuildResourceDescriptorHob (\r
200	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
201	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
202	PmcBase,\r
203	0x1000\r
204	);\r
205	DEBUG ((EFI_D_INFO, "PmcBase : 0x%x\n", PmcBase));\r
206	\r
207	IoBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE ) & B_PCH_LPC_IO_BASE_BAR;\r
208	BuildResourceDescriptorHob (\r
209	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
210	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
211	IoBase,\r
212	0x4000\r
213	);\r
214	DEBUG ((EFI_D_INFO, "IoBase : 0x%x\n", IoBase));\r
215	\r
216	IlbBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ILB_BASE ) & B_PCH_LPC_ILB_BASE_BAR;\r
217	BuildResourceDescriptorHob (\r
218	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
219	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
220	IlbBase,\r
221	0x1000\r
222	);\r
223	DEBUG ((EFI_D_INFO, "IlbBase : 0x%x\n", IlbBase));\r
224	\r
225	SpiBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_SPI_BASE ) & B_PCH_LPC_SPI_BASE_BAR;\r
226	BuildResourceDescriptorHob (\r
227	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
228	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
229	SpiBase,\r
230	0x1000\r
231	);\r
232	DEBUG ((EFI_D_INFO, "SpiBase : 0x%x\n", SpiBase));\r
233	\r
234	MphyBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_MPHY_BASE ) & B_PCH_LPC_MPHY_BASE_BAR;\r
235	BuildResourceDescriptorHob (\r
236	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
237	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
238	MphyBase,\r
239	0x100000\r
240	);\r
241	DEBUG ((EFI_D_INFO, "MphyBase : 0x%x\n", MphyBase));\r
242	\r
243	//\r
244	// Local APIC\r
245	//\r
246	BuildResourceDescriptorHob (\r
247	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
248	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
249	LOCAL_APIC_ADDRESS,\r
250	0x1000\r
251	);\r
252	DEBUG ((EFI_D_INFO, "LOCAL_APIC_ADDRESS : 0x%x\n", LOCAL_APIC_ADDRESS));\r
253	\r
254	//\r
255	// IO APIC\r
256	//\r
257	BuildResourceDescriptorHob (\r
258	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
259	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
260	IO_APIC_ADDRESS,\r
261	0x1000\r
262	);\r
263	DEBUG ((EFI_D_INFO, "IO_APIC_ADDRESS : 0x%x\n", IO_APIC_ADDRESS));\r
264	\r
265	//\r
266	// Adding the PCIE Express area to the E820 memory table as type 2 memory.\r
267	//\r
268	BuildResourceDescriptorHob (\r
269	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
270	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
271	PlatformInfo->PciData.PciExpressBase,\r
272	PlatformInfo->PciData.PciExpressSize\r
273	);\r
274	DEBUG ((EFI_D_INFO, "PciExpressBase : 0x%x\n", PlatformInfo->PciData.PciExpressBase));\r
275	\r
276	//\r
277	// Adding the Flashpart to the E820 memory table as type 2 memory.\r
278	//\r
279	BuildResourceDescriptorHob (\r
280	EFI_RESOURCE_FIRMWARE_DEVICE,\r
281	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
282	FixedPcdGet32 (PcdFlashAreaBaseAddress),\r
283	FixedPcdGet32 (PcdFlashAreaSize)\r
284	);\r
285	DEBUG ((EFI_D_INFO, "FLASH_BASE_ADDRESS : 0x%x\n", FixedPcdGet32 (PcdFlashAreaBaseAddress)));\r
286	\r
287	//\r
288	// Create a CPU hand-off information\r
289	//\r
290	CpuAddressWidth = 32;\r
291	AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);\r
292	if (FeatureInfo.RegEax >= EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE) {\r
293	AsmCpuid (EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);\r
294	CpuAddressWidth = (UINT8) (FeatureInfo.RegEax & 0xFF);\r
295	}\r
296	\r
297	BuildCpuHob(CpuAddressWidth, 16);\r
298	ASSERT_EFI_ERROR (Status);\r
299	\r
300	return Status;\r
301	\r
302	}\r
303	\r
304	\r
305	EFI_STATUS\r
306	ValidateFvHeader (\r
307	IN EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader\r
308	)\r
309	{\r
310	UINT16 *Ptr;\r
311	UINT16 HeaderLength;\r
312	UINT16 Checksum;\r
313	\r
314	//\r
315	// Verify the header revision, header signature, length\r
316	// Length of FvBlock cannot be 2**64-1\r
317	// HeaderLength cannot be an odd number\r
318	//\r
319	if ((FwVolHeader->Revision != EFI_FVH_REVISION) \|\|\r
320	(FwVolHeader->Signature != EFI_FVH_SIGNATURE) \|\|\r
321	(FwVolHeader->FvLength == ((UINT64) -1)) \|\|\r
322	((FwVolHeader->HeaderLength & 0x01) != 0)\r
323	) {\r
324	return EFI_NOT_FOUND;\r
325	}\r
326	\r
327	//\r
328	// Verify the header checksum\r
329	//\r
330	HeaderLength = (UINT16) (FwVolHeader->HeaderLength / 2);\r
331	Ptr = (UINT16 *) FwVolHeader;\r
332	Checksum = 0;\r
333	while (HeaderLength > 0) {\r
334	Checksum = *Ptr++;\r
335	HeaderLength--;\r
336	}\r
337	\r
338	if (Checksum != 0) {\r
339	return EFI_NOT_FOUND;\r
340	}\r
341	\r
342	return EFI_SUCCESS;\r
343	}\r