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MdeModulePkg: Add IsaBusDxe driver
[mirror_edk2.git] / Vlv2TbltDevicePkg / PlatformInitPei / PlatformEarlyInit.c
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DW		 1/** @file\r
2\r
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
4 \r\r
5 This program and the accompanying materials are licensed and made available under\r\r
6 the terms and conditions of the BSD License that accompanies this distribution. \r\r
7 The full text of the license may be found at \r\r
8 http://opensource.org/licenses/bsd-license.php. \r\r
9 \r\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r
12 \r\r
13\r
14\r
15Module Name:\r
16\r
17 PlatformEarlyInit.c\r
18\r
19Abstract:\r
20\r
21 Do platform specific PEI stage initializations.\r
22\r
23--*/\r
24\r
25\r
26#include "PlatformEarlyInit.h"\r
27\r
28#ifdef __GNUC__\r
29#pragma GCC push_options\r
30#pragma GCC optimize ("O0")\r
31#else\r
32#pragma optimize ("", off)\r
33#endif\r
34\r
35\r
36\r
37static EFI_PEI_STALL_PPI mStallPpi = {\r
38 PEI_STALL_RESOLUTION,\r
39 Stall\r
40};\r
41\r
42static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi = {\r
43 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
44 &gEfiPeiStallPpiGuid,\r
45 &mStallPpi\r
46};\r
47\r
48//\r
49// The reserved SMBus addresses are defined in PlatformDxe.h file.\r
50//\r
51static UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;\r
52static PEI_SMBUS_POLICY_PPI mSmbusPolicyPpi = {\r
53 SMBUS_BASE_ADDRESS,\r
54 SMBUS_BUS_DEV_FUNC,\r
55 PLATFORM_NUM_SMBUS_RSVD_ADDRESSES,\r
56 mSmbusRsvdAddresses\r
57};\r
58\r
59static EFI_PEI_PPI_DESCRIPTOR mInstallSmbusPolicyPpi = {\r
60 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
61 &gPeiSmbusPolicyPpiGuid,\r
62 &mSmbusPolicyPpi\r
63};\r
64static PEI_SPEAKER_IF_PPI mSpeakerInterfacePpi = {\r
65 ProgramToneFrequency,\r
66 GenerateBeepTone\r
67};\r
68\r
69static EFI_PEI_PPI_DESCRIPTOR mInstallSpeakerInterfacePpi = {\r
70 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
71 &gPeiSpeakerInterfacePpiGuid,\r
72 &mSpeakerInterfacePpi\r
73};\r
74\r
75static EFI_PEI_RESET_PPI mResetPpi = { IchReset };\r
76\r
77\r
78static EFI_PEI_FIND_FV_PPI mEfiFindFvPpi = {\r
79 (EFI_PEI_FIND_FV_FINDFV)FindFv\r
80};\r
81\r
82static EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {\r
83 {\r
84 EFI_PEI_PPI_DESCRIPTOR_PPI,\r
85 &gEfiPeiMasterBootModePpiGuid,\r
86 NULL\r
87 },\r
88 {\r
89 EFI_PEI_PPI_DESCRIPTOR_PPI,\r
90 &gEfiPeiResetPpiGuid,\r
91 &mResetPpi\r
92 },\r
93 {\r
94 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
95 &gEfiFindFvPpiGuid,\r
96 &mEfiFindFvPpi\r
97 }\r
98};\r
99\r
100static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {\r
101 {\r
102 EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,\r
103 &gEfiEndOfPeiSignalPpiGuid,\r
104 (EFI_PEIM_NOTIFY_ENTRY_POINT)EndOfPeiPpiNotifyCallback\r
105 },\r
106 {\r
107 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
108 &gEfiPeiMemoryDiscoveredPpiGuid,\r
109 (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotifyCallback\r
110 }\r
111\r
112};\r
113\r
114\r
115/**\r
116\r
117 Parse the status registers for figuring out the wake-up event and save it into\r
118 an GUID HOB which will be referenced later. However, modification is required\r
119 to meet the chipset register definition and the practical hardware design. Thus,\r
120 this is just an example.\r
121\r
122\r
123 @param PeiServices pointer to the PEI Service Table\r
124 @param EFI_SUCCESS Always return Success\r
125\r
126 @retval None\r
127\r
128\r
129**/\r
130EFI_STATUS\r
131EFIAPI\r
132GetWakeupEventAndSaveToHob (\r
133 IN CONST EFI_PEI_SERVICES **PeiServices\r
134 )\r
135{\r
136 UINT16 Pm1Sts;\r
137 UINTN Gpe0Sts;\r
138 UINTN WakeEventData;\r
139\r
140 //\r
141 // Read the ACPI registers\r
142 //\r
143 Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);\r
144 Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS);\r
145\r
146 //\r
147 // Figure out the wake-up event\r
148 //\r
149 if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) != 0) {\r
150 WakeEventData = SMBIOS_WAKEUP_TYPE_POWER_SWITCH;\r
151 } else if (((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) != 0)) {\r
152 WakeEventData = SMBIOS_WAKEUP_TYPE_PCI_PME;\r
153 } else if (Gpe0Sts != 0) {\r
154 WakeEventData = SMBIOS_WAKEUP_TYPE_OTHERS;\r
155 } else {\r
156 WakeEventData = SMBIOS_WAKEUP_TYPE_UNKNOWN;\r
157 }\r
158\r
159 DEBUG ((EFI_D_ERROR, "ACPI Wake Status Register: %04x\n", Pm1Sts));\r
160\r
161 return EFI_SUCCESS;\r
162}\r
163\r
164EFI_STATUS\r
165GetSetupVariable (\r
166 IN CONST EFI_PEI_SERVICES **PeiServices,\r
167 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
168 )\r
169{\r
170 UINTN VariableSize;\r
171 EFI_STATUS Status;\r
172 EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;\r
173\r
174 VariableSize = sizeof (SYSTEM_CONFIGURATION);\r
175 ZeroMem (SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));\r
176\r
177 Status = (*PeiServices)->LocatePpi (\r
178 PeiServices,\r
179 &gEfiPeiReadOnlyVariable2PpiGuid,\r
180 0,\r
181 NULL,\r
182 (void **)&Variable\r
183 );\r
184 ASSERT_EFI_ERROR (Status);\r
185\r
186 //\r
187 // Use normal setup default from NVRAM variable,\r
188 // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.\r
189 //\r
190 VariableSize = sizeof(SYSTEM_CONFIGURATION);\r
191 Status = Variable->GetVariable (\r
192 Variable,\r
193 L"Setup",\r
194 &gEfiSetupVariableGuid,\r
195 NULL,\r
196 &VariableSize,\r
197 SystemConfiguration\r
198 );\r
199 ASSERT_EFI_ERROR(Status);\r
200 return Status;\r
201}\r
202\r
203EFI_STATUS\r
204VlvPolicyInit (\r
205 IN CONST EFI_PEI_SERVICES **PeiServices,\r
206 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
207 )\r
208{\r
209 EFI_STATUS Status;\r
210 EFI_PEI_PPI_DESCRIPTOR *mVlvPolicyPpiDesc;\r
211 VLV_POLICY_PPI *mVlvPolicyPpi;\r
212\r
213 Status = (*PeiServices)->AllocatePool(\r
214 PeiServices,\r
215 sizeof (EFI_PEI_PPI_DESCRIPTOR),\r
216 (void **)&mVlvPolicyPpiDesc\r
217 );\r
218 ASSERT_EFI_ERROR (Status);\r
219\r
220 Status = (*PeiServices)->AllocatePool(\r
221 PeiServices,\r
222 sizeof (VLV_POLICY_PPI),\r
223 (void **)&mVlvPolicyPpi\r
224 );\r
225 ASSERT_EFI_ERROR (Status);\r
226\r
227 //\r
228 // Initialize PPI\r
229 //\r
230 (*PeiServices)->SetMem ((VOID *)mVlvPolicyPpi, sizeof (VLV_POLICY_PPI), 0);\r
231 mVlvPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r
232 mVlvPolicyPpiDesc->Guid = &gVlvPolicyPpiGuid;\r
233 mVlvPolicyPpiDesc->Ppi = mVlvPolicyPpi;\r
234 mVlvPolicyPpi->GtConfig.PrimaryDisplay = SystemConfiguration->PrimaryVideoAdaptor;\r
235 mVlvPolicyPpi->GtConfig.IgdDvmt50PreAlloc = SystemConfiguration->IgdDvmt50PreAlloc;\r
236 mVlvPolicyPpi->GtConfig.ApertureSize = SystemConfiguration->IgdApertureSize;\r
237 mVlvPolicyPpi->GtConfig.GttSize = SystemConfiguration->GTTSize;\r
238 if (SystemConfiguration->PrimaryVideoAdaptor != 2) {\r
239 mVlvPolicyPpi->GtConfig.InternalGraphics = SystemConfiguration->Igd;\r
240 } else {\r
241 mVlvPolicyPpi->GtConfig.InternalGraphics = 0;\r
242 }\r
243\r
244\r
245 mVlvPolicyPpi->GtConfig.IgdTurboEn = 1;\r
246\r
247\r
248 mVlvPolicyPpi->PlatformData.FastBoot = SystemConfiguration->FastBoot;\r
249 mVlvPolicyPpi->PlatformData.DynSR = 1;\r
250 DEBUG ((EFI_D_ERROR, "Setup Option ISPEn: 0x%x\n", SystemConfiguration->ISPEn));\r
251 mVlvPolicyPpi->ISPEn = SystemConfiguration->ISPEn;\r
252 DEBUG ((EFI_D_ERROR, "Setup Option ISPDevSel: 0x%x\n", SystemConfiguration->ISPDevSel));\r
253 mVlvPolicyPpi->ISPPciDevConfig = SystemConfiguration->ISPDevSel;\r
254 if (SystemConfiguration->ISPEn == 0) {\r
255 mVlvPolicyPpi->ISPPciDevConfig = 0;\r
256 DEBUG ((EFI_D_ERROR, "Update Setup Option ISPDevSel: 0x%x\n", mVlvPolicyPpi->ISPPciDevConfig));\r
257 }\r
258 Status = (*PeiServices)->InstallPpi(\r
259 PeiServices,\r
260 mVlvPolicyPpiDesc\r
261 );\r
262 ASSERT_EFI_ERROR (Status);\r
263\r
264 return EFI_SUCCESS;\r
265}\r
266\r
267\r
268EFI_STATUS\r
269ConfigureSoCGpio (\r
270 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
271 )\r
272{\r
273\r
274 DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------start\n"));\r
275 if (SystemConfiguration->eMMCBootMode== 1) {// Auto detection mode\r
276 DEBUG ((EFI_D_ERROR, "Auto detection mode------------start\n"));\r
277\r
278 //\r
279 //Silicon Steppings\r
280 //\r
281 switch (PchStepping()) {\r
282 case PchA0: // SOC A0 and A1\r
283 case PchA1:\r
284 DEBUG ((EFI_D_ERROR, "SOC A0/A1: eMMC 4.41 GPIO Configuration\n"));\r
285 SystemConfiguration->LpsseMMCEnabled = 1;\r
286 SystemConfiguration->LpsseMMC45Enabled = 0;\r
287 break;\r
288 case PchB0: // SOC B0 and later\r
289 default:\r
290 DEBUG ((EFI_D_ERROR, "SOC B0 and later: eMMC 4.5 GPIO Configuration\n"));\r
291 SystemConfiguration->LpsseMMCEnabled = 0;\r
292 SystemConfiguration->LpsseMMC45Enabled = 1;\r
293 break;\r
294 }\r
295 } else if (SystemConfiguration->eMMCBootMode == 2) { // eMMC 4.41\r
296 DEBUG ((EFI_D_ERROR, "Force to eMMC 4.41 GPIO Configuration\n"));\r
297 SystemConfiguration->LpsseMMCEnabled = 1;\r
298 SystemConfiguration->LpsseMMC45Enabled = 0;\r
299 } else if (SystemConfiguration->eMMCBootMode == 3) { // eMMC 4.5\r
300 DEBUG ((EFI_D_ERROR, "Force to eMMC 4.5 GPIO Configuration\n"));\r
301 SystemConfiguration->LpsseMMCEnabled = 0;\r
302 SystemConfiguration->LpsseMMC45Enabled = 1;\r
303\r
304 } else { // Disable eMMC controllers\r
305 DEBUG ((EFI_D_ERROR, "Disable eMMC GPIO controllers\n"));\r
306 SystemConfiguration->LpsseMMCEnabled = 0;\r
307 SystemConfiguration->LpsseMMC45Enabled = 0;\r
308 }\r
309\r
310 /*\r
311 20.1.1 EMMC\r
312 SDMMC1_CLK - write 0x2003ED01 to IOBASE + 0x03E0\r
313 SDMMC1_CMD - write 0x2003EC81 to IOBASE + 0x0390\r
314 SDMMC1_D0 - write 0x2003EC81 to IOBASE + 0x03D0\r
315 SDMMC1_D1 - write 0x2003EC81 to IOBASE + 0x0400\r
316 SDMMC1_D2 - write 0x2003EC81 to IOBASE + 0x03B0\r
317 SDMMC1_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0360\r
318 MMC1_D4_SD_WE - write 0x2003EC81 to IOBASE + 0x0380\r
319 MMC1_D5 - write 0x2003EC81 to IOBASE + 0x03C0\r
320 MMC1_D6 - write 0x2003EC81 to IOBASE + 0x0370\r
321 MMC1_D7 - write 0x2003EC81 to IOBASE + 0x03F0\r
322 MMC1_RESET_B - write 0x2003ED01 to IOBASE + 0x0330\r
323 */\r
324 if (SystemConfiguration->LpsseMMCEnabled== 1) {\r
325 MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED01); //EMMC 4.41\r
326 MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC81);\r
327 MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC81);\r
328 MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC81);\r
329 MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC81);\r
330 MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC81);\r
331 MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC81);\r
332 MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC81);\r
333 MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC81);\r
334 MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC81);\r
335 MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED01);\r
336 }\r
337\r
338 /*\r
339 eMMC 4.5 controller\r
340 SDMMC1_CLK - write 0x2003ED03 to IOBASE + 0x03E0\r
341 SDMMC1_CMD - write 0x2003EC83 to IOBASE + 0x0390\r
342 SDMMC1_D0 - write 0x2003EC83 to IOBASE + 0x03D0\r
343 SDMMC1_D1 - write 0x2003EC83 to IOBASE + 0x0400\r
344 SDMMC1_D2 - write 0x2003EC83 to IOBASE + 0x03B0\r
345 SDMMC1_D3_CD_B - write 0x2003EC83 to IOBASE + 0x0360\r
346 MMC1_D4_SD_WE - write 0x2003EC83 to IOBASE + 0x0380\r
347 MMC1_D5 - write 0x2003EC83 to IOBASE + 0x03C0\r
348 MMC1_D6 - write 0x2003EC83 to IOBASE + 0x0370\r
349 MMC1_D7 - write 0x2003EC83 to IOBASE + 0x03F0\r
350 MMC1_RESET_B - write 0x2003ED03 to IOBASE + 0x0330\r
351 */\r
352 if (SystemConfiguration->LpsseMMC45Enabled== 1) {\r
353 MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED03); // EMMC 4.5\r
354 MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC83);\r
355 MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC83);\r
356 MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC83);\r
357 MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC83);\r
358 MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC83);\r
359 MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC83);\r
360 MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC83);\r
361 MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC83);\r
362 MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC83);\r
363 MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED03);\r
364\r
365 }\r
366\r
367//\r
368// Change GPIOC_0 setting to allow MMIO access under Android.\r
369//\r
370 IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL,\r
371 (IoRead32(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL) & (UINT32)~BIT0));\r
372 DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------end\n"));\r
373 return EFI_SUCCESS;\r
374}\r
375\r
376EFI_STATUS\r
377MeasuredBootInit (\r
378 IN CONST EFI_PEI_SERVICES **PeiServices,\r
379 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
380 )\r
381{\r
382 if (SystemConfiguration->MeasuredBootEnable) {\r
383 PcdSetBool (PcdMeasuredBootEnable, TRUE);\r
384 } else {\r
385 PcdSetBool (PcdMeasuredBootEnable, FALSE);\r
386 }\r
387\r
388 return EFI_SUCCESS;\r
389}\r
390\r
391\r
392EFI_STATUS\r
393ConfigureLpssAndSccGpio (\r
394 IN SYSTEM_CONFIGURATION *SystemConfiguration,\r
395 IN EFI_PLATFORM_INFO_HOB *PlatformInfo\r
396 )\r
397{\r
398 /*One time configuration to each GPIO controller PSB_CONF register should be done before starting pad configuration:\r
399 GPIO SCORE - write 0x01001002 to IOBASE + 0x0700\r
400 GPIO NCORE - write 0x01001002 to IOBASE + 0x0F00\r
401 GPIO SSUS - write 0x01001002 to IOBASE + 0x1700\r
402 */\r
403 DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------start\n"));\r
404\r
405 /*\r
406 19.1.1 PWM0\r
407 PWM0 - write 0x2003CD01 to IOBASE + 0x00A0\r
408 19.1.2 PWM1\r
409 PWM0 - write 0x2003CD01 to IOBASE + 0x00B0\r
410 */\r
411 if (SystemConfiguration->LpssPwm0Enabled== 1) {\r
412 MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD01);\r
413 } else if (SystemConfiguration->LpssPwm0Enabled== 0) {\r
414 MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD00);\r
415 }\r
416\r
417 if (SystemConfiguration->LpssPwm1Enabled== 1) {\r
418 MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CC01);\r
419 } else if (SystemConfiguration->LpssPwm1Enabled== 0) {\r
420 MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CD00);\r
421 }\r
422\r
423 /*\r
424 19.1.3 UART1\r
425 UART1_RXD-L - write 0x2003CC81 to IOBASE + 0x0020\r
426 UART1_TXD-0 - write 0x2003CC81 to IOBASE + 0x0010\r
427 UART1_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0000\r
428 UART1_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0040\r
429 */\r
430 if (SystemConfiguration->LpssHsuart0Enabled== 1) {\r
431 MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC81); // uart1\r
432 MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC81);\r
433 if (SystemConfiguration->LpssHsuart0FlowControlEnabled== 0) {\r
434 DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[0]\n"));\r
435 MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC80);\r
436 MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC80);\r
437 } else {\r
438 DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[1]\n"));\r
439 MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC81);\r
440 MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC01);//W/A HSD 4752617 0x2003CC81\r
441 }\r
442 } else if (SystemConfiguration->LpssHsuart0Enabled== 0) {\r
443 MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC80); // uart1\r
444 MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC80);\r
445 }\r
446\r
447\r
448 /*\r
449 19.1.4 UART2\r
450 UART2_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0090\r
451 UART2_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0080\r
452 UART2_RXD-H - write 0x2003CC81 to IOBASE + 0x0060\r
453 UART2_TXD-0 - write 0x2003CC81 to IOBASE + 0x0070\r
454 */\r
455 if (SystemConfiguration->LpssHsuart1Enabled== 1) {\r
456 MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC81);\r
457 MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC81);\r
458\r
459 if (SystemConfiguration->LpssHsuart1FlowControlEnabled== 0) {\r
460 DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[0]\n"));\r
461 MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC80); // UART2_RTS_B\r
462 MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC80); // UART2_CTS_B\r
463 } else {\r
464 DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[1]\n"));\r
465 MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC81); // uart2\r
466 MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC01); //W/A HSD 4752617 0x2003CC81\r
467 }\r
468 } else if (SystemConfiguration->LpssHsuart1Enabled== 0) {\r
469 MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC80);\r
470 MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC80);\r
471 }\r
472\r
473 /*\r
474 19.1.5 SPI\r
475 SPI1_CS0_B - write 0x2003CC81 to IOBASE + 0x0110\r
476 SPI1_CLK - write 0x2003CD01 to IOBASE + 0x0100\r
477 SPI1_MOSI - write 0x2003CC81 to IOBASE + 0x0130\r
478 SPI1_MISO - write 0x2003CC81 to IOBASE + 0x0120\r
479 */\r
480 if (SystemConfiguration->LpssSpiEnabled== 1) {\r
481 MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003CC81); // SPI\r
482 MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003CD01);\r
483 MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003CC81);\r
484 MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003CC81);\r
485 } else if (SystemConfiguration->LpssSpiEnabled== 0) {\r
486 MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003cc80);\r
487 MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003cc80);\r
488 MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003cc80);\r
489 MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003cc80);\r
490 }\r
491\r
492 /*\r
493 19.1.6 I2C0\r
494 I2C0_SDA-OD-O - write 0x2003CC81 to IOBASE + 0x0210\r
495 I2C0_SCL-OD-O - write 0x2003CC81 to IOBASE + 0x0200\r
496 */\r
497 if (SystemConfiguration->LpssI2C0Enabled== 1) {\r
498 MmioWrite32 (IO_BASE_ADDRESS + 0x0210, 0x2003C881);\r
499 MmioWrite32 (IO_BASE_ADDRESS + 0x0200, 0x2003C881);\r
500 }\r
501 /*\r
502 19.1.7 I2C1\r
503 I2C1_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01F0\r
504 I2C1_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01E0\r
505 */\r
506\r
507 if (SystemConfiguration->LpssI2C1Enabled== 1) {\r
508 MmioWrite32 (IO_BASE_ADDRESS + 0x01F0, 0x2003C881);\r
509 MmioWrite32 (IO_BASE_ADDRESS + 0x01E0, 0x2003C881);\r
510 }\r
511 /*\r
512 19.1.8 I2C2\r
513 I2C2_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01D0\r
514 I2C2_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01B0\r
515 */\r
516 if (SystemConfiguration->LpssI2C2Enabled== 1) {\r
517 MmioWrite32 (IO_BASE_ADDRESS + 0x01D0, 0x2003C881);\r
518 MmioWrite32 (IO_BASE_ADDRESS + 0x01B0, 0x2003C881);\r
519 }\r
520 /*\r
521 19.1.9 I2C3\r
522 I2C3_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0190\r
523 I2C3_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01C0\r
524 */\r
525 if (SystemConfiguration->LpssI2C3Enabled== 1) {\r
526 MmioWrite32 (IO_BASE_ADDRESS + 0x0190, 0x2003C881);\r
527 MmioWrite32 (IO_BASE_ADDRESS + 0x01C0, 0x2003C881);\r
528 }\r
529 /*\r
530 19.1.10 I2C4\r
531 I2C4_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01A0\r
532 I2C4_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0170\r
533 */\r
534 if (SystemConfiguration->LpssI2C4Enabled== 1) {\r
535 MmioWrite32 (IO_BASE_ADDRESS + 0x01A0, 0x2003C881);\r
536 MmioWrite32 (IO_BASE_ADDRESS + 0x0170, 0x2003C881);\r
537 }\r
538 /*\r
539 19.1.11 I2C5\r
540 I2C5_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0150\r
541 I2C5_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0140\r
542 */\r
543 //touch 1.7M support on i2c5(from 0) need 2k PULL-UP.\r
544 if (SystemConfiguration->LpssI2C5Enabled== 1) {\r
545 MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C881);\r
546 MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C881);\r
547 } else if(SystemConfiguration->LpssI2C5Enabled== 0) {\r
548 MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C880);\r
549 MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C880);\r
550 }\r
551 /*\r
552 19.1.12 I2C6\r
553 I2C6_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0180\r
554 I2C6_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0160\r
555 */\r
556 if (SystemConfiguration->LpssI2C6Enabled== 1) {\r
557 MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C881);\r
558 MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C881);\r
559 } else if (SystemConfiguration->LpssI2C6Enabled== 0) {\r
560 MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C880);\r
561 MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C880);\r
562 }\r
563\r
564\r
565 /*\r
566 20.1.2 SDIO\r
567 SDMMC2_CLK - write 0x2003ED01 to IOBASE + 0x0320\r
568 SDMMC2_CMD - write 0x2003EC81 to IOBASE + 0x0300\r
569 SDMMC2_D0 - write 0x2003EC81 to IOBASE + 0x0350\r
570 SDMMC2_D1 - write 0x2003EC81 to IOBASE + 0x02F0\r
571 SDMMC2_D2 - write 0x2003EC81 to IOBASE + 0x0340\r
572 SDMMC2_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0310\r
573 */\r
574 if (SystemConfiguration->LpssSdioEnabled== 1) {\r
575 MmioWrite32 (IO_BASE_ADDRESS + 0x0320, 0x2003ED01);//SDIO\r
576 MmioWrite32 (IO_BASE_ADDRESS + 0x0300, 0x2003EC81);\r
577 MmioWrite32 (IO_BASE_ADDRESS + 0x0350, 0x2003EC81);\r
578 MmioWrite32 (IO_BASE_ADDRESS + 0x02F0, 0x2003EC81);\r
579 MmioWrite32 (IO_BASE_ADDRESS + 0x0340, 0x2003EC81);\r
580 MmioWrite32 (IO_BASE_ADDRESS + 0x0310, 0x2003EC81);\r
581 }\r
582\r
583 /*\r
584 20.1.3 SD Card\r
585 SDMMC3_1P8_EN - write 0x2003CD01 to IOBASE + 0x03F0\r
586 SDMMC3_CD_B - write 0x2003CC81 to IOBASE + 0x03A0\r
587 SDMMC3_CLK - write 0x2003CD01 to IOBASE + 0x02B0\r
588 SDMMC3_CMD - write 0x2003CC81 to IOBASE + 0x02C0\r
589 SDMMC3_D0 - write 0x2003CC81 to IOBASE + 0x02E0\r
590 SDMMC3_D1 - write 0x2003CC81 to IOBASE + 0x0290\r
591 SDMMC3_D2 - write 0x2003CC81 to IOBASE + 0x02D0\r
592 SDMMC3_D3 - write 0x2003CC81 to IOBASE + 0x02A0\r
593 SDMMC3_PWR_EN_B - write 0x2003CC81 to IOBASE + 0x0690\r
594 SDMMC3_WP - write 0x2003CC82 to IOBASE + 0x0160\r
595 */\r
596 if (SystemConfiguration->LpssSdcardEnabled == 1) {\r
597 if (!((PlatformInfo->BoardId == BOARD_ID_BL_FFRD && PlatformInfo->BoardRev== PR11) && (SystemConfiguration->CfioPnpSettings == 1))) {\r
598 MmioWrite32 (IO_BASE_ADDRESS + 0x05F0, 0x2003CD01);//SDCARD\r
599 MmioWrite32 (IO_BASE_ADDRESS + 0x02B0, 0x2003CD01);\r
600 MmioWrite32 (IO_BASE_ADDRESS + 0x02C0, 0x2003CC81);\r
601 MmioWrite32 (IO_BASE_ADDRESS + 0x02E0, 0x2003CC81);\r
602 MmioWrite32 (IO_BASE_ADDRESS + 0x0290, 0x2003CC81);\r
603 MmioWrite32 (IO_BASE_ADDRESS + 0x02D0, 0x2003CC81);\r
604 MmioWrite32 (IO_BASE_ADDRESS + 0x02A0, 0x2003CC81);\r
605 MmioWrite32 (IO_BASE_ADDRESS + 0x0690, 0x2003CC81);\r
606 MmioWrite32 (IO_BASE_ADDRESS + 0x0650, 0x2003CC82); //GPIOC_7 set to WP Pin\r
607 }\r
608 }\r
609\r
610\r
611 DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------end\n"));\r
612 return EFI_SUCCESS;\r
613}\r
614\r
615EFI_STATUS\r
616ConfigureLpeGpio (\r
617 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
618 )\r
619{\r
620 DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------start\n"));\r
621\r
622 if (SystemConfiguration->PchAzalia == 0) {\r
623 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x220, (UINT32)~(0x7), (UINT32) (0x01));\r
624 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x250, (UINT32)~(0x7), (UINT32) (0x01));\r
625 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x240, (UINT32)~(0x7), (UINT32) (0x01));\r
626 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x260, (UINT32)~(0x7), (UINT32) (0x01));\r
627 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x270, (UINT32)~(0x7), (UINT32) (0x01));\r
628 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x230, (UINT32)~(0x7), (UINT32) (0x01));\r
629 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x280, (UINT32)~(0x7), (UINT32) (0x01));\r
630 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x540, (UINT32)~(0x7), (UINT32) (0x01));\r
631 }\r
632\r
633 DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------end\n"));\r
634\r
635 return EFI_SUCCESS;\r
636}\r
637\r
638EFI_STATUS\r
639ConfigureSciSmiGpioRout (\r
640 IN EFI_PLATFORM_INFO_HOB *PlatformInfo)\r
641{\r
642 UINT32 GPI_Routing;\r
643\r
644 GPI_Routing = MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT);\r
645\r
646 //\r
647 // For FAB3, Route GPIO_CORE 0 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI\r
648 //\r
649 if(PlatformInfo->BoardRev == 3) {\r
650 GPI_Routing = GPI_Routing & 0xfffc3ffc;\r
651 GPI_Routing = GPI_Routing | 0x00024002;\r
652 }\r
653\r
654 //\r
655 // For FAB2/1, Route GPIO_CORE 7 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI\r
656 //\r
657 else {\r
658 GPI_Routing = GPI_Routing & 0x3fff3ffc;\r
659 GPI_Routing = GPI_Routing | 0x80004002;\r
660 }\r
661 MmioWrite32((PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT), GPI_Routing);\r
662\r
663 return EFI_SUCCESS;\r
664}\r
665\r
666EFI_STATUS\r
667ConfigureMipiCsi (\r
668 VOID)\r
669{\r
670 //\r
671 //Configure the platform clock for MIPI-CSI usage\r
672 //PLT_CLK0\r
673 //\r
674 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x6a0, (UINT32)~(0x7), (UINT32) (0x01));\r
675\r
676 //\r
677 //PLT_CLK1\r
678 //\r
679 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x570, (UINT32)~(0x7), (UINT32) (0x01));\r
680\r
681 //\r
682 //PLT_CLK2\r
683 //\r
684 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x5B0, (UINT32)~(0x7), (UINT32) (0x01));\r
685\r
686 return EFI_SUCCESS;\r
687}\r
688\r
689EFI_STATUS\r
690ConfigureUSBULPI (\r
691 VOID)\r
692{\r
693 //\r
694 //Configure USB ULPI\r
695 //USB_ULPI_0_CLK\r
696 //\r
697 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x338, (UINT32)~(0x7), (UINT32) (GPI));\r
698 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x330, (UINT32)~(0x187), (UINT32) (0x101));\r
699\r
700 //\r
701 //USB_ULPI_0_DATA0\r
702 //\r
703 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x388, (UINT32)~(0x7), (UINT32) (GPI));\r
704 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x380, (UINT32)~(0x187), (UINT32) (0x101));\r
705\r
706 //\r
707 //USB_ULPI_0_DATA1\r
708 //\r
709 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x368, (UINT32)~(0x7), (UINT32) (GPI));\r
710 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x360, (UINT32)~(0x187), (UINT32) (0x101));\r
711\r
712 //\r
713 //USB_ULPI_0_DATA2\r
714 //\r
715 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x318, (UINT32)~(0x7), (UINT32) (GPI));\r
716 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x310, (UINT32)~(0x187), (UINT32) (0x101));\r
717\r
718 //\r
719 //USB_ULPI_0_DATA3\r
720 //\r
721 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x378, (UINT32)~(0x7), (UINT32) (GPI));\r
722 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x370, (UINT32)~(0x187), (UINT32) (0x101));\r
723\r
724 //\r
725 //USB_ULPI_0_DATA4\r
726 //\r
727 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x308, (UINT32)~(0x7), (UINT32) (GPI));\r
728 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x300, (UINT32)~(0x187), (UINT32) (0x101));\r
729\r
730 //\r
731 //USB_ULPI_0_DATA5\r
732 //\r
733 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x398, (UINT32)~(0x7), (UINT32) (GPI));\r
734 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x390, (UINT32)~(0x187), (UINT32) (0x101));\r
735\r
736 //\r
737 //USB_ULPI_0_DATA6\r
738 //\r
739 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x328, (UINT32)~(0x7), (UINT32) (GPI));\r
740 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x320, (UINT32)~(0x187), (UINT32) (0x101));\r
741\r
742 //\r
743 //USB_ULPI_0_DATA7\r
744 //\r
745 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a8, (UINT32)~(0x7), (UINT32) (GPI));\r
746 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a0, (UINT32)~(0x187), (UINT32) (0x101));\r
747\r
748 //\r
749 //USB_ULPI_0_DIR\r
750 //\r
751 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x348, (UINT32)~(0x7), (UINT32) (GPI));\r
752 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x340, (UINT32)~(0x187), (UINT32) (0x81));\r
753\r
754 //\r
755 //USB_ULPI_0_NXT\r
756 //\r
757 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x358, (UINT32)~(0x7), (UINT32) (GPI));\r
758 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x350, (UINT32)~(0x187), (UINT32) (0x101));\r
759\r
760 //\r
761 //USB_ULPI_0_STP\r
762 //\r
763 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b8, (UINT32)~(0x7), (UINT32) (GPI));\r
764 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b0, (UINT32)~(0x187), (UINT32) (0x81));\r
765\r
766 //\r
767 //USB_ULPI_0_REFCLK\r
768 //\r
769 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x288, (UINT32)~(0x7), (UINT32) (GPI));\r
770 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x280, (UINT32)~(0x187), (UINT32) (0x101));\r
771\r
772 return EFI_SUCCESS;\r
773}\r
774\r
775EFI_STATUS\r
776DisableRTD3 (\r
777 VOID)\r
778{\r
779 //\r
780 //Disable RTD3\r
781 //\r
782 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x210, (UINT32)~(0x0f000007), (UINT32) (0x00));\r
783 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x1e0, (UINT32)~(0x0f000007), (UINT32) (0x00));\r
784\r
785 return EFI_SUCCESS;\r
786}\r
787\r
788/**\r
789 Platform specific initializations in stage1.\r
790\r
791 @param FfsHeader Pointer to the PEIM FFS file header.\r
792 @param PeiServices General purpose services available to every PEIM.\r
793\r
794 @retval EFI_SUCCESS Operation completed successfully.\r
795 @retval Otherwise Platform initialization failed.\r
796**/\r
797EFI_STATUS\r
798EFIAPI\r
799PlatformEarlyInitEntry (\r
800\r
801 IN EFI_PEI_FILE_HANDLE FileHandle,\r
802 IN CONST EFI_PEI_SERVICES **PeiServices\r
803 )\r
804{\r
805 EFI_STATUS Status;\r
806 SYSTEM_CONFIGURATION SystemConfiguration;\r
807 EFI_PLATFORM_INFO_HOB *PlatformInfo;\r
808 EFI_PEI_HOB_POINTERS Hob;\r
809 EFI_PLATFORM_CPU_INFO PlatformCpuInfo;\r
810\r
811 //\r
812 // Initialize SmbusPolicy PPI\r
813 //\r
814 Status = (*PeiServices)->InstallPpi(PeiServices, &mInstallSmbusPolicyPpi);\r
815 ASSERT_EFI_ERROR (Status);\r
816\r
817 //\r
818 // Initialize Stall PPIs\r
819 //\r
820 Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi);\r
821 ASSERT_EFI_ERROR (Status);\r
822\r
823 //\r
824 // Initialize platform PPIs\r
825 //\r
826 Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallSpeakerInterfacePpi);\r
827 ASSERT_EFI_ERROR (Status);\r
828\r
829 //\r
830 // Variable initialization\r
831 //\r
832 ZeroMem(&PlatformCpuInfo, sizeof(EFI_PLATFORM_CPU_INFO));\r
833\r
834 //\r
835 // Set the some PCI and chipset range as UC\r
836 // And align to 1M at leaset\r
837 //\r
838 Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r
839 ASSERT (Hob.Raw != NULL);\r
840 PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);\r
841\r
842 //\r
843 // Initialize PlatformInfo HOB\r
844 //\r
845 MultiPlatformInfoInit(PeiServices, PlatformInfo);\r
846\r
847 //\r
848 // Do basic MCH init\r
849 //\r
850 MchInit (PeiServices);\r
851\r
852 //\r
853 // Set the new boot mode\r
854 //\r
855 Status = UpdateBootMode (PeiServices, PlatformInfo);\r
856 ASSERT_EFI_ERROR (Status);\r
857\r
858 SetPlatformBootMode (PeiServices, PlatformInfo);\r
859\r
860 //\r
861 // Get setup variable. This can only be done after BootMode is updated\r
862 //\r
863 GetSetupVariable (PeiServices, &SystemConfiguration);\r
864\r
865 CheckOsSelection(PeiServices, &SystemConfiguration);\r
866\r
867 //\r
868 // Update PlatformInfo HOB according to setup variable\r
869 //\r
870 PlatformInfoUpdate(PeiServices, PlatformInfo, &SystemConfiguration);\r
871\r
872 InitializePlatform (PeiServices, PlatformInfo, &SystemConfiguration);\r
873\r
874 //\r
875 // Initialize VlvPolicy PPI\r
876 //\r
877 Status = VlvPolicyInit (PeiServices, &SystemConfiguration);\r
878 ASSERT_EFI_ERROR (Status);\r
879\r
880 //\r
881 // Soc specific GPIO setting\r
882 //\r
883 ConfigureSoCGpio(&SystemConfiguration);\r
884\r
885 //\r
886 // Baylake Board specific.\r
887 //\r
888 if (PlatformInfo->BoardId == BOARD_ID_BL_RVP ||\r
889 PlatformInfo->BoardId == BOARD_ID_BL_FFRD ||\r
890 PlatformInfo->BoardId == BOARD_ID_BL_FFRD8 ||\r
891 PlatformInfo->BoardId == BOARD_ID_BL_RVP_DDR3L ||\r
892 PlatformInfo->BoardId == BOARD_ID_BL_STHI ||\r
893 PlatformInfo->BoardId == BOARD_ID_BB_RVP ||\r
894 PlatformInfo->BoardId == BOARD_ID_BS_RVP ||\r
895 PlatformInfo->BoardId == BOARD_ID_MINNOW2 ||\r
896 PlatformInfo->BoardId == BOARD_ID_CVH) {\r
897 ConfigureLpssAndSccGpio(&SystemConfiguration, PlatformInfo);\r
898\r
899 }\r
900\r
901\r
902 //\r
903 // Configure LPE\r
904 // Alpine Valley and Bayley Bay board specific\r
905 //\r
906 ConfigureLpeGpio(&SystemConfiguration);\r
907\r
908 //\r
909 // Bayley Bay Board specific.\r
910 //\r
911 ConfigureSciSmiGpioRout(PlatformInfo);\r
912 if (SystemConfiguration.LpssI2C3Enabled == 1) {\r
913 ConfigureMipiCsi();\r
914 }\r
915\r
916\r
917 //\r
918 // Do basic CPU init\r
919 //\r
920 Status = PlatformCpuInit (PeiServices, &SystemConfiguration, &PlatformCpuInfo);\r
921\r
922 //\r
923 // Perform basic SSA related platform initialization\r
924 //\r
925 PlatformSsaInit (&SystemConfiguration,PeiServices);\r
926\r
927\r
928 //\r
929 // Do basic PCH init\r
930 //\r
931 Status = PlatformPchInit (&SystemConfiguration, PeiServices, PlatformInfo->PlatformType);\r
932 ASSERT_EFI_ERROR (Status);\r
933\r
934 //\r
935 // Initialize platform PPIs\r
936 //\r
937 Status = (*PeiServices)->InstallPpi (PeiServices, &mPpiList[0]);\r
938 ASSERT_EFI_ERROR (Status);\r
939\r
940 if (PlatformInfo->BoardId != BOARD_ID_CVH) {\r
941 InstallPlatformClocksNotify (PeiServices);\r
942 InstallPlatformSysCtrlGPIONotify(PeiServices);\r
943 }\r
944\r
945 //\r
946 // Initialize platform PPIs\r
947 //\r
948 Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);\r
949 ASSERT_EFI_ERROR (Status);\r
950\r
951 //\r
952 // Initialize Measured Boot\r
953 //\r
954 Status = MeasuredBootInit (PeiServices, &SystemConfiguration);\r
955 ASSERT_EFI_ERROR (Status);\r
956\r
957 return Status;\r
958}\r
959\r
960/**\r
961\r
962 Return the mainblockcompact Fv.\r
963\r
964 @param FvNumber Our enumeration of the firmware volumes we care about.\r
965\r
966 @param FvAddress Base Address of the memory containing the firmware volume\r
967\r
968 @retval EFI_SUCCESS\r
969 @retval EFI_NOT_FOUND\r
970\r
971**/\r
972EFI_STATUS\r
973EFIAPI\r
974FindFv (\r
975 IN EFI_PEI_FIND_FV_PPI *This,\r
976 IN CONST EFI_PEI_SERVICES **PeiServices,\r
977 IN OUT UINT8 *FvNumber,\r
978 OUT EFI_FIRMWARE_VOLUME_HEADER **FVAddress\r
979 )\r
980{\r
981 //\r
982 // At present, we only have one Fv to search\r
983 //\r
984 if (*FvNumber == 0) {\r
985 *FvNumber = 1;\r
986 *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FixedPcdGet32 (PcdFlashFvMainBase);\r
987 return EFI_SUCCESS;\r
988 }\r
989 else if (*FvNumber == 1) {\r
990 *FvNumber = 2;\r
991 *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FixedPcdGet32 (PcdFlashFvRecovery2Base);\r
992 return EFI_SUCCESS;\r
993 }\r
994 else { // Not the one Fv we care about\r
995 return EFI_NOT_FOUND;\r
996 }\r
997}\r
998\r
999EFI_STATUS\r
1000EFIAPI\r
1001CpuOnlyReset (\r
1002 IN CONST EFI_PEI_SERVICES **PeiServices\r
1003 )\r
1004{\r
1005// MsgBus32Write(CDV_UNIT_PUNIT, PUNIT_CPU_RST, 0x01)\r
1006#ifdef __GNUC__\r
1007 __asm__\r
1008 (\r
1009 "xorl %ecx, %ecx\n"\r
1010 "1:hlt; hlt; hlt\n"\r
1011 "jmp 1b\n"\r
1012 );\r
1013#else\r
1014 _asm {\r
1015 xor ecx, ecx\r
1016 HltLoop:\r
1017 hlt\r
1018 hlt\r
1019 hlt\r
1020 loop HltLoop\r
1021 }\r
1022#endif\r
1023 //\r
1024 // If we get here we need to mark it as a failure.\r
1025 //\r
1026 return EFI_UNSUPPORTED;\r
1027}\r
1028\r
1029\r
1030#ifdef __GNUC__\r
1031#pragma GCC pop_options\r
1032#else\r
1033#pragma optimize ("", on)\r
1034#endif\r
EFI Development Kit II mirror for PVE