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3cbfba02
DW		 1/** @file\r
2\r
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
4 \r\r
5 This program and the accompanying materials are licensed and made available under\r\r
6 the terms and conditions of the BSD License that accompanies this distribution. \r\r
7 The full text of the license may be found at \r\r
8 http://opensource.org/licenses/bsd-license.php. \r\r
9 \r\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r
12 \r\r
13\r
14\r
15Module Name:\r
16\r
17 PlatformEarlyInit.c\r
18\r
19Abstract:\r
20\r
21 Do platform specific PEI stage initializations.\r
22\r
23--*/\r
24\r
25\r
26#include "PlatformEarlyInit.h"\r
27\r
28#ifdef __GNUC__\r
29#pragma GCC push_options\r
30#pragma GCC optimize ("O0")\r
31#else\r
32#pragma optimize ("", off)\r
33#endif\r
34\r
35\r
36\r
37static EFI_PEI_STALL_PPI mStallPpi = {\r
38 PEI_STALL_RESOLUTION,\r
39 Stall\r
40};\r
41\r
42static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi = {\r
43 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
44 &gEfiPeiStallPpiGuid,\r
45 &mStallPpi\r
46};\r
47\r
48//\r
49// The reserved SMBus addresses are defined in PlatformDxe.h file.\r
50//\r
51static UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;\r
52static PEI_SMBUS_POLICY_PPI mSmbusPolicyPpi = {\r
53 SMBUS_BASE_ADDRESS,\r
54 SMBUS_BUS_DEV_FUNC,\r
55 PLATFORM_NUM_SMBUS_RSVD_ADDRESSES,\r
56 mSmbusRsvdAddresses\r
57};\r
58\r
59static EFI_PEI_PPI_DESCRIPTOR mInstallSmbusPolicyPpi = {\r
60 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
61 &gPeiSmbusPolicyPpiGuid,\r
62 &mSmbusPolicyPpi\r
63};\r
64static PEI_SPEAKER_IF_PPI mSpeakerInterfacePpi = {\r
65 ProgramToneFrequency,\r
66 GenerateBeepTone\r
67};\r
68\r
69static EFI_PEI_PPI_DESCRIPTOR mInstallSpeakerInterfacePpi = {\r
70 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
71 &gPeiSpeakerInterfacePpiGuid,\r
72 &mSpeakerInterfacePpi\r
73};\r
74\r
75static EFI_PEI_RESET_PPI mResetPpi = { IchReset };\r
76\r
77\r
78static EFI_PEI_FIND_FV_PPI mEfiFindFvPpi = {\r
79 (EFI_PEI_FIND_FV_FINDFV)FindFv\r
80};\r
81\r
82static EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {\r
83 {\r
84 EFI_PEI_PPI_DESCRIPTOR_PPI,\r
85 &gEfiPeiMasterBootModePpiGuid,\r
86 NULL\r
87 },\r
88 {\r
89 EFI_PEI_PPI_DESCRIPTOR_PPI,\r
90 &gEfiPeiResetPpiGuid,\r
91 &mResetPpi\r
92 },\r
93 {\r
94 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
95 &gEfiFindFvPpiGuid,\r
96 &mEfiFindFvPpi\r
97 }\r
98};\r
99\r
100static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {\r
101 {\r
102 EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,\r
103 &gEfiEndOfPeiSignalPpiGuid,\r
104 (EFI_PEIM_NOTIFY_ENTRY_POINT)EndOfPeiPpiNotifyCallback\r
105 },\r
106 {\r
107 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
108 &gEfiPeiMemoryDiscoveredPpiGuid,\r
109 (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotifyCallback\r
110 }\r
111\r
112};\r
113\r
114\r
115/**\r
116\r
117 Parse the status registers for figuring out the wake-up event and save it into\r
118 an GUID HOB which will be referenced later. However, modification is required\r
119 to meet the chipset register definition and the practical hardware design. Thus,\r
120 this is just an example.\r
121\r
122\r
123 @param PeiServices pointer to the PEI Service Table\r
124 @param EFI_SUCCESS Always return Success\r
125\r
126 @retval None\r
127\r
128\r
129**/\r
130EFI_STATUS\r
131EFIAPI\r
132GetWakeupEventAndSaveToHob (\r
133 IN CONST EFI_PEI_SERVICES **PeiServices\r
134 )\r
135{\r
136 UINT16 Pm1Sts;\r
137 UINTN Gpe0Sts;\r
138 UINTN WakeEventData;\r
139\r
140 //\r
141 // Read the ACPI registers\r
142 //\r
143 Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);\r
144 Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS);\r
145\r
146 //\r
147 // Figure out the wake-up event\r
148 //\r
149 if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) != 0) {\r
150 WakeEventData = SMBIOS_WAKEUP_TYPE_POWER_SWITCH;\r
151 } else if (((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) != 0)) {\r
152 WakeEventData = SMBIOS_WAKEUP_TYPE_PCI_PME;\r
153 } else if (Gpe0Sts != 0) {\r
154 WakeEventData = SMBIOS_WAKEUP_TYPE_OTHERS;\r
155 } else {\r
156 WakeEventData = SMBIOS_WAKEUP_TYPE_UNKNOWN;\r
157 }\r
158\r
159 DEBUG ((EFI_D_ERROR, "ACPI Wake Status Register: %04x\n", Pm1Sts));\r
160\r
161 return EFI_SUCCESS;\r
162}\r
163\r
164EFI_STATUS\r
165GetSetupVariable (\r
166 IN CONST EFI_PEI_SERVICES **PeiServices,\r
167 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
168 )\r
169{\r
170 UINTN VariableSize;\r
171 EFI_STATUS Status;\r
172 EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;\r
173\r
174 VariableSize = sizeof (SYSTEM_CONFIGURATION);\r
175 ZeroMem (SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));\r
176\r
177 Status = (*PeiServices)->LocatePpi (\r
178 PeiServices,\r
179 &gEfiPeiReadOnlyVariable2PpiGuid,\r
180 0,\r
181 NULL,\r
182 (void **)&Variable\r
183 );\r
184 ASSERT_EFI_ERROR (Status);\r
185\r
186 //\r
187 // Use normal setup default from NVRAM variable,\r
188 // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.\r
189 //\r
190 VariableSize = sizeof(SYSTEM_CONFIGURATION);\r
191 Status = Variable->GetVariable (\r
192 Variable,\r
193 L"Setup",\r
194 &gEfiSetupVariableGuid,\r
195 NULL,\r
196 &VariableSize,\r
197 SystemConfiguration\r
198 );\r
620f2891
TH		 199 if (EFI_ERROR (Status) || VariableSize != sizeof(SYSTEM_CONFIGURATION)) {\r
200 //The setup variable is corrupted\r
201 VariableSize = sizeof(SYSTEM_CONFIGURATION);\r
202 Status = Variable->GetVariable(\r
203 Variable,\r
204 L"SetupRecovery",\r
205 &gEfiSetupVariableGuid,\r
206 NULL,\r
207 &VariableSize,\r
208 SystemConfiguration\r
209 );\r
210 ASSERT_EFI_ERROR (Status);\r
211 } \r
3cbfba02
DW		 212 return Status;\r
213}\r
214\r
215EFI_STATUS\r
216VlvPolicyInit (\r
217 IN CONST EFI_PEI_SERVICES **PeiServices,\r
218 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
219 )\r
220{\r
221 EFI_STATUS Status;\r
222 EFI_PEI_PPI_DESCRIPTOR *mVlvPolicyPpiDesc;\r
223 VLV_POLICY_PPI *mVlvPolicyPpi;\r
224\r
225 Status = (*PeiServices)->AllocatePool(\r
226 PeiServices,\r
227 sizeof (EFI_PEI_PPI_DESCRIPTOR),\r
228 (void **)&mVlvPolicyPpiDesc\r
229 );\r
230 ASSERT_EFI_ERROR (Status);\r
231\r
232 Status = (*PeiServices)->AllocatePool(\r
233 PeiServices,\r
234 sizeof (VLV_POLICY_PPI),\r
235 (void **)&mVlvPolicyPpi\r
236 );\r
237 ASSERT_EFI_ERROR (Status);\r
238\r
239 //\r
240 // Initialize PPI\r
241 //\r
242 (*PeiServices)->SetMem ((VOID *)mVlvPolicyPpi, sizeof (VLV_POLICY_PPI), 0);\r
243 mVlvPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r
244 mVlvPolicyPpiDesc->Guid = &gVlvPolicyPpiGuid;\r
245 mVlvPolicyPpiDesc->Ppi = mVlvPolicyPpi;\r
246 mVlvPolicyPpi->GtConfig.PrimaryDisplay = SystemConfiguration->PrimaryVideoAdaptor;\r
247 mVlvPolicyPpi->GtConfig.IgdDvmt50PreAlloc = SystemConfiguration->IgdDvmt50PreAlloc;\r
248 mVlvPolicyPpi->GtConfig.ApertureSize = SystemConfiguration->IgdApertureSize;\r
249 mVlvPolicyPpi->GtConfig.GttSize = SystemConfiguration->GTTSize;\r
250 if (SystemConfiguration->PrimaryVideoAdaptor != 2) {\r
251 mVlvPolicyPpi->GtConfig.InternalGraphics = SystemConfiguration->Igd;\r
252 } else {\r
253 mVlvPolicyPpi->GtConfig.InternalGraphics = 0;\r
254 }\r
255\r
256\r
257 mVlvPolicyPpi->GtConfig.IgdTurboEn = 1;\r
258\r
259\r
260 mVlvPolicyPpi->PlatformData.FastBoot = SystemConfiguration->FastBoot;\r
261 mVlvPolicyPpi->PlatformData.DynSR = 1;\r
262 DEBUG ((EFI_D_ERROR, "Setup Option ISPEn: 0x%x\n", SystemConfiguration->ISPEn));\r
263 mVlvPolicyPpi->ISPEn = SystemConfiguration->ISPEn;\r
264 DEBUG ((EFI_D_ERROR, "Setup Option ISPDevSel: 0x%x\n", SystemConfiguration->ISPDevSel));\r
265 mVlvPolicyPpi->ISPPciDevConfig = SystemConfiguration->ISPDevSel;\r
266 if (SystemConfiguration->ISPEn == 0) {\r
267 mVlvPolicyPpi->ISPPciDevConfig = 0;\r
268 DEBUG ((EFI_D_ERROR, "Update Setup Option ISPDevSel: 0x%x\n", mVlvPolicyPpi->ISPPciDevConfig));\r
269 }\r
270 Status = (*PeiServices)->InstallPpi(\r
271 PeiServices,\r
272 mVlvPolicyPpiDesc\r
273 );\r
274 ASSERT_EFI_ERROR (Status);\r
275\r
276 return EFI_SUCCESS;\r
277}\r
278\r
279\r
280EFI_STATUS\r
281ConfigureSoCGpio (\r
282 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
283 )\r
284{\r
285\r
286 DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------start\n"));\r
287 if (SystemConfiguration->eMMCBootMode== 1) {// Auto detection mode\r
288 DEBUG ((EFI_D_ERROR, "Auto detection mode------------start\n"));\r
289\r
290 //\r
291 //Silicon Steppings\r
292 //\r
293 switch (PchStepping()) {\r
294 case PchA0: // SOC A0 and A1\r
295 case PchA1:\r
296 DEBUG ((EFI_D_ERROR, "SOC A0/A1: eMMC 4.41 GPIO Configuration\n"));\r
297 SystemConfiguration->LpsseMMCEnabled = 1;\r
298 SystemConfiguration->LpsseMMC45Enabled = 0;\r
299 break;\r
300 case PchB0: // SOC B0 and later\r
301 default:\r
302 DEBUG ((EFI_D_ERROR, "SOC B0 and later: eMMC 4.5 GPIO Configuration\n"));\r
303 SystemConfiguration->LpsseMMCEnabled = 0;\r
304 SystemConfiguration->LpsseMMC45Enabled = 1;\r
305 break;\r
306 }\r
307 } else if (SystemConfiguration->eMMCBootMode == 2) { // eMMC 4.41\r
308 DEBUG ((EFI_D_ERROR, "Force to eMMC 4.41 GPIO Configuration\n"));\r
309 SystemConfiguration->LpsseMMCEnabled = 1;\r
310 SystemConfiguration->LpsseMMC45Enabled = 0;\r
311 } else if (SystemConfiguration->eMMCBootMode == 3) { // eMMC 4.5\r
312 DEBUG ((EFI_D_ERROR, "Force to eMMC 4.5 GPIO Configuration\n"));\r
313 SystemConfiguration->LpsseMMCEnabled = 0;\r
314 SystemConfiguration->LpsseMMC45Enabled = 1;\r
315\r
316 } else { // Disable eMMC controllers\r
317 DEBUG ((EFI_D_ERROR, "Disable eMMC GPIO controllers\n"));\r
318 SystemConfiguration->LpsseMMCEnabled = 0;\r
319 SystemConfiguration->LpsseMMC45Enabled = 0;\r
320 }\r
321\r
322 /*\r
323 20.1.1 EMMC\r
324 SDMMC1_CLK - write 0x2003ED01 to IOBASE + 0x03E0\r
325 SDMMC1_CMD - write 0x2003EC81 to IOBASE + 0x0390\r
326 SDMMC1_D0 - write 0x2003EC81 to IOBASE + 0x03D0\r
327 SDMMC1_D1 - write 0x2003EC81 to IOBASE + 0x0400\r
328 SDMMC1_D2 - write 0x2003EC81 to IOBASE + 0x03B0\r
329 SDMMC1_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0360\r
330 MMC1_D4_SD_WE - write 0x2003EC81 to IOBASE + 0x0380\r
331 MMC1_D5 - write 0x2003EC81 to IOBASE + 0x03C0\r
332 MMC1_D6 - write 0x2003EC81 to IOBASE + 0x0370\r
333 MMC1_D7 - write 0x2003EC81 to IOBASE + 0x03F0\r
334 MMC1_RESET_B - write 0x2003ED01 to IOBASE + 0x0330\r
335 */\r
336 if (SystemConfiguration->LpsseMMCEnabled== 1) {\r
337 MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED01); //EMMC 4.41\r
338 MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC81);\r
339 MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC81);\r
340 MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC81);\r
341 MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC81);\r
342 MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC81);\r
343 MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC81);\r
344 MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC81);\r
345 MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC81);\r
346 MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC81);\r
347 MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED01);\r
348 }\r
349\r
350 /*\r
351 eMMC 4.5 controller\r
352 SDMMC1_CLK - write 0x2003ED03 to IOBASE + 0x03E0\r
353 SDMMC1_CMD - write 0x2003EC83 to IOBASE + 0x0390\r
354 SDMMC1_D0 - write 0x2003EC83 to IOBASE + 0x03D0\r
355 SDMMC1_D1 - write 0x2003EC83 to IOBASE + 0x0400\r
356 SDMMC1_D2 - write 0x2003EC83 to IOBASE + 0x03B0\r
357 SDMMC1_D3_CD_B - write 0x2003EC83 to IOBASE + 0x0360\r
358 MMC1_D4_SD_WE - write 0x2003EC83 to IOBASE + 0x0380\r
359 MMC1_D5 - write 0x2003EC83 to IOBASE + 0x03C0\r
360 MMC1_D6 - write 0x2003EC83 to IOBASE + 0x0370\r
361 MMC1_D7 - write 0x2003EC83 to IOBASE + 0x03F0\r
362 MMC1_RESET_B - write 0x2003ED03 to IOBASE + 0x0330\r
363 */\r
364 if (SystemConfiguration->LpsseMMC45Enabled== 1) {\r
365 MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED03); // EMMC 4.5\r
366 MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC83);\r
367 MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC83);\r
368 MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC83);\r
369 MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC83);\r
370 MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC83);\r
371 MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC83);\r
372 MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC83);\r
373 MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC83);\r
374 MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC83);\r
375 MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED03);\r
376\r
377 }\r
378\r
379//\r
380// Change GPIOC_0 setting to allow MMIO access under Android.\r
381//\r
382 IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL,\r
383 (IoRead32(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL) & (UINT32)~BIT0));\r
384 DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------end\n"));\r
385 return EFI_SUCCESS;\r
386}\r
387\r
388EFI_STATUS\r
389MeasuredBootInit (\r
390 IN CONST EFI_PEI_SERVICES **PeiServices,\r
391 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
392 )\r
393{\r
394 if (SystemConfiguration->MeasuredBootEnable) {\r
395 PcdSetBool (PcdMeasuredBootEnable, TRUE);\r
396 } else {\r
397 PcdSetBool (PcdMeasuredBootEnable, FALSE);\r
398 }\r
399\r
400 return EFI_SUCCESS;\r
401}\r
402\r
403\r
404EFI_STATUS\r
405ConfigureLpssAndSccGpio (\r
406 IN SYSTEM_CONFIGURATION *SystemConfiguration,\r
407 IN EFI_PLATFORM_INFO_HOB *PlatformInfo\r
408 )\r
409{\r
410 /*One time configuration to each GPIO controller PSB_CONF register should be done before starting pad configuration:\r
411 GPIO SCORE - write 0x01001002 to IOBASE + 0x0700\r
412 GPIO NCORE - write 0x01001002 to IOBASE + 0x0F00\r
413 GPIO SSUS - write 0x01001002 to IOBASE + 0x1700\r
414 */\r
415 DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------start\n"));\r
416\r
417 /*\r
418 19.1.1 PWM0\r
419 PWM0 - write 0x2003CD01 to IOBASE + 0x00A0\r
420 19.1.2 PWM1\r
421 PWM0 - write 0x2003CD01 to IOBASE + 0x00B0\r
422 */\r
423 if (SystemConfiguration->LpssPwm0Enabled== 1) {\r
424 MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD01);\r
425 } else if (SystemConfiguration->LpssPwm0Enabled== 0) {\r
426 MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD00);\r
427 }\r
428\r
429 if (SystemConfiguration->LpssPwm1Enabled== 1) {\r
430 MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CC01);\r
431 } else if (SystemConfiguration->LpssPwm1Enabled== 0) {\r
432 MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CD00);\r
433 }\r
434\r
435 /*\r
436 19.1.3 UART1\r
437 UART1_RXD-L - write 0x2003CC81 to IOBASE + 0x0020\r
438 UART1_TXD-0 - write 0x2003CC81 to IOBASE + 0x0010\r
439 UART1_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0000\r
440 UART1_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0040\r
441 */\r
442 if (SystemConfiguration->LpssHsuart0Enabled== 1) {\r
443 MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC81); // uart1\r
444 MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC81);\r
445 if (SystemConfiguration->LpssHsuart0FlowControlEnabled== 0) {\r
446 DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[0]\n"));\r
447 MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC80);\r
448 MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC80);\r
449 } else {\r
450 DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[1]\n"));\r
451 MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC81);\r
452 MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC01);//W/A HSD 4752617 0x2003CC81\r
453 }\r
454 } else if (SystemConfiguration->LpssHsuart0Enabled== 0) {\r
455 MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC80); // uart1\r
456 MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC80);\r
457 }\r
458\r
459\r
460 /*\r
461 19.1.4 UART2\r
462 UART2_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0090\r
463 UART2_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0080\r
464 UART2_RXD-H - write 0x2003CC81 to IOBASE + 0x0060\r
465 UART2_TXD-0 - write 0x2003CC81 to IOBASE + 0x0070\r
466 */\r
467 if (SystemConfiguration->LpssHsuart1Enabled== 1) {\r
468 MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC81);\r
469 MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC81);\r
470\r
471 if (SystemConfiguration->LpssHsuart1FlowControlEnabled== 0) {\r
472 DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[0]\n"));\r
473 MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC80); // UART2_RTS_B\r
474 MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC80); // UART2_CTS_B\r
475 } else {\r
476 DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[1]\n"));\r
477 MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC81); // uart2\r
478 MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC01); //W/A HSD 4752617 0x2003CC81\r
479 }\r
480 } else if (SystemConfiguration->LpssHsuart1Enabled== 0) {\r
481 MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC80);\r
482 MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC80);\r
483 }\r
484\r
485 /*\r
486 19.1.5 SPI\r
487 SPI1_CS0_B - write 0x2003CC81 to IOBASE + 0x0110\r
488 SPI1_CLK - write 0x2003CD01 to IOBASE + 0x0100\r
489 SPI1_MOSI - write 0x2003CC81 to IOBASE + 0x0130\r
490 SPI1_MISO - write 0x2003CC81 to IOBASE + 0x0120\r
491 */\r
492 if (SystemConfiguration->LpssSpiEnabled== 1) {\r
493 MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003CC81); // SPI\r
494 MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003CD01);\r
495 MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003CC81);\r
496 MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003CC81);\r
497 } else if (SystemConfiguration->LpssSpiEnabled== 0) {\r
498 MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003cc80);\r
499 MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003cc80);\r
500 MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003cc80);\r
501 MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003cc80);\r
502 }\r
503\r
504 /*\r
505 19.1.6 I2C0\r
506 I2C0_SDA-OD-O - write 0x2003CC81 to IOBASE + 0x0210\r
507 I2C0_SCL-OD-O - write 0x2003CC81 to IOBASE + 0x0200\r
508 */\r
509 if (SystemConfiguration->LpssI2C0Enabled== 1) {\r
510 MmioWrite32 (IO_BASE_ADDRESS + 0x0210, 0x2003C881);\r
511 MmioWrite32 (IO_BASE_ADDRESS + 0x0200, 0x2003C881);\r
512 }\r
513 /*\r
514 19.1.7 I2C1\r
515 I2C1_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01F0\r
516 I2C1_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01E0\r
517 */\r
518\r
519 if (SystemConfiguration->LpssI2C1Enabled== 1) {\r
520 MmioWrite32 (IO_BASE_ADDRESS + 0x01F0, 0x2003C881);\r
521 MmioWrite32 (IO_BASE_ADDRESS + 0x01E0, 0x2003C881);\r
522 }\r
523 /*\r
524 19.1.8 I2C2\r
525 I2C2_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01D0\r
526 I2C2_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01B0\r
527 */\r
528 if (SystemConfiguration->LpssI2C2Enabled== 1) {\r
529 MmioWrite32 (IO_BASE_ADDRESS + 0x01D0, 0x2003C881);\r
530 MmioWrite32 (IO_BASE_ADDRESS + 0x01B0, 0x2003C881);\r
531 }\r
532 /*\r
533 19.1.9 I2C3\r
534 I2C3_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0190\r
535 I2C3_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01C0\r
536 */\r
537 if (SystemConfiguration->LpssI2C3Enabled== 1) {\r
538 MmioWrite32 (IO_BASE_ADDRESS + 0x0190, 0x2003C881);\r
539 MmioWrite32 (IO_BASE_ADDRESS + 0x01C0, 0x2003C881);\r
540 }\r
541 /*\r
542 19.1.10 I2C4\r
543 I2C4_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01A0\r
544 I2C4_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0170\r
545 */\r
546 if (SystemConfiguration->LpssI2C4Enabled== 1) {\r
547 MmioWrite32 (IO_BASE_ADDRESS + 0x01A0, 0x2003C881);\r
548 MmioWrite32 (IO_BASE_ADDRESS + 0x0170, 0x2003C881);\r
549 }\r
550 /*\r
551 19.1.11 I2C5\r
552 I2C5_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0150\r
553 I2C5_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0140\r
554 */\r
555 //touch 1.7M support on i2c5(from 0) need 2k PULL-UP.\r
556 if (SystemConfiguration->LpssI2C5Enabled== 1) {\r
557 MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C881);\r
558 MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C881);\r
559 } else if(SystemConfiguration->LpssI2C5Enabled== 0) {\r
560 MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C880);\r
561 MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C880);\r
562 }\r
563 /*\r
564 19.1.12 I2C6\r
565 I2C6_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0180\r
566 I2C6_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0160\r
567 */\r
568 if (SystemConfiguration->LpssI2C6Enabled== 1) {\r
569 MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C881);\r
570 MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C881);\r
571 } else if (SystemConfiguration->LpssI2C6Enabled== 0) {\r
572 MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C880);\r
573 MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C880);\r
574 }\r
575\r
576\r
577 /*\r
578 20.1.2 SDIO\r
579 SDMMC2_CLK - write 0x2003ED01 to IOBASE + 0x0320\r
580 SDMMC2_CMD - write 0x2003EC81 to IOBASE + 0x0300\r
581 SDMMC2_D0 - write 0x2003EC81 to IOBASE + 0x0350\r
582 SDMMC2_D1 - write 0x2003EC81 to IOBASE + 0x02F0\r
583 SDMMC2_D2 - write 0x2003EC81 to IOBASE + 0x0340\r
584 SDMMC2_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0310\r
585 */\r
586 if (SystemConfiguration->LpssSdioEnabled== 1) {\r
587 MmioWrite32 (IO_BASE_ADDRESS + 0x0320, 0x2003ED01);//SDIO\r
588 MmioWrite32 (IO_BASE_ADDRESS + 0x0300, 0x2003EC81);\r
589 MmioWrite32 (IO_BASE_ADDRESS + 0x0350, 0x2003EC81);\r
590 MmioWrite32 (IO_BASE_ADDRESS + 0x02F0, 0x2003EC81);\r
591 MmioWrite32 (IO_BASE_ADDRESS + 0x0340, 0x2003EC81);\r
592 MmioWrite32 (IO_BASE_ADDRESS + 0x0310, 0x2003EC81);\r
593 }\r
594\r
595 /*\r
596 20.1.3 SD Card\r
597 SDMMC3_1P8_EN - write 0x2003CD01 to IOBASE + 0x03F0\r
598 SDMMC3_CD_B - write 0x2003CC81 to IOBASE + 0x03A0\r
599 SDMMC3_CLK - write 0x2003CD01 to IOBASE + 0x02B0\r
600 SDMMC3_CMD - write 0x2003CC81 to IOBASE + 0x02C0\r
601 SDMMC3_D0 - write 0x2003CC81 to IOBASE + 0x02E0\r
602 SDMMC3_D1 - write 0x2003CC81 to IOBASE + 0x0290\r
603 SDMMC3_D2 - write 0x2003CC81 to IOBASE + 0x02D0\r
604 SDMMC3_D3 - write 0x2003CC81 to IOBASE + 0x02A0\r
605 SDMMC3_PWR_EN_B - write 0x2003CC81 to IOBASE + 0x0690\r
606 SDMMC3_WP - write 0x2003CC82 to IOBASE + 0x0160\r
607 */\r
608 if (SystemConfiguration->LpssSdcardEnabled == 1) {\r
609 if (!((PlatformInfo->BoardId == BOARD_ID_BL_FFRD && PlatformInfo->BoardRev== PR11) && (SystemConfiguration->CfioPnpSettings == 1))) {\r
610 MmioWrite32 (IO_BASE_ADDRESS + 0x05F0, 0x2003CD01);//SDCARD\r
611 MmioWrite32 (IO_BASE_ADDRESS + 0x02B0, 0x2003CD01);\r
612 MmioWrite32 (IO_BASE_ADDRESS + 0x02C0, 0x2003CC81);\r
613 MmioWrite32 (IO_BASE_ADDRESS + 0x02E0, 0x2003CC81);\r
614 MmioWrite32 (IO_BASE_ADDRESS + 0x0290, 0x2003CC81);\r
615 MmioWrite32 (IO_BASE_ADDRESS + 0x02D0, 0x2003CC81);\r
616 MmioWrite32 (IO_BASE_ADDRESS + 0x02A0, 0x2003CC81);\r
617 MmioWrite32 (IO_BASE_ADDRESS + 0x0690, 0x2003CC81);\r
618 MmioWrite32 (IO_BASE_ADDRESS + 0x0650, 0x2003CC82); //GPIOC_7 set to WP Pin\r
619 }\r
620 }\r
621\r
622\r
623 DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------end\n"));\r
624 return EFI_SUCCESS;\r
625}\r
626\r
627EFI_STATUS\r
628ConfigureLpeGpio (\r
629 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
630 )\r
631{\r
632 DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------start\n"));\r
633\r
634 if (SystemConfiguration->PchAzalia == 0) {\r
635 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x220, (UINT32)~(0x7), (UINT32) (0x01));\r
636 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x250, (UINT32)~(0x7), (UINT32) (0x01));\r
637 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x240, (UINT32)~(0x7), (UINT32) (0x01));\r
638 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x260, (UINT32)~(0x7), (UINT32) (0x01));\r
639 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x270, (UINT32)~(0x7), (UINT32) (0x01));\r
640 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x230, (UINT32)~(0x7), (UINT32) (0x01));\r
641 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x280, (UINT32)~(0x7), (UINT32) (0x01));\r
642 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x540, (UINT32)~(0x7), (UINT32) (0x01));\r
643 }\r
644\r
645 DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------end\n"));\r
646\r
647 return EFI_SUCCESS;\r
648}\r
649\r
650EFI_STATUS\r
651ConfigureSciSmiGpioRout (\r
652 IN EFI_PLATFORM_INFO_HOB *PlatformInfo)\r
653{\r
654 UINT32 GPI_Routing;\r
655\r
656 GPI_Routing = MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT);\r
657\r
658 //\r
659 // For FAB3, Route GPIO_CORE 0 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI\r
660 //\r
661 if(PlatformInfo->BoardRev == 3) {\r
662 GPI_Routing = GPI_Routing & 0xfffc3ffc;\r
663 GPI_Routing = GPI_Routing | 0x00024002;\r
664 }\r
665\r
666 //\r
667 // For FAB2/1, Route GPIO_CORE 7 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI\r
668 //\r
669 else {\r
670 GPI_Routing = GPI_Routing & 0x3fff3ffc;\r
671 GPI_Routing = GPI_Routing | 0x80004002;\r
672 }\r
673 MmioWrite32((PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT), GPI_Routing);\r
674\r
675 return EFI_SUCCESS;\r
676}\r
677\r
678EFI_STATUS\r
679ConfigureMipiCsi (\r
680 VOID)\r
681{\r
682 //\r
683 //Configure the platform clock for MIPI-CSI usage\r
684 //PLT_CLK0\r
685 //\r
686 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x6a0, (UINT32)~(0x7), (UINT32) (0x01));\r
687\r
688 //\r
689 //PLT_CLK1\r
690 //\r
691 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x570, (UINT32)~(0x7), (UINT32) (0x01));\r
692\r
693 //\r
694 //PLT_CLK2\r
695 //\r
696 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x5B0, (UINT32)~(0x7), (UINT32) (0x01));\r
697\r
698 return EFI_SUCCESS;\r
699}\r
700\r
701EFI_STATUS\r
702ConfigureUSBULPI (\r
703 VOID)\r
704{\r
705 //\r
706 //Configure USB ULPI\r
707 //USB_ULPI_0_CLK\r
708 //\r
709 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x338, (UINT32)~(0x7), (UINT32) (GPI));\r
710 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x330, (UINT32)~(0x187), (UINT32) (0x101));\r
711\r
712 //\r
713 //USB_ULPI_0_DATA0\r
714 //\r
715 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x388, (UINT32)~(0x7), (UINT32) (GPI));\r
716 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x380, (UINT32)~(0x187), (UINT32) (0x101));\r
717\r
718 //\r
719 //USB_ULPI_0_DATA1\r
720 //\r
721 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x368, (UINT32)~(0x7), (UINT32) (GPI));\r
722 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x360, (UINT32)~(0x187), (UINT32) (0x101));\r
723\r
724 //\r
725 //USB_ULPI_0_DATA2\r
726 //\r
727 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x318, (UINT32)~(0x7), (UINT32) (GPI));\r
728 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x310, (UINT32)~(0x187), (UINT32) (0x101));\r
729\r
730 //\r
731 //USB_ULPI_0_DATA3\r
732 //\r
733 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x378, (UINT32)~(0x7), (UINT32) (GPI));\r
734 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x370, (UINT32)~(0x187), (UINT32) (0x101));\r
735\r
736 //\r
737 //USB_ULPI_0_DATA4\r
738 //\r
739 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x308, (UINT32)~(0x7), (UINT32) (GPI));\r
740 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x300, (UINT32)~(0x187), (UINT32) (0x101));\r
741\r
742 //\r
743 //USB_ULPI_0_DATA5\r
744 //\r
745 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x398, (UINT32)~(0x7), (UINT32) (GPI));\r
746 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x390, (UINT32)~(0x187), (UINT32) (0x101));\r
747\r
748 //\r
749 //USB_ULPI_0_DATA6\r
750 //\r
751 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x328, (UINT32)~(0x7), (UINT32) (GPI));\r
752 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x320, (UINT32)~(0x187), (UINT32) (0x101));\r
753\r
754 //\r
755 //USB_ULPI_0_DATA7\r
756 //\r
757 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a8, (UINT32)~(0x7), (UINT32) (GPI));\r
758 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a0, (UINT32)~(0x187), (UINT32) (0x101));\r
759\r
760 //\r
761 //USB_ULPI_0_DIR\r
762 //\r
763 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x348, (UINT32)~(0x7), (UINT32) (GPI));\r
764 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x340, (UINT32)~(0x187), (UINT32) (0x81));\r
765\r
766 //\r
767 //USB_ULPI_0_NXT\r
768 //\r
769 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x358, (UINT32)~(0x7), (UINT32) (GPI));\r
770 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x350, (UINT32)~(0x187), (UINT32) (0x101));\r
771\r
772 //\r
773 //USB_ULPI_0_STP\r
774 //\r
775 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b8, (UINT32)~(0x7), (UINT32) (GPI));\r
776 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b0, (UINT32)~(0x187), (UINT32) (0x81));\r
777\r
778 //\r
779 //USB_ULPI_0_REFCLK\r
780 //\r
781 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x288, (UINT32)~(0x7), (UINT32) (GPI));\r
782 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x280, (UINT32)~(0x187), (UINT32) (0x101));\r
783\r
784 return EFI_SUCCESS;\r
785}\r
786\r
787EFI_STATUS\r
788DisableRTD3 (\r
789 VOID)\r
790{\r
791 //\r
792 //Disable RTD3\r
793 //\r
794 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x210, (UINT32)~(0x0f000007), (UINT32) (0x00));\r
795 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x1e0, (UINT32)~(0x0f000007), (UINT32) (0x00));\r
796\r
797 return EFI_SUCCESS;\r
798}\r
799\r
800/**\r
801 Platform specific initializations in stage1.\r
802\r
803 @param FfsHeader Pointer to the PEIM FFS file header.\r
804 @param PeiServices General purpose services available to every PEIM.\r
805\r
806 @retval EFI_SUCCESS Operation completed successfully.\r
807 @retval Otherwise Platform initialization failed.\r
808**/\r
809EFI_STATUS\r
810EFIAPI\r
811PlatformEarlyInitEntry (\r
812\r
813 IN EFI_PEI_FILE_HANDLE FileHandle,\r
814 IN CONST EFI_PEI_SERVICES **PeiServices\r
815 )\r
816{\r
817 EFI_STATUS Status;\r
818 SYSTEM_CONFIGURATION SystemConfiguration;\r
819 EFI_PLATFORM_INFO_HOB *PlatformInfo;\r
820 EFI_PEI_HOB_POINTERS Hob;\r
821 EFI_PLATFORM_CPU_INFO PlatformCpuInfo;\r
822\r
823 //\r
824 // Initialize SmbusPolicy PPI\r
825 //\r
826 Status = (*PeiServices)->InstallPpi(PeiServices, &mInstallSmbusPolicyPpi);\r
827 ASSERT_EFI_ERROR (Status);\r
828\r
829 //\r
830 // Initialize Stall PPIs\r
831 //\r
832 Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi);\r
833 ASSERT_EFI_ERROR (Status);\r
834\r
835 //\r
836 // Initialize platform PPIs\r
837 //\r
838 Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallSpeakerInterfacePpi);\r
839 ASSERT_EFI_ERROR (Status);\r
840\r
841 //\r
842 // Variable initialization\r
843 //\r
844 ZeroMem(&PlatformCpuInfo, sizeof(EFI_PLATFORM_CPU_INFO));\r
845\r
846 //\r
847 // Set the some PCI and chipset range as UC\r
848 // And align to 1M at leaset\r
849 //\r
850 Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r
851 ASSERT (Hob.Raw != NULL);\r
852 PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);\r
853\r
854 //\r
855 // Initialize PlatformInfo HOB\r
856 //\r
857 MultiPlatformInfoInit(PeiServices, PlatformInfo);\r
858\r
859 //\r
860 // Do basic MCH init\r
861 //\r
862 MchInit (PeiServices);\r
863\r
864 //\r
865 // Set the new boot mode\r
866 //\r
867 Status = UpdateBootMode (PeiServices, PlatformInfo);\r
868 ASSERT_EFI_ERROR (Status);\r
869\r
870 SetPlatformBootMode (PeiServices, PlatformInfo);\r
871\r
872 //\r
873 // Get setup variable. This can only be done after BootMode is updated\r
874 //\r
875 GetSetupVariable (PeiServices, &SystemConfiguration);\r
876\r
877 CheckOsSelection(PeiServices, &SystemConfiguration);\r
878\r
879 //\r
880 // Update PlatformInfo HOB according to setup variable\r
881 //\r
882 PlatformInfoUpdate(PeiServices, PlatformInfo, &SystemConfiguration);\r
883\r
884 InitializePlatform (PeiServices, PlatformInfo, &SystemConfiguration);\r
885\r
886 //\r
887 // Initialize VlvPolicy PPI\r
888 //\r
889 Status = VlvPolicyInit (PeiServices, &SystemConfiguration);\r
890 ASSERT_EFI_ERROR (Status);\r
891\r
892 //\r
893 // Soc specific GPIO setting\r
894 //\r
895 ConfigureSoCGpio(&SystemConfiguration);\r
896\r
897 //\r
898 // Baylake Board specific.\r
899 //\r
900 if (PlatformInfo->BoardId == BOARD_ID_BL_RVP ||\r
901 PlatformInfo->BoardId == BOARD_ID_BL_FFRD ||\r
902 PlatformInfo->BoardId == BOARD_ID_BL_FFRD8 ||\r
903 PlatformInfo->BoardId == BOARD_ID_BL_RVP_DDR3L ||\r
904 PlatformInfo->BoardId == BOARD_ID_BL_STHI ||\r
905 PlatformInfo->BoardId == BOARD_ID_BB_RVP ||\r
906 PlatformInfo->BoardId == BOARD_ID_BS_RVP ||\r
907 PlatformInfo->BoardId == BOARD_ID_MINNOW2 ||\r
8b7a63e7 908 PlatformInfo->BoardId == BOARD_ID_MINNOW2_TURBOT||\r
3cbfba02
DW		 909 PlatformInfo->BoardId == BOARD_ID_CVH) {\r
910 ConfigureLpssAndSccGpio(&SystemConfiguration, PlatformInfo);\r
911\r
912 }\r
913\r
914\r
915 //\r
916 // Configure LPE\r
917 // Alpine Valley and Bayley Bay board specific\r
918 //\r
919 ConfigureLpeGpio(&SystemConfiguration);\r
920\r
921 //\r
922 // Bayley Bay Board specific.\r
923 //\r
924 ConfigureSciSmiGpioRout(PlatformInfo);\r
925 if (SystemConfiguration.LpssI2C3Enabled == 1) {\r
926 ConfigureMipiCsi();\r
927 }\r
928\r
929\r
930 //\r
931 // Do basic CPU init\r
932 //\r
933 Status = PlatformCpuInit (PeiServices, &SystemConfiguration, &PlatformCpuInfo);\r
934\r
935 //\r
936 // Perform basic SSA related platform initialization\r
937 //\r
938 PlatformSsaInit (&SystemConfiguration,PeiServices);\r
939\r
940\r
941 //\r
942 // Do basic PCH init\r
943 //\r
944 Status = PlatformPchInit (&SystemConfiguration, PeiServices, PlatformInfo->PlatformType);\r
945 ASSERT_EFI_ERROR (Status);\r
946\r
947 //\r
948 // Initialize platform PPIs\r
949 //\r
950 Status = (*PeiServices)->InstallPpi (PeiServices, &mPpiList[0]);\r
951 ASSERT_EFI_ERROR (Status);\r
952\r
953 if (PlatformInfo->BoardId != BOARD_ID_CVH) {\r
954 InstallPlatformClocksNotify (PeiServices);\r
955 InstallPlatformSysCtrlGPIONotify(PeiServices);\r
956 }\r
957\r
958 //\r
959 // Initialize platform PPIs\r
960 //\r
961 Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);\r
962 ASSERT_EFI_ERROR (Status);\r
963\r
964 //\r
965 // Initialize Measured Boot\r
966 //\r
967 Status = MeasuredBootInit (PeiServices, &SystemConfiguration);\r
968 ASSERT_EFI_ERROR (Status);\r
969\r
970 return Status;\r
971}\r
972\r
973/**\r
974\r
975 Return the mainblockcompact Fv.\r
976\r
977 @param FvNumber Our enumeration of the firmware volumes we care about.\r
978\r
979 @param FvAddress Base Address of the memory containing the firmware volume\r
980\r
981 @retval EFI_SUCCESS\r
982 @retval EFI_NOT_FOUND\r
983\r
984**/\r
985EFI_STATUS\r
986EFIAPI\r
987FindFv (\r
988 IN EFI_PEI_FIND_FV_PPI *This,\r
989 IN CONST EFI_PEI_SERVICES **PeiServices,\r
990 IN OUT UINT8 *FvNumber,\r
991 OUT EFI_FIRMWARE_VOLUME_HEADER **FVAddress\r
992 )\r
993{\r
994 //\r
995 // At present, we only have one Fv to search\r
996 //\r
997 if (*FvNumber == 0) {\r
998 *FvNumber = 1;\r
999 *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FixedPcdGet32 (PcdFlashFvMainBase);\r
1000 return EFI_SUCCESS;\r
1001 }\r
1002 else if (*FvNumber == 1) {\r
1003 *FvNumber = 2;\r
1004 *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FixedPcdGet32 (PcdFlashFvRecovery2Base);\r
1005 return EFI_SUCCESS;\r
1006 }\r
1007 else { // Not the one Fv we care about\r
1008 return EFI_NOT_FOUND;\r
1009 }\r
1010}\r
1011\r
1012EFI_STATUS\r
1013EFIAPI\r
1014CpuOnlyReset (\r
1015 IN CONST EFI_PEI_SERVICES **PeiServices\r
1016 )\r
1017{\r
1018// MsgBus32Write(CDV_UNIT_PUNIT, PUNIT_CPU_RST, 0x01)\r
1019#ifdef __GNUC__\r
1020 __asm__\r
1021 (\r
1022 "xorl %ecx, %ecx\n"\r
1023 "1:hlt; hlt; hlt\n"\r
1024 "jmp 1b\n"\r
1025 );\r
1026#else\r
1027 _asm {\r
1028 xor ecx, ecx\r
1029 HltLoop:\r
1030 hlt\r
1031 hlt\r
1032 hlt\r
1033 loop HltLoop\r
1034 }\r
1035#endif\r
1036 //\r
1037 // If we get here we need to mark it as a failure.\r
1038 //\r
1039 return EFI_UNSUPPORTED;\r
1040}\r
1041\r
1042\r
1043#ifdef __GNUC__\r
1044#pragma GCC pop_options\r
1045#else\r
1046#pragma optimize ("", on)\r
1047#endif\r
EFI Development Kit II mirror for PVE