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3cbfba02
DW		 1/** @file\r
2\r
890f11d4 3 Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>\r
3cbfba02 4 \r\r
9dc8036d
MK		 5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
6\r
3cbfba02
DW		 7 \r\r
8\r
9\r
10Module Name:\r
11\r
12 PlatformEarlyInit.c\r
13\r
14Abstract:\r
15\r
16 Do platform specific PEI stage initializations.\r
17\r
18--*/\r
19\r
20\r
21#include "PlatformEarlyInit.h"\r
22\r
23#ifdef __GNUC__\r
24#pragma GCC push_options\r
25#pragma GCC optimize ("O0")\r
26#else\r
27#pragma optimize ("", off)\r
28#endif\r
29\r
30\r
31\r
32static EFI_PEI_STALL_PPI mStallPpi = {\r
33 PEI_STALL_RESOLUTION,\r
34 Stall\r
35};\r
36\r
37static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi = {\r
38 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
39 &gEfiPeiStallPpiGuid,\r
40 &mStallPpi\r
41};\r
42\r
43//\r
44// The reserved SMBus addresses are defined in PlatformDxe.h file.\r
45//\r
46static UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;\r
47static PEI_SMBUS_POLICY_PPI mSmbusPolicyPpi = {\r
48 SMBUS_BASE_ADDRESS,\r
49 SMBUS_BUS_DEV_FUNC,\r
50 PLATFORM_NUM_SMBUS_RSVD_ADDRESSES,\r
51 mSmbusRsvdAddresses\r
52};\r
53\r
54static EFI_PEI_PPI_DESCRIPTOR mInstallSmbusPolicyPpi = {\r
55 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
56 &gPeiSmbusPolicyPpiGuid,\r
57 &mSmbusPolicyPpi\r
58};\r
59static PEI_SPEAKER_IF_PPI mSpeakerInterfacePpi = {\r
60 ProgramToneFrequency,\r
61 GenerateBeepTone\r
62};\r
63\r
64static EFI_PEI_PPI_DESCRIPTOR mInstallSpeakerInterfacePpi = {\r
65 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
66 &gPeiSpeakerInterfacePpiGuid,\r
67 &mSpeakerInterfacePpi\r
68};\r
69\r
70static EFI_PEI_RESET_PPI mResetPpi = { IchReset };\r
71\r
72\r
73static EFI_PEI_FIND_FV_PPI mEfiFindFvPpi = {\r
74 (EFI_PEI_FIND_FV_FINDFV)FindFv\r
75};\r
76\r
77static EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {\r
78 {\r
79 EFI_PEI_PPI_DESCRIPTOR_PPI,\r
80 &gEfiPeiMasterBootModePpiGuid,\r
81 NULL\r
82 },\r
83 {\r
84 EFI_PEI_PPI_DESCRIPTOR_PPI,\r
85 &gEfiPeiResetPpiGuid,\r
86 &mResetPpi\r
87 },\r
88 {\r
89 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
90 &gEfiFindFvPpiGuid,\r
91 &mEfiFindFvPpi\r
92 }\r
93};\r
94\r
95static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {\r
96 {\r
97 EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,\r
98 &gEfiEndOfPeiSignalPpiGuid,\r
99 (EFI_PEIM_NOTIFY_ENTRY_POINT)EndOfPeiPpiNotifyCallback\r
100 },\r
101 {\r
102 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
103 &gEfiPeiMemoryDiscoveredPpiGuid,\r
104 (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotifyCallback\r
105 }\r
106\r
107};\r
108\r
109\r
110/**\r
111\r
112 Parse the status registers for figuring out the wake-up event and save it into\r
113 an GUID HOB which will be referenced later. However, modification is required\r
114 to meet the chipset register definition and the practical hardware design. Thus,\r
115 this is just an example.\r
116\r
117\r
118 @param PeiServices pointer to the PEI Service Table\r
119 @param EFI_SUCCESS Always return Success\r
120\r
121 @retval None\r
122\r
123\r
124**/\r
125EFI_STATUS\r
126EFIAPI\r
127GetWakeupEventAndSaveToHob (\r
128 IN CONST EFI_PEI_SERVICES **PeiServices\r
129 )\r
130{\r
131 UINT16 Pm1Sts;\r
132 UINTN Gpe0Sts;\r
133 UINTN WakeEventData;\r
134\r
135 //\r
136 // Read the ACPI registers\r
137 //\r
138 Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);\r
139 Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS);\r
140\r
141 //\r
142 // Figure out the wake-up event\r
143 //\r
144 if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) != 0) {\r
145 WakeEventData = SMBIOS_WAKEUP_TYPE_POWER_SWITCH;\r
146 } else if (((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) != 0)) {\r
147 WakeEventData = SMBIOS_WAKEUP_TYPE_PCI_PME;\r
148 } else if (Gpe0Sts != 0) {\r
149 WakeEventData = SMBIOS_WAKEUP_TYPE_OTHERS;\r
150 } else {\r
151 WakeEventData = SMBIOS_WAKEUP_TYPE_UNKNOWN;\r
152 }\r
153\r
154 DEBUG ((EFI_D_ERROR, "ACPI Wake Status Register: %04x\n", Pm1Sts));\r
c5136804 155 DEBUG ((EFI_D_ERROR, "ACPI Wake Event Data: %02x\n", WakeEventData));\r
3cbfba02
DW		 156\r
157 return EFI_SUCCESS;\r
158}\r
159\r
160EFI_STATUS\r
161GetSetupVariable (\r
162 IN CONST EFI_PEI_SERVICES **PeiServices,\r
163 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
164 )\r
165{\r
166 UINTN VariableSize;\r
167 EFI_STATUS Status;\r
168 EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;\r
169\r
170 VariableSize = sizeof (SYSTEM_CONFIGURATION);\r
171 ZeroMem (SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));\r
172\r
173 Status = (*PeiServices)->LocatePpi (\r
174 PeiServices,\r
175 &gEfiPeiReadOnlyVariable2PpiGuid,\r
176 0,\r
177 NULL,\r
178 (void **)&Variable\r
179 );\r
180 ASSERT_EFI_ERROR (Status);\r
181\r
182 //\r
183 // Use normal setup default from NVRAM variable,\r
184 // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.\r
185 //\r
186 VariableSize = sizeof(SYSTEM_CONFIGURATION);\r
187 Status = Variable->GetVariable (\r
188 Variable,\r
189 L"Setup",\r
190 &gEfiSetupVariableGuid,\r
191 NULL,\r
192 &VariableSize,\r
193 SystemConfiguration\r
194 );\r
620f2891
TH		 195 if (EFI_ERROR (Status) || VariableSize != sizeof(SYSTEM_CONFIGURATION)) {\r
196 //The setup variable is corrupted\r
197 VariableSize = sizeof(SYSTEM_CONFIGURATION);\r
198 Status = Variable->GetVariable(\r
199 Variable,\r
200 L"SetupRecovery",\r
201 &gEfiSetupVariableGuid,\r
202 NULL,\r
203 &VariableSize,\r
204 SystemConfiguration\r
205 );\r
206 ASSERT_EFI_ERROR (Status);\r
207 } \r
3cbfba02
DW		 208 return Status;\r
209}\r
210\r
211EFI_STATUS\r
212VlvPolicyInit (\r
213 IN CONST EFI_PEI_SERVICES **PeiServices,\r
214 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
215 )\r
216{\r
217 EFI_STATUS Status;\r
218 EFI_PEI_PPI_DESCRIPTOR *mVlvPolicyPpiDesc;\r
219 VLV_POLICY_PPI *mVlvPolicyPpi;\r
220\r
221 Status = (*PeiServices)->AllocatePool(\r
222 PeiServices,\r
223 sizeof (EFI_PEI_PPI_DESCRIPTOR),\r
224 (void **)&mVlvPolicyPpiDesc\r
225 );\r
226 ASSERT_EFI_ERROR (Status);\r
227\r
228 Status = (*PeiServices)->AllocatePool(\r
229 PeiServices,\r
230 sizeof (VLV_POLICY_PPI),\r
231 (void **)&mVlvPolicyPpi\r
232 );\r
233 ASSERT_EFI_ERROR (Status);\r
234\r
235 //\r
236 // Initialize PPI\r
237 //\r
238 (*PeiServices)->SetMem ((VOID *)mVlvPolicyPpi, sizeof (VLV_POLICY_PPI), 0);\r
239 mVlvPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r
240 mVlvPolicyPpiDesc->Guid = &gVlvPolicyPpiGuid;\r
241 mVlvPolicyPpiDesc->Ppi = mVlvPolicyPpi;\r
242 mVlvPolicyPpi->GtConfig.PrimaryDisplay = SystemConfiguration->PrimaryVideoAdaptor;\r
243 mVlvPolicyPpi->GtConfig.IgdDvmt50PreAlloc = SystemConfiguration->IgdDvmt50PreAlloc;\r
244 mVlvPolicyPpi->GtConfig.ApertureSize = SystemConfiguration->IgdApertureSize;\r
245 mVlvPolicyPpi->GtConfig.GttSize = SystemConfiguration->GTTSize;\r
246 if (SystemConfiguration->PrimaryVideoAdaptor != 2) {\r
247 mVlvPolicyPpi->GtConfig.InternalGraphics = SystemConfiguration->Igd;\r
248 } else {\r
249 mVlvPolicyPpi->GtConfig.InternalGraphics = 0;\r
250 }\r
251\r
252\r
253 mVlvPolicyPpi->GtConfig.IgdTurboEn = 1;\r
254\r
255\r
256 mVlvPolicyPpi->PlatformData.FastBoot = SystemConfiguration->FastBoot;\r
257 mVlvPolicyPpi->PlatformData.DynSR = 1;\r
258 DEBUG ((EFI_D_ERROR, "Setup Option ISPEn: 0x%x\n", SystemConfiguration->ISPEn));\r
259 mVlvPolicyPpi->ISPEn = SystemConfiguration->ISPEn;\r
260 DEBUG ((EFI_D_ERROR, "Setup Option ISPDevSel: 0x%x\n", SystemConfiguration->ISPDevSel));\r
261 mVlvPolicyPpi->ISPPciDevConfig = SystemConfiguration->ISPDevSel;\r
262 if (SystemConfiguration->ISPEn == 0) {\r
263 mVlvPolicyPpi->ISPPciDevConfig = 0;\r
264 DEBUG ((EFI_D_ERROR, "Update Setup Option ISPDevSel: 0x%x\n", mVlvPolicyPpi->ISPPciDevConfig));\r
265 }\r
266 Status = (*PeiServices)->InstallPpi(\r
267 PeiServices,\r
268 mVlvPolicyPpiDesc\r
269 );\r
270 ASSERT_EFI_ERROR (Status);\r
271\r
272 return EFI_SUCCESS;\r
273}\r
274\r
275\r
276EFI_STATUS\r
277ConfigureSoCGpio (\r
278 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
279 )\r
280{\r
281\r
282 DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------start\n"));\r
283 if (SystemConfiguration->eMMCBootMode== 1) {// Auto detection mode\r
284 DEBUG ((EFI_D_ERROR, "Auto detection mode------------start\n"));\r
285\r
286 //\r
287 //Silicon Steppings\r
288 //\r
289 switch (PchStepping()) {\r
290 case PchA0: // SOC A0 and A1\r
291 case PchA1:\r
292 DEBUG ((EFI_D_ERROR, "SOC A0/A1: eMMC 4.41 GPIO Configuration\n"));\r
293 SystemConfiguration->LpsseMMCEnabled = 1;\r
294 SystemConfiguration->LpsseMMC45Enabled = 0;\r
295 break;\r
296 case PchB0: // SOC B0 and later\r
297 default:\r
298 DEBUG ((EFI_D_ERROR, "SOC B0 and later: eMMC 4.5 GPIO Configuration\n"));\r
299 SystemConfiguration->LpsseMMCEnabled = 0;\r
300 SystemConfiguration->LpsseMMC45Enabled = 1;\r
301 break;\r
302 }\r
303 } else if (SystemConfiguration->eMMCBootMode == 2) { // eMMC 4.41\r
304 DEBUG ((EFI_D_ERROR, "Force to eMMC 4.41 GPIO Configuration\n"));\r
305 SystemConfiguration->LpsseMMCEnabled = 1;\r
306 SystemConfiguration->LpsseMMC45Enabled = 0;\r
307 } else if (SystemConfiguration->eMMCBootMode == 3) { // eMMC 4.5\r
308 DEBUG ((EFI_D_ERROR, "Force to eMMC 4.5 GPIO Configuration\n"));\r
309 SystemConfiguration->LpsseMMCEnabled = 0;\r
310 SystemConfiguration->LpsseMMC45Enabled = 1;\r
311\r
312 } else { // Disable eMMC controllers\r
313 DEBUG ((EFI_D_ERROR, "Disable eMMC GPIO controllers\n"));\r
314 SystemConfiguration->LpsseMMCEnabled = 0;\r
315 SystemConfiguration->LpsseMMC45Enabled = 0;\r
316 }\r
317\r
318 /*\r
319 20.1.1 EMMC\r
320 SDMMC1_CLK - write 0x2003ED01 to IOBASE + 0x03E0\r
321 SDMMC1_CMD - write 0x2003EC81 to IOBASE + 0x0390\r
322 SDMMC1_D0 - write 0x2003EC81 to IOBASE + 0x03D0\r
323 SDMMC1_D1 - write 0x2003EC81 to IOBASE + 0x0400\r
324 SDMMC1_D2 - write 0x2003EC81 to IOBASE + 0x03B0\r
325 SDMMC1_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0360\r
326 MMC1_D4_SD_WE - write 0x2003EC81 to IOBASE + 0x0380\r
327 MMC1_D5 - write 0x2003EC81 to IOBASE + 0x03C0\r
328 MMC1_D6 - write 0x2003EC81 to IOBASE + 0x0370\r
329 MMC1_D7 - write 0x2003EC81 to IOBASE + 0x03F0\r
330 MMC1_RESET_B - write 0x2003ED01 to IOBASE + 0x0330\r
331 */\r
332 if (SystemConfiguration->LpsseMMCEnabled== 1) {\r
333 MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED01); //EMMC 4.41\r
334 MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC81);\r
335 MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC81);\r
336 MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC81);\r
337 MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC81);\r
338 MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC81);\r
339 MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC81);\r
340 MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC81);\r
341 MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC81);\r
342 MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC81);\r
343 MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED01);\r
344 }\r
345\r
346 /*\r
347 eMMC 4.5 controller\r
348 SDMMC1_CLK - write 0x2003ED03 to IOBASE + 0x03E0\r
349 SDMMC1_CMD - write 0x2003EC83 to IOBASE + 0x0390\r
350 SDMMC1_D0 - write 0x2003EC83 to IOBASE + 0x03D0\r
351 SDMMC1_D1 - write 0x2003EC83 to IOBASE + 0x0400\r
352 SDMMC1_D2 - write 0x2003EC83 to IOBASE + 0x03B0\r
353 SDMMC1_D3_CD_B - write 0x2003EC83 to IOBASE + 0x0360\r
354 MMC1_D4_SD_WE - write 0x2003EC83 to IOBASE + 0x0380\r
355 MMC1_D5 - write 0x2003EC83 to IOBASE + 0x03C0\r
356 MMC1_D6 - write 0x2003EC83 to IOBASE + 0x0370\r
357 MMC1_D7 - write 0x2003EC83 to IOBASE + 0x03F0\r
358 MMC1_RESET_B - write 0x2003ED03 to IOBASE + 0x0330\r
359 */\r
360 if (SystemConfiguration->LpsseMMC45Enabled== 1) {\r
361 MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED03); // EMMC 4.5\r
362 MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC83);\r
363 MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC83);\r
364 MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC83);\r
365 MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC83);\r
366 MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC83);\r
367 MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC83);\r
368 MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC83);\r
369 MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC83);\r
370 MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC83);\r
371 MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED03);\r
372\r
373 }\r
374\r
375//\r
376// Change GPIOC_0 setting to allow MMIO access under Android.\r
377//\r
378 IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL,\r
379 (IoRead32(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL) & (UINT32)~BIT0));\r
380 DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------end\n"));\r
381 return EFI_SUCCESS;\r
382}\r
383\r
384EFI_STATUS\r
385MeasuredBootInit (\r
386 IN CONST EFI_PEI_SERVICES **PeiServices,\r
387 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
388 )\r
389{\r
390 if (SystemConfiguration->MeasuredBootEnable) {\r
391 PcdSetBool (PcdMeasuredBootEnable, TRUE);\r
392 } else {\r
393 PcdSetBool (PcdMeasuredBootEnable, FALSE);\r
394 }\r
395\r
396 return EFI_SUCCESS;\r
397}\r
398\r
399\r
400EFI_STATUS\r
401ConfigureLpssAndSccGpio (\r
402 IN SYSTEM_CONFIGURATION *SystemConfiguration,\r
403 IN EFI_PLATFORM_INFO_HOB *PlatformInfo\r
404 )\r
405{\r
406 /*One time configuration to each GPIO controller PSB_CONF register should be done before starting pad configuration:\r
407 GPIO SCORE - write 0x01001002 to IOBASE + 0x0700\r
408 GPIO NCORE - write 0x01001002 to IOBASE + 0x0F00\r
409 GPIO SSUS - write 0x01001002 to IOBASE + 0x1700\r
410 */\r
411 DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------start\n"));\r
412\r
413 /*\r
414 19.1.1 PWM0\r
415 PWM0 - write 0x2003CD01 to IOBASE + 0x00A0\r
416 19.1.2 PWM1\r
417 PWM0 - write 0x2003CD01 to IOBASE + 0x00B0\r
418 */\r
419 if (SystemConfiguration->LpssPwm0Enabled== 1) {\r
420 MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD01);\r
421 } else if (SystemConfiguration->LpssPwm0Enabled== 0) {\r
422 MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD00);\r
423 }\r
424\r
425 if (SystemConfiguration->LpssPwm1Enabled== 1) {\r
426 MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CC01);\r
427 } else if (SystemConfiguration->LpssPwm1Enabled== 0) {\r
428 MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CD00);\r
429 }\r
430\r
431 /*\r
432 19.1.3 UART1\r
433 UART1_RXD-L - write 0x2003CC81 to IOBASE + 0x0020\r
434 UART1_TXD-0 - write 0x2003CC81 to IOBASE + 0x0010\r
435 UART1_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0000\r
436 UART1_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0040\r
437 */\r
438 if (SystemConfiguration->LpssHsuart0Enabled== 1) {\r
439 MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC81); // uart1\r
440 MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC81);\r
441 if (SystemConfiguration->LpssHsuart0FlowControlEnabled== 0) {\r
442 DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[0]\n"));\r
443 MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC80);\r
444 MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC80);\r
445 } else {\r
446 DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[1]\n"));\r
447 MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC81);\r
448 MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC01);//W/A HSD 4752617 0x2003CC81\r
449 }\r
450 } else if (SystemConfiguration->LpssHsuart0Enabled== 0) {\r
451 MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC80); // uart1\r
452 MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC80);\r
453 }\r
454\r
455\r
456 /*\r
457 19.1.4 UART2\r
458 UART2_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0090\r
459 UART2_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0080\r
460 UART2_RXD-H - write 0x2003CC81 to IOBASE + 0x0060\r
461 UART2_TXD-0 - write 0x2003CC81 to IOBASE + 0x0070\r
462 */\r
463 if (SystemConfiguration->LpssHsuart1Enabled== 1) {\r
464 MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC81);\r
465 MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC81);\r
466\r
467 if (SystemConfiguration->LpssHsuart1FlowControlEnabled== 0) {\r
468 DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[0]\n"));\r
469 MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC80); // UART2_RTS_B\r
470 MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC80); // UART2_CTS_B\r
471 } else {\r
472 DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[1]\n"));\r
473 MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC81); // uart2\r
474 MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC01); //W/A HSD 4752617 0x2003CC81\r
475 }\r
476 } else if (SystemConfiguration->LpssHsuart1Enabled== 0) {\r
477 MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC80);\r
478 MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC80);\r
479 }\r
480\r
481 /*\r
482 19.1.5 SPI\r
483 SPI1_CS0_B - write 0x2003CC81 to IOBASE + 0x0110\r
484 SPI1_CLK - write 0x2003CD01 to IOBASE + 0x0100\r
485 SPI1_MOSI - write 0x2003CC81 to IOBASE + 0x0130\r
486 SPI1_MISO - write 0x2003CC81 to IOBASE + 0x0120\r
487 */\r
488 if (SystemConfiguration->LpssSpiEnabled== 1) {\r
489 MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003CC81); // SPI\r
490 MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003CD01);\r
491 MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003CC81);\r
492 MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003CC81);\r
493 } else if (SystemConfiguration->LpssSpiEnabled== 0) {\r
494 MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003cc80);\r
495 MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003cc80);\r
496 MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003cc80);\r
497 MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003cc80);\r
498 }\r
499\r
500 /*\r
501 19.1.6 I2C0\r
502 I2C0_SDA-OD-O - write 0x2003CC81 to IOBASE + 0x0210\r
503 I2C0_SCL-OD-O - write 0x2003CC81 to IOBASE + 0x0200\r
504 */\r
505 if (SystemConfiguration->LpssI2C0Enabled== 1) {\r
506 MmioWrite32 (IO_BASE_ADDRESS + 0x0210, 0x2003C881);\r
507 MmioWrite32 (IO_BASE_ADDRESS + 0x0200, 0x2003C881);\r
508 }\r
509 /*\r
510 19.1.7 I2C1\r
511 I2C1_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01F0\r
512 I2C1_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01E0\r
513 */\r
514\r
515 if (SystemConfiguration->LpssI2C1Enabled== 1) {\r
516 MmioWrite32 (IO_BASE_ADDRESS + 0x01F0, 0x2003C881);\r
517 MmioWrite32 (IO_BASE_ADDRESS + 0x01E0, 0x2003C881);\r
518 }\r
519 /*\r
520 19.1.8 I2C2\r
521 I2C2_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01D0\r
522 I2C2_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01B0\r
523 */\r
524 if (SystemConfiguration->LpssI2C2Enabled== 1) {\r
525 MmioWrite32 (IO_BASE_ADDRESS + 0x01D0, 0x2003C881);\r
526 MmioWrite32 (IO_BASE_ADDRESS + 0x01B0, 0x2003C881);\r
527 }\r
528 /*\r
529 19.1.9 I2C3\r
530 I2C3_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0190\r
531 I2C3_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01C0\r
532 */\r
533 if (SystemConfiguration->LpssI2C3Enabled== 1) {\r
534 MmioWrite32 (IO_BASE_ADDRESS + 0x0190, 0x2003C881);\r
535 MmioWrite32 (IO_BASE_ADDRESS + 0x01C0, 0x2003C881);\r
536 }\r
537 /*\r
538 19.1.10 I2C4\r
539 I2C4_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01A0\r
540 I2C4_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0170\r
541 */\r
542 if (SystemConfiguration->LpssI2C4Enabled== 1) {\r
543 MmioWrite32 (IO_BASE_ADDRESS + 0x01A0, 0x2003C881);\r
544 MmioWrite32 (IO_BASE_ADDRESS + 0x0170, 0x2003C881);\r
545 }\r
546 /*\r
547 19.1.11 I2C5\r
548 I2C5_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0150\r
549 I2C5_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0140\r
550 */\r
551 //touch 1.7M support on i2c5(from 0) need 2k PULL-UP.\r
552 if (SystemConfiguration->LpssI2C5Enabled== 1) {\r
553 MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C881);\r
554 MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C881);\r
555 } else if(SystemConfiguration->LpssI2C5Enabled== 0) {\r
556 MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C880);\r
557 MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C880);\r
558 }\r
559 /*\r
560 19.1.12 I2C6\r
561 I2C6_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0180\r
562 I2C6_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0160\r
563 */\r
564 if (SystemConfiguration->LpssI2C6Enabled== 1) {\r
565 MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C881);\r
566 MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C881);\r
567 } else if (SystemConfiguration->LpssI2C6Enabled== 0) {\r
568 MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C880);\r
569 MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C880);\r
570 }\r
571\r
572\r
573 /*\r
574 20.1.2 SDIO\r
575 SDMMC2_CLK - write 0x2003ED01 to IOBASE + 0x0320\r
576 SDMMC2_CMD - write 0x2003EC81 to IOBASE + 0x0300\r
577 SDMMC2_D0 - write 0x2003EC81 to IOBASE + 0x0350\r
578 SDMMC2_D1 - write 0x2003EC81 to IOBASE + 0x02F0\r
579 SDMMC2_D2 - write 0x2003EC81 to IOBASE + 0x0340\r
580 SDMMC2_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0310\r
581 */\r
582 if (SystemConfiguration->LpssSdioEnabled== 1) {\r
583 MmioWrite32 (IO_BASE_ADDRESS + 0x0320, 0x2003ED01);//SDIO\r
584 MmioWrite32 (IO_BASE_ADDRESS + 0x0300, 0x2003EC81);\r
585 MmioWrite32 (IO_BASE_ADDRESS + 0x0350, 0x2003EC81);\r
586 MmioWrite32 (IO_BASE_ADDRESS + 0x02F0, 0x2003EC81);\r
587 MmioWrite32 (IO_BASE_ADDRESS + 0x0340, 0x2003EC81);\r
588 MmioWrite32 (IO_BASE_ADDRESS + 0x0310, 0x2003EC81);\r
589 }\r
590\r
591 /*\r
592 20.1.3 SD Card\r
593 SDMMC3_1P8_EN - write 0x2003CD01 to IOBASE + 0x03F0\r
594 SDMMC3_CD_B - write 0x2003CC81 to IOBASE + 0x03A0\r
595 SDMMC3_CLK - write 0x2003CD01 to IOBASE + 0x02B0\r
596 SDMMC3_CMD - write 0x2003CC81 to IOBASE + 0x02C0\r
597 SDMMC3_D0 - write 0x2003CC81 to IOBASE + 0x02E0\r
598 SDMMC3_D1 - write 0x2003CC81 to IOBASE + 0x0290\r
599 SDMMC3_D2 - write 0x2003CC81 to IOBASE + 0x02D0\r
600 SDMMC3_D3 - write 0x2003CC81 to IOBASE + 0x02A0\r
601 SDMMC3_PWR_EN_B - write 0x2003CC81 to IOBASE + 0x0690\r
602 SDMMC3_WP - write 0x2003CC82 to IOBASE + 0x0160\r
603 */\r
604 if (SystemConfiguration->LpssSdcardEnabled == 1) {\r
605 if (!((PlatformInfo->BoardId == BOARD_ID_BL_FFRD && PlatformInfo->BoardRev== PR11) && (SystemConfiguration->CfioPnpSettings == 1))) {\r
606 MmioWrite32 (IO_BASE_ADDRESS + 0x05F0, 0x2003CD01);//SDCARD\r
607 MmioWrite32 (IO_BASE_ADDRESS + 0x02B0, 0x2003CD01);\r
608 MmioWrite32 (IO_BASE_ADDRESS + 0x02C0, 0x2003CC81);\r
609 MmioWrite32 (IO_BASE_ADDRESS + 0x02E0, 0x2003CC81);\r
610 MmioWrite32 (IO_BASE_ADDRESS + 0x0290, 0x2003CC81);\r
611 MmioWrite32 (IO_BASE_ADDRESS + 0x02D0, 0x2003CC81);\r
612 MmioWrite32 (IO_BASE_ADDRESS + 0x02A0, 0x2003CC81);\r
613 MmioWrite32 (IO_BASE_ADDRESS + 0x0690, 0x2003CC81);\r
614 MmioWrite32 (IO_BASE_ADDRESS + 0x0650, 0x2003CC82); //GPIOC_7 set to WP Pin\r
615 }\r
616 }\r
617\r
618\r
619 DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------end\n"));\r
620 return EFI_SUCCESS;\r
621}\r
622\r
623EFI_STATUS\r
624ConfigureLpeGpio (\r
625 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
626 )\r
627{\r
628 DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------start\n"));\r
629\r
630 if (SystemConfiguration->PchAzalia == 0) {\r
631 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x220, (UINT32)~(0x7), (UINT32) (0x01));\r
632 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x250, (UINT32)~(0x7), (UINT32) (0x01));\r
633 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x240, (UINT32)~(0x7), (UINT32) (0x01));\r
634 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x260, (UINT32)~(0x7), (UINT32) (0x01));\r
635 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x270, (UINT32)~(0x7), (UINT32) (0x01));\r
636 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x230, (UINT32)~(0x7), (UINT32) (0x01));\r
637 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x280, (UINT32)~(0x7), (UINT32) (0x01));\r
638 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x540, (UINT32)~(0x7), (UINT32) (0x01));\r
639 }\r
640\r
641 DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------end\n"));\r
642\r
643 return EFI_SUCCESS;\r
644}\r
645\r
646EFI_STATUS\r
647ConfigureSciSmiGpioRout (\r
648 IN EFI_PLATFORM_INFO_HOB *PlatformInfo)\r
649{\r
650 UINT32 GPI_Routing;\r
651\r
652 GPI_Routing = MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT);\r
653\r
654 //\r
655 // For FAB3, Route GPIO_CORE 0 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI\r
656 //\r
657 if(PlatformInfo->BoardRev == 3) {\r
658 GPI_Routing = GPI_Routing & 0xfffc3ffc;\r
659 GPI_Routing = GPI_Routing | 0x00024002;\r
660 }\r
661\r
662 //\r
663 // For FAB2/1, Route GPIO_CORE 7 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI\r
664 //\r
665 else {\r
666 GPI_Routing = GPI_Routing & 0x3fff3ffc;\r
667 GPI_Routing = GPI_Routing | 0x80004002;\r
668 }\r
669 MmioWrite32((PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT), GPI_Routing);\r
670\r
671 return EFI_SUCCESS;\r
672}\r
673\r
674EFI_STATUS\r
675ConfigureMipiCsi (\r
676 VOID)\r
677{\r
678 //\r
679 //Configure the platform clock for MIPI-CSI usage\r
680 //PLT_CLK0\r
681 //\r
682 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x6a0, (UINT32)~(0x7), (UINT32) (0x01));\r
683\r
684 //\r
685 //PLT_CLK1\r
686 //\r
687 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x570, (UINT32)~(0x7), (UINT32) (0x01));\r
688\r
689 //\r
690 //PLT_CLK2\r
691 //\r
692 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x5B0, (UINT32)~(0x7), (UINT32) (0x01));\r
693\r
694 return EFI_SUCCESS;\r
695}\r
696\r
697EFI_STATUS\r
698ConfigureUSBULPI (\r
699 VOID)\r
700{\r
701 //\r
702 //Configure USB ULPI\r
703 //USB_ULPI_0_CLK\r
704 //\r
705 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x338, (UINT32)~(0x7), (UINT32) (GPI));\r
706 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x330, (UINT32)~(0x187), (UINT32) (0x101));\r
707\r
708 //\r
709 //USB_ULPI_0_DATA0\r
710 //\r
711 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x388, (UINT32)~(0x7), (UINT32) (GPI));\r
712 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x380, (UINT32)~(0x187), (UINT32) (0x101));\r
713\r
714 //\r
715 //USB_ULPI_0_DATA1\r
716 //\r
717 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x368, (UINT32)~(0x7), (UINT32) (GPI));\r
718 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x360, (UINT32)~(0x187), (UINT32) (0x101));\r
719\r
720 //\r
721 //USB_ULPI_0_DATA2\r
722 //\r
723 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x318, (UINT32)~(0x7), (UINT32) (GPI));\r
724 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x310, (UINT32)~(0x187), (UINT32) (0x101));\r
725\r
726 //\r
727 //USB_ULPI_0_DATA3\r
728 //\r
729 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x378, (UINT32)~(0x7), (UINT32) (GPI));\r
730 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x370, (UINT32)~(0x187), (UINT32) (0x101));\r
731\r
732 //\r
733 //USB_ULPI_0_DATA4\r
734 //\r
735 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x308, (UINT32)~(0x7), (UINT32) (GPI));\r
736 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x300, (UINT32)~(0x187), (UINT32) (0x101));\r
737\r
738 //\r
739 //USB_ULPI_0_DATA5\r
740 //\r
741 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x398, (UINT32)~(0x7), (UINT32) (GPI));\r
742 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x390, (UINT32)~(0x187), (UINT32) (0x101));\r
743\r
744 //\r
745 //USB_ULPI_0_DATA6\r
746 //\r
747 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x328, (UINT32)~(0x7), (UINT32) (GPI));\r
748 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x320, (UINT32)~(0x187), (UINT32) (0x101));\r
749\r
750 //\r
751 //USB_ULPI_0_DATA7\r
752 //\r
753 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a8, (UINT32)~(0x7), (UINT32) (GPI));\r
754 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a0, (UINT32)~(0x187), (UINT32) (0x101));\r
755\r
756 //\r
757 //USB_ULPI_0_DIR\r
758 //\r
759 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x348, (UINT32)~(0x7), (UINT32) (GPI));\r
760 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x340, (UINT32)~(0x187), (UINT32) (0x81));\r
761\r
762 //\r
763 //USB_ULPI_0_NXT\r
764 //\r
765 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x358, (UINT32)~(0x7), (UINT32) (GPI));\r
766 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x350, (UINT32)~(0x187), (UINT32) (0x101));\r
767\r
768 //\r
769 //USB_ULPI_0_STP\r
770 //\r
771 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b8, (UINT32)~(0x7), (UINT32) (GPI));\r
772 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b0, (UINT32)~(0x187), (UINT32) (0x81));\r
773\r
774 //\r
775 //USB_ULPI_0_REFCLK\r
776 //\r
777 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x288, (UINT32)~(0x7), (UINT32) (GPI));\r
778 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x280, (UINT32)~(0x187), (UINT32) (0x101));\r
779\r
780 return EFI_SUCCESS;\r
781}\r
782\r
783EFI_STATUS\r
784DisableRTD3 (\r
785 VOID)\r
786{\r
787 //\r
788 //Disable RTD3\r
789 //\r
790 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x210, (UINT32)~(0x0f000007), (UINT32) (0x00));\r
791 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x1e0, (UINT32)~(0x0f000007), (UINT32) (0x00));\r
792\r
793 return EFI_SUCCESS;\r
794}\r
795\r
796/**\r
797 Platform specific initializations in stage1.\r
798\r
799 @param FfsHeader Pointer to the PEIM FFS file header.\r
800 @param PeiServices General purpose services available to every PEIM.\r
801\r
802 @retval EFI_SUCCESS Operation completed successfully.\r
803 @retval Otherwise Platform initialization failed.\r
804**/\r
805EFI_STATUS\r
806EFIAPI\r
807PlatformEarlyInitEntry (\r
808\r
809 IN EFI_PEI_FILE_HANDLE FileHandle,\r
810 IN CONST EFI_PEI_SERVICES **PeiServices\r
811 )\r
812{\r
813 EFI_STATUS Status;\r
814 SYSTEM_CONFIGURATION SystemConfiguration;\r
815 EFI_PLATFORM_INFO_HOB *PlatformInfo;\r
816 EFI_PEI_HOB_POINTERS Hob;\r
817 EFI_PLATFORM_CPU_INFO PlatformCpuInfo;\r
890f11d4 818 EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBlock;\r
c497dcc8
MK		 819 EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *NewDescriptorBlock;\r
820 UINTN Index;\r
821 UINTN MaxIndex;\r
822 UINT64 Base;\r
890f11d4 823 UINT64 Size;\r
c497dcc8 824 UINT64 NewSize;\r
890f11d4
MK		 825\r
826 //\r
c497dcc8 827 // Make sure base and size of the SMRAM region is aligned\r
890f11d4
MK		 828 //\r
829 Hob.Raw = GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid);\r
830 if (Hob.Raw != NULL) {\r
831 DescriptorBlock = GET_GUID_HOB_DATA (Hob.Raw);\r
c497dcc8
MK		 832 DEBUG ((DEBUG_INFO, "SMM PEI SMRAM Memory Reserved HOB\n"));\r
833 for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {\r
834 DEBUG((DEBUG_INFO, " SMRAM Descriptor[%02x]: Start=%016lx Size=%016lx State=%02x\n",\r
835 Index,\r
836 DescriptorBlock->Descriptor[Index].PhysicalStart,\r
837 DescriptorBlock->Descriptor[Index].PhysicalSize,\r
838 DescriptorBlock->Descriptor[Index].RegionState\r
839 ));\r
840 }\r
841\r
842 //\r
843 // Find the largest usable range of SMRAM between 1MB and 4GB\r
844 //\r
845 for (Index = 0, MaxIndex = 0, Size = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {\r
846 //\r
847 // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization\r
848 //\r
849 if ((DescriptorBlock->Descriptor[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {\r
850 continue;\r
851 }\r
852 //\r
853 // Skip any SMRAM region below 1MB\r
854 //\r
855 if (DescriptorBlock->Descriptor[Index].CpuStart < BASE_1MB) {\r
856 continue;\r
857 }\r
858 //\r
859 // Skip any SMRAM region that is above 4GB or crosses the 4GB boundary\r
860 //\r
861 if ((DescriptorBlock->Descriptor[Index].CpuStart + DescriptorBlock->Descriptor[Index].PhysicalSize) >= BASE_4GB) {\r
862 continue;\r
863 }\r
864 //\r
865 // Cache the largest SMRAM region index\r
866 //\r
867 if (DescriptorBlock->Descriptor[Index].PhysicalSize >= DescriptorBlock->Descriptor[MaxIndex].PhysicalSize) {\r
868 MaxIndex = Index;\r
869 }\r
870 }\r
871\r
872 //\r
873 // Find the extent of the contiguous SMRAM region that surrounds the largest usable SMRAM range\r
874 //\r
875 Base = DescriptorBlock->Descriptor[MaxIndex].CpuStart;\r
876 Size = DescriptorBlock->Descriptor[MaxIndex].PhysicalSize;\r
877 for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {\r
878 if (DescriptorBlock->Descriptor[Index].CpuStart < Base &&\r
879 Base == (DescriptorBlock->Descriptor[Index].CpuStart + DescriptorBlock->Descriptor[Index].PhysicalSize)) {\r
880 Base = DescriptorBlock->Descriptor[Index].CpuStart;\r
881 Size += DescriptorBlock->Descriptor[Index].PhysicalSize;\r
882 } else if ((Base + Size) == DescriptorBlock->Descriptor[Index].CpuStart) {\r
883 Size += DescriptorBlock->Descriptor[Index].PhysicalSize;\r
884 }\r
885 }\r
886\r
887 //\r
888 // Round SMRAM region up to nearest power of 2 that is at least 4KB\r
889 //\r
890 NewSize = MAX (LShiftU64 (1, HighBitSet64 (Size - 1) + 1), SIZE_4KB);\r
891 if ((Base & ~(NewSize - 1)) != Base) {\r
892 //\r
893 // SMRAM region Base Address has smaller alignment than SMRAM region Size\r
894 // This is not compatible with SMRR settings\r
895 //\r
896 DEBUG((DEBUG_ERROR, "ERROR: SMRAM Region Size has larger alignment than SMRAM Region Base\n"));\r
897 DEBUG((DEBUG_ERROR, " SMRAM Region Base=%016lx Size=%016lx\n", Base, NewSize));\r
898 ASSERT (FALSE);\r
899 } else if (Size != NewSize) {\r
900 //\r
901 // See if the size difference can be added to an adjacent descriptor that is already allocated\r
902 //\r
903 for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {\r
904 if ((DescriptorBlock->Descriptor[Index].CpuStart + DescriptorBlock->Descriptor[Index].PhysicalSize) == (Base + Size)) {\r
905 if (((DescriptorBlock->Descriptor[Index].RegionState) & EFI_ALLOCATED) != 0) {\r
906 DescriptorBlock->Descriptor[Index].PhysicalSize += (NewSize - Size);\r
907 Size = NewSize;\r
908 break;\r
909 }\r
910 }\r
911 }\r
912\r
913 if (Size != NewSize) {\r
914 //\r
915 // Add an allocated descriptor to the SMM PEI SMRAM Memory Reserved HOB to accomodate the larger size.\r
916 //\r
917 Index = DescriptorBlock->NumberOfSmmReservedRegions;\r
918 NewDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *)BuildGuidHob (\r
919 &gEfiSmmPeiSmramMemoryReserveGuid,\r
920 sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK) + ((Index + 1) * sizeof (EFI_SMRAM_DESCRIPTOR))\r
921 );\r
922 ASSERT (NewDescriptorBlock != NULL);\r
923\r
924 //\r
925 // Copy old EFI_SMRAM_HOB_DESCRIPTOR_BLOCK to new allocated region\r
926 //\r
927 CopyMem (\r
928 NewDescriptorBlock,\r
929 DescriptorBlock,\r
930 sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK) + (Index * sizeof (EFI_SMRAM_DESCRIPTOR))\r
931 );\r
932\r
933 //\r
934 // Make sure last descriptor in NewDescriptorBlock contains last descriptor from DescriptorBlock\r
935 //\r
936 CopyMem (\r
937 &NewDescriptorBlock->Descriptor[Index],\r
938 &NewDescriptorBlock->Descriptor[Index - 1],\r
939 sizeof (EFI_SMRAM_DESCRIPTOR)\r
940 );\r
941\r
942 //\r
943 // Fill next to last descriptor with an allocated descriptor that aligns the total size of SMRAM\r
944 //\r
945 NewDescriptorBlock->Descriptor[Index - 1].CpuStart = Base + Size;\r
946 NewDescriptorBlock->Descriptor[Index - 1].PhysicalStart = Base + Size;\r
947 NewDescriptorBlock->Descriptor[Index - 1].PhysicalSize = NewSize - Size;\r
948 NewDescriptorBlock->Descriptor[Index - 1].RegionState = DescriptorBlock->Descriptor[MaxIndex].RegionState | EFI_ALLOCATED;\r
949 NewDescriptorBlock->NumberOfSmmReservedRegions++;\r
950\r
951 //\r
952 // Invalidate the original gEfiSmmPeiSmramMemoryReserveGuid HOB\r
953 //\r
954 ZeroMem (&Hob.Guid->Name, sizeof (&Hob.Guid->Name));\r
955 }\r
956\r
957 Hob.Raw = GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid);\r
958 DescriptorBlock = GET_GUID_HOB_DATA (Hob.Raw);\r
959 DEBUG ((DEBUG_INFO, "SMM PEI SMRAM Memory Reserved HOB - Updated\n"));\r
960 for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {\r
961 DEBUG((DEBUG_INFO, " SMRAM Descriptor[%02x]: Start=%016lx Size=%016lx State=%02x\n",\r
962 Index,\r
963 DescriptorBlock->Descriptor[Index].PhysicalStart,\r
964 DescriptorBlock->Descriptor[Index].PhysicalSize,\r
965 DescriptorBlock->Descriptor[Index].RegionState\r
966 ));\r
967 }\r
968 }\r
890f11d4 969 }\r
3cbfba02
DW		 970\r
971 //\r
972 // Initialize SmbusPolicy PPI\r
973 //\r
974 Status = (*PeiServices)->InstallPpi(PeiServices, &mInstallSmbusPolicyPpi);\r
975 ASSERT_EFI_ERROR (Status);\r
976\r
977 //\r
978 // Initialize Stall PPIs\r
979 //\r
980 Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi);\r
981 ASSERT_EFI_ERROR (Status);\r
982\r
983 //\r
984 // Initialize platform PPIs\r
985 //\r
986 Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallSpeakerInterfacePpi);\r
987 ASSERT_EFI_ERROR (Status);\r
988\r
989 //\r
990 // Variable initialization\r
991 //\r
992 ZeroMem(&PlatformCpuInfo, sizeof(EFI_PLATFORM_CPU_INFO));\r
993\r
994 //\r
995 // Set the some PCI and chipset range as UC\r
996 // And align to 1M at leaset\r
997 //\r
998 Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r
999 ASSERT (Hob.Raw != NULL);\r
1000 PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);\r
1001\r
1002 //\r
1003 // Initialize PlatformInfo HOB\r
1004 //\r
1005 MultiPlatformInfoInit(PeiServices, PlatformInfo);\r
1006\r
1007 //\r
1008 // Do basic MCH init\r
1009 //\r
1010 MchInit (PeiServices);\r
1011\r
1012 //\r
1013 // Set the new boot mode\r
1014 //\r
1015 Status = UpdateBootMode (PeiServices, PlatformInfo);\r
1016 ASSERT_EFI_ERROR (Status);\r
1017\r
1018 SetPlatformBootMode (PeiServices, PlatformInfo);\r
1019\r
1020 //\r
1021 // Get setup variable. This can only be done after BootMode is updated\r
1022 //\r
1023 GetSetupVariable (PeiServices, &SystemConfiguration);\r
1024\r
1025 CheckOsSelection(PeiServices, &SystemConfiguration);\r
1026\r
1027 //\r
1028 // Update PlatformInfo HOB according to setup variable\r
1029 //\r
1030 PlatformInfoUpdate(PeiServices, PlatformInfo, &SystemConfiguration);\r
1031\r
1032 InitializePlatform (PeiServices, PlatformInfo, &SystemConfiguration);\r
1033\r
1034 //\r
1035 // Initialize VlvPolicy PPI\r
1036 //\r
1037 Status = VlvPolicyInit (PeiServices, &SystemConfiguration);\r
1038 ASSERT_EFI_ERROR (Status);\r
1039\r
1040 //\r
1041 // Soc specific GPIO setting\r
1042 //\r
1043 ConfigureSoCGpio(&SystemConfiguration);\r
1044\r
1045 //\r
1046 // Baylake Board specific.\r
1047 //\r
1048 if (PlatformInfo->BoardId == BOARD_ID_BL_RVP ||\r
1049 PlatformInfo->BoardId == BOARD_ID_BL_FFRD ||\r
1050 PlatformInfo->BoardId == BOARD_ID_BL_FFRD8 ||\r
1051 PlatformInfo->BoardId == BOARD_ID_BL_RVP_DDR3L ||\r
1052 PlatformInfo->BoardId == BOARD_ID_BL_STHI ||\r
1053 PlatformInfo->BoardId == BOARD_ID_BB_RVP ||\r
1054 PlatformInfo->BoardId == BOARD_ID_BS_RVP ||\r
1055 PlatformInfo->BoardId == BOARD_ID_MINNOW2 ||\r
8b7a63e7 1056 PlatformInfo->BoardId == BOARD_ID_MINNOW2_TURBOT||\r
3cbfba02
DW		 1057 PlatformInfo->BoardId == BOARD_ID_CVH) {\r
1058 ConfigureLpssAndSccGpio(&SystemConfiguration, PlatformInfo);\r
1059\r
1060 }\r
1061\r
1062\r
1063 //\r
1064 // Configure LPE\r
1065 // Alpine Valley and Bayley Bay board specific\r
1066 //\r
1067 ConfigureLpeGpio(&SystemConfiguration);\r
1068\r
1069 //\r
1070 // Bayley Bay Board specific.\r
1071 //\r
1072 ConfigureSciSmiGpioRout(PlatformInfo);\r
1073 if (SystemConfiguration.LpssI2C3Enabled == 1) {\r
1074 ConfigureMipiCsi();\r
1075 }\r
1076\r
1077\r
1078 //\r
1079 // Do basic CPU init\r
1080 //\r
1081 Status = PlatformCpuInit (PeiServices, &SystemConfiguration, &PlatformCpuInfo);\r
1082\r
1083 //\r
1084 // Perform basic SSA related platform initialization\r
1085 //\r
1086 PlatformSsaInit (&SystemConfiguration,PeiServices);\r
1087\r
1088\r
1089 //\r
1090 // Do basic PCH init\r
1091 //\r
1092 Status = PlatformPchInit (&SystemConfiguration, PeiServices, PlatformInfo->PlatformType);\r
1093 ASSERT_EFI_ERROR (Status);\r
1094\r
1095 //\r
1096 // Initialize platform PPIs\r
1097 //\r
1098 Status = (*PeiServices)->InstallPpi (PeiServices, &mPpiList[0]);\r
1099 ASSERT_EFI_ERROR (Status);\r
1100\r
1101 if (PlatformInfo->BoardId != BOARD_ID_CVH) {\r
1102 InstallPlatformClocksNotify (PeiServices);\r
1103 InstallPlatformSysCtrlGPIONotify(PeiServices);\r
1104 }\r
1105\r
1106 //\r
1107 // Initialize platform PPIs\r
1108 //\r
1109 Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);\r
1110 ASSERT_EFI_ERROR (Status);\r
1111\r
1112 //\r
1113 // Initialize Measured Boot\r
1114 //\r
1115 Status = MeasuredBootInit (PeiServices, &SystemConfiguration);\r
1116 ASSERT_EFI_ERROR (Status);\r
1117\r
1118 return Status;\r
1119}\r
1120\r
1121/**\r
1122\r
1123 Return the mainblockcompact Fv.\r
1124\r
1125 @param FvNumber Our enumeration of the firmware volumes we care about.\r
1126\r
1127 @param FvAddress Base Address of the memory containing the firmware volume\r
1128\r
1129 @retval EFI_SUCCESS\r
1130 @retval EFI_NOT_FOUND\r
1131\r
1132**/\r
1133EFI_STATUS\r
1134EFIAPI\r
1135FindFv (\r
1136 IN EFI_PEI_FIND_FV_PPI *This,\r
1137 IN CONST EFI_PEI_SERVICES **PeiServices,\r
1138 IN OUT UINT8 *FvNumber,\r
1139 OUT EFI_FIRMWARE_VOLUME_HEADER **FVAddress\r
1140 )\r
1141{\r
1142 //\r
1143 // At present, we only have one Fv to search\r
1144 //\r
1145 if (*FvNumber == 0) {\r
1146 *FvNumber = 1;\r
1147 *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FixedPcdGet32 (PcdFlashFvMainBase);\r
1148 return EFI_SUCCESS;\r
1149 }\r
1150 else if (*FvNumber == 1) {\r
1151 *FvNumber = 2;\r
1152 *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FixedPcdGet32 (PcdFlashFvRecovery2Base);\r
1153 return EFI_SUCCESS;\r
1154 }\r
1155 else { // Not the one Fv we care about\r
1156 return EFI_NOT_FOUND;\r
1157 }\r
1158}\r
1159\r
1160EFI_STATUS\r
1161EFIAPI\r
1162CpuOnlyReset (\r
1163 IN CONST EFI_PEI_SERVICES **PeiServices\r
1164 )\r
1165{\r
1166// MsgBus32Write(CDV_UNIT_PUNIT, PUNIT_CPU_RST, 0x01)\r
1167#ifdef __GNUC__\r
1168 __asm__\r
1169 (\r
1170 "xorl %ecx, %ecx\n"\r
1171 "1:hlt; hlt; hlt\n"\r
1172 "jmp 1b\n"\r
1173 );\r
1174#else\r
1175 _asm {\r
1176 xor ecx, ecx\r
1177 HltLoop:\r
1178 hlt\r
1179 hlt\r
1180 hlt\r
1181 loop HltLoop\r
1182 }\r
1183#endif\r
1184 //\r
1185 // If we get here we need to mark it as a failure.\r
1186 //\r
1187 return EFI_UNSUPPORTED;\r
1188}\r
1189\r
1190\r
1191#ifdef __GNUC__\r
1192#pragma GCC pop_options\r
1193#else\r
1194#pragma optimize ("", on)\r
1195#endif\r
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