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Vlv2TbltDevicePkg/PlatformInitPei: Better SMRAM size alignment
[mirror_edk2.git] / Vlv2TbltDevicePkg / PlatformInitPei / PlatformEarlyInit.c
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3cbfba02
DW		 1/** @file\r
2\r
890f11d4 3 Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>\r
3cbfba02
DW		 4 \r\r
5 This program and the accompanying materials are licensed and made available under\r\r
6 the terms and conditions of the BSD License that accompanies this distribution. \r\r
7 The full text of the license may be found at \r\r
8 http://opensource.org/licenses/bsd-license.php. \r\r
9 \r\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r
12 \r\r
13\r
14\r
15Module Name:\r
16\r
17 PlatformEarlyInit.c\r
18\r
19Abstract:\r
20\r
21 Do platform specific PEI stage initializations.\r
22\r
23--*/\r
24\r
25\r
26#include "PlatformEarlyInit.h"\r
27\r
28#ifdef __GNUC__\r
29#pragma GCC push_options\r
30#pragma GCC optimize ("O0")\r
31#else\r
32#pragma optimize ("", off)\r
33#endif\r
34\r
35\r
36\r
37static EFI_PEI_STALL_PPI mStallPpi = {\r
38 PEI_STALL_RESOLUTION,\r
39 Stall\r
40};\r
41\r
42static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi = {\r
43 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
44 &gEfiPeiStallPpiGuid,\r
45 &mStallPpi\r
46};\r
47\r
48//\r
49// The reserved SMBus addresses are defined in PlatformDxe.h file.\r
50//\r
51static UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;\r
52static PEI_SMBUS_POLICY_PPI mSmbusPolicyPpi = {\r
53 SMBUS_BASE_ADDRESS,\r
54 SMBUS_BUS_DEV_FUNC,\r
55 PLATFORM_NUM_SMBUS_RSVD_ADDRESSES,\r
56 mSmbusRsvdAddresses\r
57};\r
58\r
59static EFI_PEI_PPI_DESCRIPTOR mInstallSmbusPolicyPpi = {\r
60 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
61 &gPeiSmbusPolicyPpiGuid,\r
62 &mSmbusPolicyPpi\r
63};\r
64static PEI_SPEAKER_IF_PPI mSpeakerInterfacePpi = {\r
65 ProgramToneFrequency,\r
66 GenerateBeepTone\r
67};\r
68\r
69static EFI_PEI_PPI_DESCRIPTOR mInstallSpeakerInterfacePpi = {\r
70 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
71 &gPeiSpeakerInterfacePpiGuid,\r
72 &mSpeakerInterfacePpi\r
73};\r
74\r
75static EFI_PEI_RESET_PPI mResetPpi = { IchReset };\r
76\r
77\r
78static EFI_PEI_FIND_FV_PPI mEfiFindFvPpi = {\r
79 (EFI_PEI_FIND_FV_FINDFV)FindFv\r
80};\r
81\r
82static EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {\r
83 {\r
84 EFI_PEI_PPI_DESCRIPTOR_PPI,\r
85 &gEfiPeiMasterBootModePpiGuid,\r
86 NULL\r
87 },\r
88 {\r
89 EFI_PEI_PPI_DESCRIPTOR_PPI,\r
90 &gEfiPeiResetPpiGuid,\r
91 &mResetPpi\r
92 },\r
93 {\r
94 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
95 &gEfiFindFvPpiGuid,\r
96 &mEfiFindFvPpi\r
97 }\r
98};\r
99\r
100static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {\r
101 {\r
102 EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,\r
103 &gEfiEndOfPeiSignalPpiGuid,\r
104 (EFI_PEIM_NOTIFY_ENTRY_POINT)EndOfPeiPpiNotifyCallback\r
105 },\r
106 {\r
107 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
108 &gEfiPeiMemoryDiscoveredPpiGuid,\r
109 (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotifyCallback\r
110 }\r
111\r
112};\r
113\r
114\r
115/**\r
116\r
117 Parse the status registers for figuring out the wake-up event and save it into\r
118 an GUID HOB which will be referenced later. However, modification is required\r
119 to meet the chipset register definition and the practical hardware design. Thus,\r
120 this is just an example.\r
121\r
122\r
123 @param PeiServices pointer to the PEI Service Table\r
124 @param EFI_SUCCESS Always return Success\r
125\r
126 @retval None\r
127\r
128\r
129**/\r
130EFI_STATUS\r
131EFIAPI\r
132GetWakeupEventAndSaveToHob (\r
133 IN CONST EFI_PEI_SERVICES **PeiServices\r
134 )\r
135{\r
136 UINT16 Pm1Sts;\r
137 UINTN Gpe0Sts;\r
138 UINTN WakeEventData;\r
139\r
140 //\r
141 // Read the ACPI registers\r
142 //\r
143 Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);\r
144 Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS);\r
145\r
146 //\r
147 // Figure out the wake-up event\r
148 //\r
149 if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) != 0) {\r
150 WakeEventData = SMBIOS_WAKEUP_TYPE_POWER_SWITCH;\r
151 } else if (((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) != 0)) {\r
152 WakeEventData = SMBIOS_WAKEUP_TYPE_PCI_PME;\r
153 } else if (Gpe0Sts != 0) {\r
154 WakeEventData = SMBIOS_WAKEUP_TYPE_OTHERS;\r
155 } else {\r
156 WakeEventData = SMBIOS_WAKEUP_TYPE_UNKNOWN;\r
157 }\r
158\r
159 DEBUG ((EFI_D_ERROR, "ACPI Wake Status Register: %04x\n", Pm1Sts));\r
c5136804 160 DEBUG ((EFI_D_ERROR, "ACPI Wake Event Data: %02x\n", WakeEventData));\r
3cbfba02
DW		 161\r
162 return EFI_SUCCESS;\r
163}\r
164\r
165EFI_STATUS\r
166GetSetupVariable (\r
167 IN CONST EFI_PEI_SERVICES **PeiServices,\r
168 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
169 )\r
170{\r
171 UINTN VariableSize;\r
172 EFI_STATUS Status;\r
173 EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;\r
174\r
175 VariableSize = sizeof (SYSTEM_CONFIGURATION);\r
176 ZeroMem (SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));\r
177\r
178 Status = (*PeiServices)->LocatePpi (\r
179 PeiServices,\r
180 &gEfiPeiReadOnlyVariable2PpiGuid,\r
181 0,\r
182 NULL,\r
183 (void **)&Variable\r
184 );\r
185 ASSERT_EFI_ERROR (Status);\r
186\r
187 //\r
188 // Use normal setup default from NVRAM variable,\r
189 // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.\r
190 //\r
191 VariableSize = sizeof(SYSTEM_CONFIGURATION);\r
192 Status = Variable->GetVariable (\r
193 Variable,\r
194 L"Setup",\r
195 &gEfiSetupVariableGuid,\r
196 NULL,\r
197 &VariableSize,\r
198 SystemConfiguration\r
199 );\r
620f2891
TH		 200 if (EFI_ERROR (Status) || VariableSize != sizeof(SYSTEM_CONFIGURATION)) {\r
201 //The setup variable is corrupted\r
202 VariableSize = sizeof(SYSTEM_CONFIGURATION);\r
203 Status = Variable->GetVariable(\r
204 Variable,\r
205 L"SetupRecovery",\r
206 &gEfiSetupVariableGuid,\r
207 NULL,\r
208 &VariableSize,\r
209 SystemConfiguration\r
210 );\r
211 ASSERT_EFI_ERROR (Status);\r
212 } \r
3cbfba02
DW		 213 return Status;\r
214}\r
215\r
216EFI_STATUS\r
217VlvPolicyInit (\r
218 IN CONST EFI_PEI_SERVICES **PeiServices,\r
219 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
220 )\r
221{\r
222 EFI_STATUS Status;\r
223 EFI_PEI_PPI_DESCRIPTOR *mVlvPolicyPpiDesc;\r
224 VLV_POLICY_PPI *mVlvPolicyPpi;\r
225\r
226 Status = (*PeiServices)->AllocatePool(\r
227 PeiServices,\r
228 sizeof (EFI_PEI_PPI_DESCRIPTOR),\r
229 (void **)&mVlvPolicyPpiDesc\r
230 );\r
231 ASSERT_EFI_ERROR (Status);\r
232\r
233 Status = (*PeiServices)->AllocatePool(\r
234 PeiServices,\r
235 sizeof (VLV_POLICY_PPI),\r
236 (void **)&mVlvPolicyPpi\r
237 );\r
238 ASSERT_EFI_ERROR (Status);\r
239\r
240 //\r
241 // Initialize PPI\r
242 //\r
243 (*PeiServices)->SetMem ((VOID *)mVlvPolicyPpi, sizeof (VLV_POLICY_PPI), 0);\r
244 mVlvPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r
245 mVlvPolicyPpiDesc->Guid = &gVlvPolicyPpiGuid;\r
246 mVlvPolicyPpiDesc->Ppi = mVlvPolicyPpi;\r
247 mVlvPolicyPpi->GtConfig.PrimaryDisplay = SystemConfiguration->PrimaryVideoAdaptor;\r
248 mVlvPolicyPpi->GtConfig.IgdDvmt50PreAlloc = SystemConfiguration->IgdDvmt50PreAlloc;\r
249 mVlvPolicyPpi->GtConfig.ApertureSize = SystemConfiguration->IgdApertureSize;\r
250 mVlvPolicyPpi->GtConfig.GttSize = SystemConfiguration->GTTSize;\r
251 if (SystemConfiguration->PrimaryVideoAdaptor != 2) {\r
252 mVlvPolicyPpi->GtConfig.InternalGraphics = SystemConfiguration->Igd;\r
253 } else {\r
254 mVlvPolicyPpi->GtConfig.InternalGraphics = 0;\r
255 }\r
256\r
257\r
258 mVlvPolicyPpi->GtConfig.IgdTurboEn = 1;\r
259\r
260\r
261 mVlvPolicyPpi->PlatformData.FastBoot = SystemConfiguration->FastBoot;\r
262 mVlvPolicyPpi->PlatformData.DynSR = 1;\r
263 DEBUG ((EFI_D_ERROR, "Setup Option ISPEn: 0x%x\n", SystemConfiguration->ISPEn));\r
264 mVlvPolicyPpi->ISPEn = SystemConfiguration->ISPEn;\r
265 DEBUG ((EFI_D_ERROR, "Setup Option ISPDevSel: 0x%x\n", SystemConfiguration->ISPDevSel));\r
266 mVlvPolicyPpi->ISPPciDevConfig = SystemConfiguration->ISPDevSel;\r
267 if (SystemConfiguration->ISPEn == 0) {\r
268 mVlvPolicyPpi->ISPPciDevConfig = 0;\r
269 DEBUG ((EFI_D_ERROR, "Update Setup Option ISPDevSel: 0x%x\n", mVlvPolicyPpi->ISPPciDevConfig));\r
270 }\r
271 Status = (*PeiServices)->InstallPpi(\r
272 PeiServices,\r
273 mVlvPolicyPpiDesc\r
274 );\r
275 ASSERT_EFI_ERROR (Status);\r
276\r
277 return EFI_SUCCESS;\r
278}\r
279\r
280\r
281EFI_STATUS\r
282ConfigureSoCGpio (\r
283 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
284 )\r
285{\r
286\r
287 DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------start\n"));\r
288 if (SystemConfiguration->eMMCBootMode== 1) {// Auto detection mode\r
289 DEBUG ((EFI_D_ERROR, "Auto detection mode------------start\n"));\r
290\r
291 //\r
292 //Silicon Steppings\r
293 //\r
294 switch (PchStepping()) {\r
295 case PchA0: // SOC A0 and A1\r
296 case PchA1:\r
297 DEBUG ((EFI_D_ERROR, "SOC A0/A1: eMMC 4.41 GPIO Configuration\n"));\r
298 SystemConfiguration->LpsseMMCEnabled = 1;\r
299 SystemConfiguration->LpsseMMC45Enabled = 0;\r
300 break;\r
301 case PchB0: // SOC B0 and later\r
302 default:\r
303 DEBUG ((EFI_D_ERROR, "SOC B0 and later: eMMC 4.5 GPIO Configuration\n"));\r
304 SystemConfiguration->LpsseMMCEnabled = 0;\r
305 SystemConfiguration->LpsseMMC45Enabled = 1;\r
306 break;\r
307 }\r
308 } else if (SystemConfiguration->eMMCBootMode == 2) { // eMMC 4.41\r
309 DEBUG ((EFI_D_ERROR, "Force to eMMC 4.41 GPIO Configuration\n"));\r
310 SystemConfiguration->LpsseMMCEnabled = 1;\r
311 SystemConfiguration->LpsseMMC45Enabled = 0;\r
312 } else if (SystemConfiguration->eMMCBootMode == 3) { // eMMC 4.5\r
313 DEBUG ((EFI_D_ERROR, "Force to eMMC 4.5 GPIO Configuration\n"));\r
314 SystemConfiguration->LpsseMMCEnabled = 0;\r
315 SystemConfiguration->LpsseMMC45Enabled = 1;\r
316\r
317 } else { // Disable eMMC controllers\r
318 DEBUG ((EFI_D_ERROR, "Disable eMMC GPIO controllers\n"));\r
319 SystemConfiguration->LpsseMMCEnabled = 0;\r
320 SystemConfiguration->LpsseMMC45Enabled = 0;\r
321 }\r
322\r
323 /*\r
324 20.1.1 EMMC\r
325 SDMMC1_CLK - write 0x2003ED01 to IOBASE + 0x03E0\r
326 SDMMC1_CMD - write 0x2003EC81 to IOBASE + 0x0390\r
327 SDMMC1_D0 - write 0x2003EC81 to IOBASE + 0x03D0\r
328 SDMMC1_D1 - write 0x2003EC81 to IOBASE + 0x0400\r
329 SDMMC1_D2 - write 0x2003EC81 to IOBASE + 0x03B0\r
330 SDMMC1_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0360\r
331 MMC1_D4_SD_WE - write 0x2003EC81 to IOBASE + 0x0380\r
332 MMC1_D5 - write 0x2003EC81 to IOBASE + 0x03C0\r
333 MMC1_D6 - write 0x2003EC81 to IOBASE + 0x0370\r
334 MMC1_D7 - write 0x2003EC81 to IOBASE + 0x03F0\r
335 MMC1_RESET_B - write 0x2003ED01 to IOBASE + 0x0330\r
336 */\r
337 if (SystemConfiguration->LpsseMMCEnabled== 1) {\r
338 MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED01); //EMMC 4.41\r
339 MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC81);\r
340 MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC81);\r
341 MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC81);\r
342 MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC81);\r
343 MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC81);\r
344 MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC81);\r
345 MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC81);\r
346 MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC81);\r
347 MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC81);\r
348 MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED01);\r
349 }\r
350\r
351 /*\r
352 eMMC 4.5 controller\r
353 SDMMC1_CLK - write 0x2003ED03 to IOBASE + 0x03E0\r
354 SDMMC1_CMD - write 0x2003EC83 to IOBASE + 0x0390\r
355 SDMMC1_D0 - write 0x2003EC83 to IOBASE + 0x03D0\r
356 SDMMC1_D1 - write 0x2003EC83 to IOBASE + 0x0400\r
357 SDMMC1_D2 - write 0x2003EC83 to IOBASE + 0x03B0\r
358 SDMMC1_D3_CD_B - write 0x2003EC83 to IOBASE + 0x0360\r
359 MMC1_D4_SD_WE - write 0x2003EC83 to IOBASE + 0x0380\r
360 MMC1_D5 - write 0x2003EC83 to IOBASE + 0x03C0\r
361 MMC1_D6 - write 0x2003EC83 to IOBASE + 0x0370\r
362 MMC1_D7 - write 0x2003EC83 to IOBASE + 0x03F0\r
363 MMC1_RESET_B - write 0x2003ED03 to IOBASE + 0x0330\r
364 */\r
365 if (SystemConfiguration->LpsseMMC45Enabled== 1) {\r
366 MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED03); // EMMC 4.5\r
367 MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC83);\r
368 MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC83);\r
369 MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC83);\r
370 MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC83);\r
371 MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC83);\r
372 MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC83);\r
373 MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC83);\r
374 MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC83);\r
375 MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC83);\r
376 MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED03);\r
377\r
378 }\r
379\r
380//\r
381// Change GPIOC_0 setting to allow MMIO access under Android.\r
382//\r
383 IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL,\r
384 (IoRead32(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL) & (UINT32)~BIT0));\r
385 DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------end\n"));\r
386 return EFI_SUCCESS;\r
387}\r
388\r
389EFI_STATUS\r
390MeasuredBootInit (\r
391 IN CONST EFI_PEI_SERVICES **PeiServices,\r
392 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
393 )\r
394{\r
395 if (SystemConfiguration->MeasuredBootEnable) {\r
396 PcdSetBool (PcdMeasuredBootEnable, TRUE);\r
397 } else {\r
398 PcdSetBool (PcdMeasuredBootEnable, FALSE);\r
399 }\r
400\r
401 return EFI_SUCCESS;\r
402}\r
403\r
404\r
405EFI_STATUS\r
406ConfigureLpssAndSccGpio (\r
407 IN SYSTEM_CONFIGURATION *SystemConfiguration,\r
408 IN EFI_PLATFORM_INFO_HOB *PlatformInfo\r
409 )\r
410{\r
411 /*One time configuration to each GPIO controller PSB_CONF register should be done before starting pad configuration:\r
412 GPIO SCORE - write 0x01001002 to IOBASE + 0x0700\r
413 GPIO NCORE - write 0x01001002 to IOBASE + 0x0F00\r
414 GPIO SSUS - write 0x01001002 to IOBASE + 0x1700\r
415 */\r
416 DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------start\n"));\r
417\r
418 /*\r
419 19.1.1 PWM0\r
420 PWM0 - write 0x2003CD01 to IOBASE + 0x00A0\r
421 19.1.2 PWM1\r
422 PWM0 - write 0x2003CD01 to IOBASE + 0x00B0\r
423 */\r
424 if (SystemConfiguration->LpssPwm0Enabled== 1) {\r
425 MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD01);\r
426 } else if (SystemConfiguration->LpssPwm0Enabled== 0) {\r
427 MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD00);\r
428 }\r
429\r
430 if (SystemConfiguration->LpssPwm1Enabled== 1) {\r
431 MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CC01);\r
432 } else if (SystemConfiguration->LpssPwm1Enabled== 0) {\r
433 MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CD00);\r
434 }\r
435\r
436 /*\r
437 19.1.3 UART1\r
438 UART1_RXD-L - write 0x2003CC81 to IOBASE + 0x0020\r
439 UART1_TXD-0 - write 0x2003CC81 to IOBASE + 0x0010\r
440 UART1_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0000\r
441 UART1_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0040\r
442 */\r
443 if (SystemConfiguration->LpssHsuart0Enabled== 1) {\r
444 MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC81); // uart1\r
445 MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC81);\r
446 if (SystemConfiguration->LpssHsuart0FlowControlEnabled== 0) {\r
447 DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[0]\n"));\r
448 MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC80);\r
449 MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC80);\r
450 } else {\r
451 DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[1]\n"));\r
452 MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC81);\r
453 MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC01);//W/A HSD 4752617 0x2003CC81\r
454 }\r
455 } else if (SystemConfiguration->LpssHsuart0Enabled== 0) {\r
456 MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC80); // uart1\r
457 MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC80);\r
458 }\r
459\r
460\r
461 /*\r
462 19.1.4 UART2\r
463 UART2_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0090\r
464 UART2_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0080\r
465 UART2_RXD-H - write 0x2003CC81 to IOBASE + 0x0060\r
466 UART2_TXD-0 - write 0x2003CC81 to IOBASE + 0x0070\r
467 */\r
468 if (SystemConfiguration->LpssHsuart1Enabled== 1) {\r
469 MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC81);\r
470 MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC81);\r
471\r
472 if (SystemConfiguration->LpssHsuart1FlowControlEnabled== 0) {\r
473 DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[0]\n"));\r
474 MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC80); // UART2_RTS_B\r
475 MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC80); // UART2_CTS_B\r
476 } else {\r
477 DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[1]\n"));\r
478 MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC81); // uart2\r
479 MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC01); //W/A HSD 4752617 0x2003CC81\r
480 }\r
481 } else if (SystemConfiguration->LpssHsuart1Enabled== 0) {\r
482 MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC80);\r
483 MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC80);\r
484 }\r
485\r
486 /*\r
487 19.1.5 SPI\r
488 SPI1_CS0_B - write 0x2003CC81 to IOBASE + 0x0110\r
489 SPI1_CLK - write 0x2003CD01 to IOBASE + 0x0100\r
490 SPI1_MOSI - write 0x2003CC81 to IOBASE + 0x0130\r
491 SPI1_MISO - write 0x2003CC81 to IOBASE + 0x0120\r
492 */\r
493 if (SystemConfiguration->LpssSpiEnabled== 1) {\r
494 MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003CC81); // SPI\r
495 MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003CD01);\r
496 MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003CC81);\r
497 MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003CC81);\r
498 } else if (SystemConfiguration->LpssSpiEnabled== 0) {\r
499 MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003cc80);\r
500 MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003cc80);\r
501 MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003cc80);\r
502 MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003cc80);\r
503 }\r
504\r
505 /*\r
506 19.1.6 I2C0\r
507 I2C0_SDA-OD-O - write 0x2003CC81 to IOBASE + 0x0210\r
508 I2C0_SCL-OD-O - write 0x2003CC81 to IOBASE + 0x0200\r
509 */\r
510 if (SystemConfiguration->LpssI2C0Enabled== 1) {\r
511 MmioWrite32 (IO_BASE_ADDRESS + 0x0210, 0x2003C881);\r
512 MmioWrite32 (IO_BASE_ADDRESS + 0x0200, 0x2003C881);\r
513 }\r
514 /*\r
515 19.1.7 I2C1\r
516 I2C1_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01F0\r
517 I2C1_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01E0\r
518 */\r
519\r
520 if (SystemConfiguration->LpssI2C1Enabled== 1) {\r
521 MmioWrite32 (IO_BASE_ADDRESS + 0x01F0, 0x2003C881);\r
522 MmioWrite32 (IO_BASE_ADDRESS + 0x01E0, 0x2003C881);\r
523 }\r
524 /*\r
525 19.1.8 I2C2\r
526 I2C2_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01D0\r
527 I2C2_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01B0\r
528 */\r
529 if (SystemConfiguration->LpssI2C2Enabled== 1) {\r
530 MmioWrite32 (IO_BASE_ADDRESS + 0x01D0, 0x2003C881);\r
531 MmioWrite32 (IO_BASE_ADDRESS + 0x01B0, 0x2003C881);\r
532 }\r
533 /*\r
534 19.1.9 I2C3\r
535 I2C3_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0190\r
536 I2C3_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01C0\r
537 */\r
538 if (SystemConfiguration->LpssI2C3Enabled== 1) {\r
539 MmioWrite32 (IO_BASE_ADDRESS + 0x0190, 0x2003C881);\r
540 MmioWrite32 (IO_BASE_ADDRESS + 0x01C0, 0x2003C881);\r
541 }\r
542 /*\r
543 19.1.10 I2C4\r
544 I2C4_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01A0\r
545 I2C4_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0170\r
546 */\r
547 if (SystemConfiguration->LpssI2C4Enabled== 1) {\r
548 MmioWrite32 (IO_BASE_ADDRESS + 0x01A0, 0x2003C881);\r
549 MmioWrite32 (IO_BASE_ADDRESS + 0x0170, 0x2003C881);\r
550 }\r
551 /*\r
552 19.1.11 I2C5\r
553 I2C5_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0150\r
554 I2C5_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0140\r
555 */\r
556 //touch 1.7M support on i2c5(from 0) need 2k PULL-UP.\r
557 if (SystemConfiguration->LpssI2C5Enabled== 1) {\r
558 MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C881);\r
559 MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C881);\r
560 } else if(SystemConfiguration->LpssI2C5Enabled== 0) {\r
561 MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C880);\r
562 MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C880);\r
563 }\r
564 /*\r
565 19.1.12 I2C6\r
566 I2C6_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0180\r
567 I2C6_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0160\r
568 */\r
569 if (SystemConfiguration->LpssI2C6Enabled== 1) {\r
570 MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C881);\r
571 MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C881);\r
572 } else if (SystemConfiguration->LpssI2C6Enabled== 0) {\r
573 MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C880);\r
574 MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C880);\r
575 }\r
576\r
577\r
578 /*\r
579 20.1.2 SDIO\r
580 SDMMC2_CLK - write 0x2003ED01 to IOBASE + 0x0320\r
581 SDMMC2_CMD - write 0x2003EC81 to IOBASE + 0x0300\r
582 SDMMC2_D0 - write 0x2003EC81 to IOBASE + 0x0350\r
583 SDMMC2_D1 - write 0x2003EC81 to IOBASE + 0x02F0\r
584 SDMMC2_D2 - write 0x2003EC81 to IOBASE + 0x0340\r
585 SDMMC2_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0310\r
586 */\r
587 if (SystemConfiguration->LpssSdioEnabled== 1) {\r
588 MmioWrite32 (IO_BASE_ADDRESS + 0x0320, 0x2003ED01);//SDIO\r
589 MmioWrite32 (IO_BASE_ADDRESS + 0x0300, 0x2003EC81);\r
590 MmioWrite32 (IO_BASE_ADDRESS + 0x0350, 0x2003EC81);\r
591 MmioWrite32 (IO_BASE_ADDRESS + 0x02F0, 0x2003EC81);\r
592 MmioWrite32 (IO_BASE_ADDRESS + 0x0340, 0x2003EC81);\r
593 MmioWrite32 (IO_BASE_ADDRESS + 0x0310, 0x2003EC81);\r
594 }\r
595\r
596 /*\r
597 20.1.3 SD Card\r
598 SDMMC3_1P8_EN - write 0x2003CD01 to IOBASE + 0x03F0\r
599 SDMMC3_CD_B - write 0x2003CC81 to IOBASE + 0x03A0\r
600 SDMMC3_CLK - write 0x2003CD01 to IOBASE + 0x02B0\r
601 SDMMC3_CMD - write 0x2003CC81 to IOBASE + 0x02C0\r
602 SDMMC3_D0 - write 0x2003CC81 to IOBASE + 0x02E0\r
603 SDMMC3_D1 - write 0x2003CC81 to IOBASE + 0x0290\r
604 SDMMC3_D2 - write 0x2003CC81 to IOBASE + 0x02D0\r
605 SDMMC3_D3 - write 0x2003CC81 to IOBASE + 0x02A0\r
606 SDMMC3_PWR_EN_B - write 0x2003CC81 to IOBASE + 0x0690\r
607 SDMMC3_WP - write 0x2003CC82 to IOBASE + 0x0160\r
608 */\r
609 if (SystemConfiguration->LpssSdcardEnabled == 1) {\r
610 if (!((PlatformInfo->BoardId == BOARD_ID_BL_FFRD && PlatformInfo->BoardRev== PR11) && (SystemConfiguration->CfioPnpSettings == 1))) {\r
611 MmioWrite32 (IO_BASE_ADDRESS + 0x05F0, 0x2003CD01);//SDCARD\r
612 MmioWrite32 (IO_BASE_ADDRESS + 0x02B0, 0x2003CD01);\r
613 MmioWrite32 (IO_BASE_ADDRESS + 0x02C0, 0x2003CC81);\r
614 MmioWrite32 (IO_BASE_ADDRESS + 0x02E0, 0x2003CC81);\r
615 MmioWrite32 (IO_BASE_ADDRESS + 0x0290, 0x2003CC81);\r
616 MmioWrite32 (IO_BASE_ADDRESS + 0x02D0, 0x2003CC81);\r
617 MmioWrite32 (IO_BASE_ADDRESS + 0x02A0, 0x2003CC81);\r
618 MmioWrite32 (IO_BASE_ADDRESS + 0x0690, 0x2003CC81);\r
619 MmioWrite32 (IO_BASE_ADDRESS + 0x0650, 0x2003CC82); //GPIOC_7 set to WP Pin\r
620 }\r
621 }\r
622\r
623\r
624 DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------end\n"));\r
625 return EFI_SUCCESS;\r
626}\r
627\r
628EFI_STATUS\r
629ConfigureLpeGpio (\r
630 IN SYSTEM_CONFIGURATION *SystemConfiguration\r
631 )\r
632{\r
633 DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------start\n"));\r
634\r
635 if (SystemConfiguration->PchAzalia == 0) {\r
636 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x220, (UINT32)~(0x7), (UINT32) (0x01));\r
637 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x250, (UINT32)~(0x7), (UINT32) (0x01));\r
638 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x240, (UINT32)~(0x7), (UINT32) (0x01));\r
639 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x260, (UINT32)~(0x7), (UINT32) (0x01));\r
640 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x270, (UINT32)~(0x7), (UINT32) (0x01));\r
641 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x230, (UINT32)~(0x7), (UINT32) (0x01));\r
642 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x280, (UINT32)~(0x7), (UINT32) (0x01));\r
643 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x540, (UINT32)~(0x7), (UINT32) (0x01));\r
644 }\r
645\r
646 DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------end\n"));\r
647\r
648 return EFI_SUCCESS;\r
649}\r
650\r
651EFI_STATUS\r
652ConfigureSciSmiGpioRout (\r
653 IN EFI_PLATFORM_INFO_HOB *PlatformInfo)\r
654{\r
655 UINT32 GPI_Routing;\r
656\r
657 GPI_Routing = MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT);\r
658\r
659 //\r
660 // For FAB3, Route GPIO_CORE 0 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI\r
661 //\r
662 if(PlatformInfo->BoardRev == 3) {\r
663 GPI_Routing = GPI_Routing & 0xfffc3ffc;\r
664 GPI_Routing = GPI_Routing | 0x00024002;\r
665 }\r
666\r
667 //\r
668 // For FAB2/1, Route GPIO_CORE 7 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI\r
669 //\r
670 else {\r
671 GPI_Routing = GPI_Routing & 0x3fff3ffc;\r
672 GPI_Routing = GPI_Routing | 0x80004002;\r
673 }\r
674 MmioWrite32((PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT), GPI_Routing);\r
675\r
676 return EFI_SUCCESS;\r
677}\r
678\r
679EFI_STATUS\r
680ConfigureMipiCsi (\r
681 VOID)\r
682{\r
683 //\r
684 //Configure the platform clock for MIPI-CSI usage\r
685 //PLT_CLK0\r
686 //\r
687 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x6a0, (UINT32)~(0x7), (UINT32) (0x01));\r
688\r
689 //\r
690 //PLT_CLK1\r
691 //\r
692 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x570, (UINT32)~(0x7), (UINT32) (0x01));\r
693\r
694 //\r
695 //PLT_CLK2\r
696 //\r
697 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x5B0, (UINT32)~(0x7), (UINT32) (0x01));\r
698\r
699 return EFI_SUCCESS;\r
700}\r
701\r
702EFI_STATUS\r
703ConfigureUSBULPI (\r
704 VOID)\r
705{\r
706 //\r
707 //Configure USB ULPI\r
708 //USB_ULPI_0_CLK\r
709 //\r
710 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x338, (UINT32)~(0x7), (UINT32) (GPI));\r
711 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x330, (UINT32)~(0x187), (UINT32) (0x101));\r
712\r
713 //\r
714 //USB_ULPI_0_DATA0\r
715 //\r
716 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x388, (UINT32)~(0x7), (UINT32) (GPI));\r
717 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x380, (UINT32)~(0x187), (UINT32) (0x101));\r
718\r
719 //\r
720 //USB_ULPI_0_DATA1\r
721 //\r
722 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x368, (UINT32)~(0x7), (UINT32) (GPI));\r
723 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x360, (UINT32)~(0x187), (UINT32) (0x101));\r
724\r
725 //\r
726 //USB_ULPI_0_DATA2\r
727 //\r
728 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x318, (UINT32)~(0x7), (UINT32) (GPI));\r
729 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x310, (UINT32)~(0x187), (UINT32) (0x101));\r
730\r
731 //\r
732 //USB_ULPI_0_DATA3\r
733 //\r
734 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x378, (UINT32)~(0x7), (UINT32) (GPI));\r
735 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x370, (UINT32)~(0x187), (UINT32) (0x101));\r
736\r
737 //\r
738 //USB_ULPI_0_DATA4\r
739 //\r
740 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x308, (UINT32)~(0x7), (UINT32) (GPI));\r
741 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x300, (UINT32)~(0x187), (UINT32) (0x101));\r
742\r
743 //\r
744 //USB_ULPI_0_DATA5\r
745 //\r
746 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x398, (UINT32)~(0x7), (UINT32) (GPI));\r
747 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x390, (UINT32)~(0x187), (UINT32) (0x101));\r
748\r
749 //\r
750 //USB_ULPI_0_DATA6\r
751 //\r
752 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x328, (UINT32)~(0x7), (UINT32) (GPI));\r
753 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x320, (UINT32)~(0x187), (UINT32) (0x101));\r
754\r
755 //\r
756 //USB_ULPI_0_DATA7\r
757 //\r
758 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a8, (UINT32)~(0x7), (UINT32) (GPI));\r
759 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a0, (UINT32)~(0x187), (UINT32) (0x101));\r
760\r
761 //\r
762 //USB_ULPI_0_DIR\r
763 //\r
764 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x348, (UINT32)~(0x7), (UINT32) (GPI));\r
765 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x340, (UINT32)~(0x187), (UINT32) (0x81));\r
766\r
767 //\r
768 //USB_ULPI_0_NXT\r
769 //\r
770 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x358, (UINT32)~(0x7), (UINT32) (GPI));\r
771 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x350, (UINT32)~(0x187), (UINT32) (0x101));\r
772\r
773 //\r
774 //USB_ULPI_0_STP\r
775 //\r
776 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b8, (UINT32)~(0x7), (UINT32) (GPI));\r
777 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b0, (UINT32)~(0x187), (UINT32) (0x81));\r
778\r
779 //\r
780 //USB_ULPI_0_REFCLK\r
781 //\r
782 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x288, (UINT32)~(0x7), (UINT32) (GPI));\r
783 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x280, (UINT32)~(0x187), (UINT32) (0x101));\r
784\r
785 return EFI_SUCCESS;\r
786}\r
787\r
788EFI_STATUS\r
789DisableRTD3 (\r
790 VOID)\r
791{\r
792 //\r
793 //Disable RTD3\r
794 //\r
795 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x210, (UINT32)~(0x0f000007), (UINT32) (0x00));\r
796 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x1e0, (UINT32)~(0x0f000007), (UINT32) (0x00));\r
797\r
798 return EFI_SUCCESS;\r
799}\r
800\r
801/**\r
802 Platform specific initializations in stage1.\r
803\r
804 @param FfsHeader Pointer to the PEIM FFS file header.\r
805 @param PeiServices General purpose services available to every PEIM.\r
806\r
807 @retval EFI_SUCCESS Operation completed successfully.\r
808 @retval Otherwise Platform initialization failed.\r
809**/\r
810EFI_STATUS\r
811EFIAPI\r
812PlatformEarlyInitEntry (\r
813\r
814 IN EFI_PEI_FILE_HANDLE FileHandle,\r
815 IN CONST EFI_PEI_SERVICES **PeiServices\r
816 )\r
817{\r
818 EFI_STATUS Status;\r
819 SYSTEM_CONFIGURATION SystemConfiguration;\r
820 EFI_PLATFORM_INFO_HOB *PlatformInfo;\r
821 EFI_PEI_HOB_POINTERS Hob;\r
822 EFI_PLATFORM_CPU_INFO PlatformCpuInfo;\r
890f11d4 823 EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBlock;\r
c497dcc8
MK		 824 EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *NewDescriptorBlock;\r
825 UINTN Index;\r
826 UINTN MaxIndex;\r
827 UINT64 Base;\r
890f11d4 828 UINT64 Size;\r
c497dcc8 829 UINT64 NewSize;\r
890f11d4
MK		 830\r
831 //\r
c497dcc8 832 // Make sure base and size of the SMRAM region is aligned\r
890f11d4
MK		 833 //\r
834 Hob.Raw = GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid);\r
835 if (Hob.Raw != NULL) {\r
836 DescriptorBlock = GET_GUID_HOB_DATA (Hob.Raw);\r
c497dcc8
MK		 837 DEBUG ((DEBUG_INFO, "SMM PEI SMRAM Memory Reserved HOB\n"));\r
838 for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {\r
839 DEBUG((DEBUG_INFO, " SMRAM Descriptor[%02x]: Start=%016lx Size=%016lx State=%02x\n",\r
840 Index,\r
841 DescriptorBlock->Descriptor[Index].PhysicalStart,\r
842 DescriptorBlock->Descriptor[Index].PhysicalSize,\r
843 DescriptorBlock->Descriptor[Index].RegionState\r
844 ));\r
845 }\r
846\r
847 //\r
848 // Find the largest usable range of SMRAM between 1MB and 4GB\r
849 //\r
850 for (Index = 0, MaxIndex = 0, Size = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {\r
851 //\r
852 // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization\r
853 //\r
854 if ((DescriptorBlock->Descriptor[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {\r
855 continue;\r
856 }\r
857 //\r
858 // Skip any SMRAM region below 1MB\r
859 //\r
860 if (DescriptorBlock->Descriptor[Index].CpuStart < BASE_1MB) {\r
861 continue;\r
862 }\r
863 //\r
864 // Skip any SMRAM region that is above 4GB or crosses the 4GB boundary\r
865 //\r
866 if ((DescriptorBlock->Descriptor[Index].CpuStart + DescriptorBlock->Descriptor[Index].PhysicalSize) >= BASE_4GB) {\r
867 continue;\r
868 }\r
869 //\r
870 // Cache the largest SMRAM region index\r
871 //\r
872 if (DescriptorBlock->Descriptor[Index].PhysicalSize >= DescriptorBlock->Descriptor[MaxIndex].PhysicalSize) {\r
873 MaxIndex = Index;\r
874 }\r
875 }\r
876\r
877 //\r
878 // Find the extent of the contiguous SMRAM region that surrounds the largest usable SMRAM range\r
879 //\r
880 Base = DescriptorBlock->Descriptor[MaxIndex].CpuStart;\r
881 Size = DescriptorBlock->Descriptor[MaxIndex].PhysicalSize;\r
882 for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {\r
883 if (DescriptorBlock->Descriptor[Index].CpuStart < Base &&\r
884 Base == (DescriptorBlock->Descriptor[Index].CpuStart + DescriptorBlock->Descriptor[Index].PhysicalSize)) {\r
885 Base = DescriptorBlock->Descriptor[Index].CpuStart;\r
886 Size += DescriptorBlock->Descriptor[Index].PhysicalSize;\r
887 } else if ((Base + Size) == DescriptorBlock->Descriptor[Index].CpuStart) {\r
888 Size += DescriptorBlock->Descriptor[Index].PhysicalSize;\r
889 }\r
890 }\r
891\r
892 //\r
893 // Round SMRAM region up to nearest power of 2 that is at least 4KB\r
894 //\r
895 NewSize = MAX (LShiftU64 (1, HighBitSet64 (Size - 1) + 1), SIZE_4KB);\r
896 if ((Base & ~(NewSize - 1)) != Base) {\r
897 //\r
898 // SMRAM region Base Address has smaller alignment than SMRAM region Size\r
899 // This is not compatible with SMRR settings\r
900 //\r
901 DEBUG((DEBUG_ERROR, "ERROR: SMRAM Region Size has larger alignment than SMRAM Region Base\n"));\r
902 DEBUG((DEBUG_ERROR, " SMRAM Region Base=%016lx Size=%016lx\n", Base, NewSize));\r
903 ASSERT (FALSE);\r
904 } else if (Size != NewSize) {\r
905 //\r
906 // See if the size difference can be added to an adjacent descriptor that is already allocated\r
907 //\r
908 for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {\r
909 if ((DescriptorBlock->Descriptor[Index].CpuStart + DescriptorBlock->Descriptor[Index].PhysicalSize) == (Base + Size)) {\r
910 if (((DescriptorBlock->Descriptor[Index].RegionState) & EFI_ALLOCATED) != 0) {\r
911 DescriptorBlock->Descriptor[Index].PhysicalSize += (NewSize - Size);\r
912 Size = NewSize;\r
913 break;\r
914 }\r
915 }\r
916 }\r
917\r
918 if (Size != NewSize) {\r
919 //\r
920 // Add an allocated descriptor to the SMM PEI SMRAM Memory Reserved HOB to accomodate the larger size.\r
921 //\r
922 Index = DescriptorBlock->NumberOfSmmReservedRegions;\r
923 NewDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *)BuildGuidHob (\r
924 &gEfiSmmPeiSmramMemoryReserveGuid,\r
925 sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK) + ((Index + 1) * sizeof (EFI_SMRAM_DESCRIPTOR))\r
926 );\r
927 ASSERT (NewDescriptorBlock != NULL);\r
928\r
929 //\r
930 // Copy old EFI_SMRAM_HOB_DESCRIPTOR_BLOCK to new allocated region\r
931 //\r
932 CopyMem (\r
933 NewDescriptorBlock,\r
934 DescriptorBlock,\r
935 sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK) + (Index * sizeof (EFI_SMRAM_DESCRIPTOR))\r
936 );\r
937\r
938 //\r
939 // Make sure last descriptor in NewDescriptorBlock contains last descriptor from DescriptorBlock\r
940 //\r
941 CopyMem (\r
942 &NewDescriptorBlock->Descriptor[Index],\r
943 &NewDescriptorBlock->Descriptor[Index - 1],\r
944 sizeof (EFI_SMRAM_DESCRIPTOR)\r
945 );\r
946\r
947 //\r
948 // Fill next to last descriptor with an allocated descriptor that aligns the total size of SMRAM\r
949 //\r
950 NewDescriptorBlock->Descriptor[Index - 1].CpuStart = Base + Size;\r
951 NewDescriptorBlock->Descriptor[Index - 1].PhysicalStart = Base + Size;\r
952 NewDescriptorBlock->Descriptor[Index - 1].PhysicalSize = NewSize - Size;\r
953 NewDescriptorBlock->Descriptor[Index - 1].RegionState = DescriptorBlock->Descriptor[MaxIndex].RegionState | EFI_ALLOCATED;\r
954 NewDescriptorBlock->NumberOfSmmReservedRegions++;\r
955\r
956 //\r
957 // Invalidate the original gEfiSmmPeiSmramMemoryReserveGuid HOB\r
958 //\r
959 ZeroMem (&Hob.Guid->Name, sizeof (&Hob.Guid->Name));\r
960 }\r
961\r
962 Hob.Raw = GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid);\r
963 DescriptorBlock = GET_GUID_HOB_DATA (Hob.Raw);\r
964 DEBUG ((DEBUG_INFO, "SMM PEI SMRAM Memory Reserved HOB - Updated\n"));\r
965 for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {\r
966 DEBUG((DEBUG_INFO, " SMRAM Descriptor[%02x]: Start=%016lx Size=%016lx State=%02x\n",\r
967 Index,\r
968 DescriptorBlock->Descriptor[Index].PhysicalStart,\r
969 DescriptorBlock->Descriptor[Index].PhysicalSize,\r
970 DescriptorBlock->Descriptor[Index].RegionState\r
971 ));\r
972 }\r
973 }\r
890f11d4 974 }\r
3cbfba02
DW		 975\r
976 //\r
977 // Initialize SmbusPolicy PPI\r
978 //\r
979 Status = (*PeiServices)->InstallPpi(PeiServices, &mInstallSmbusPolicyPpi);\r
980 ASSERT_EFI_ERROR (Status);\r
981\r
982 //\r
983 // Initialize Stall PPIs\r
984 //\r
985 Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi);\r
986 ASSERT_EFI_ERROR (Status);\r
987\r
988 //\r
989 // Initialize platform PPIs\r
990 //\r
991 Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallSpeakerInterfacePpi);\r
992 ASSERT_EFI_ERROR (Status);\r
993\r
994 //\r
995 // Variable initialization\r
996 //\r
997 ZeroMem(&PlatformCpuInfo, sizeof(EFI_PLATFORM_CPU_INFO));\r
998\r
999 //\r
1000 // Set the some PCI and chipset range as UC\r
1001 // And align to 1M at leaset\r
1002 //\r
1003 Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r
1004 ASSERT (Hob.Raw != NULL);\r
1005 PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);\r
1006\r
1007 //\r
1008 // Initialize PlatformInfo HOB\r
1009 //\r
1010 MultiPlatformInfoInit(PeiServices, PlatformInfo);\r
1011\r
1012 //\r
1013 // Do basic MCH init\r
1014 //\r
1015 MchInit (PeiServices);\r
1016\r
1017 //\r
1018 // Set the new boot mode\r
1019 //\r
1020 Status = UpdateBootMode (PeiServices, PlatformInfo);\r
1021 ASSERT_EFI_ERROR (Status);\r
1022\r
1023 SetPlatformBootMode (PeiServices, PlatformInfo);\r
1024\r
1025 //\r
1026 // Get setup variable. This can only be done after BootMode is updated\r
1027 //\r
1028 GetSetupVariable (PeiServices, &SystemConfiguration);\r
1029\r
1030 CheckOsSelection(PeiServices, &SystemConfiguration);\r
1031\r
1032 //\r
1033 // Update PlatformInfo HOB according to setup variable\r
1034 //\r
1035 PlatformInfoUpdate(PeiServices, PlatformInfo, &SystemConfiguration);\r
1036\r
1037 InitializePlatform (PeiServices, PlatformInfo, &SystemConfiguration);\r
1038\r
1039 //\r
1040 // Initialize VlvPolicy PPI\r
1041 //\r
1042 Status = VlvPolicyInit (PeiServices, &SystemConfiguration);\r
1043 ASSERT_EFI_ERROR (Status);\r
1044\r
1045 //\r
1046 // Soc specific GPIO setting\r
1047 //\r
1048 ConfigureSoCGpio(&SystemConfiguration);\r
1049\r
1050 //\r
1051 // Baylake Board specific.\r
1052 //\r
1053 if (PlatformInfo->BoardId == BOARD_ID_BL_RVP ||\r
1054 PlatformInfo->BoardId == BOARD_ID_BL_FFRD ||\r
1055 PlatformInfo->BoardId == BOARD_ID_BL_FFRD8 ||\r
1056 PlatformInfo->BoardId == BOARD_ID_BL_RVP_DDR3L ||\r
1057 PlatformInfo->BoardId == BOARD_ID_BL_STHI ||\r
1058 PlatformInfo->BoardId == BOARD_ID_BB_RVP ||\r
1059 PlatformInfo->BoardId == BOARD_ID_BS_RVP ||\r
1060 PlatformInfo->BoardId == BOARD_ID_MINNOW2 ||\r
8b7a63e7 1061 PlatformInfo->BoardId == BOARD_ID_MINNOW2_TURBOT||\r
3cbfba02
DW		 1062 PlatformInfo->BoardId == BOARD_ID_CVH) {\r
1063 ConfigureLpssAndSccGpio(&SystemConfiguration, PlatformInfo);\r
1064\r
1065 }\r
1066\r
1067\r
1068 //\r
1069 // Configure LPE\r
1070 // Alpine Valley and Bayley Bay board specific\r
1071 //\r
1072 ConfigureLpeGpio(&SystemConfiguration);\r
1073\r
1074 //\r
1075 // Bayley Bay Board specific.\r
1076 //\r
1077 ConfigureSciSmiGpioRout(PlatformInfo);\r
1078 if (SystemConfiguration.LpssI2C3Enabled == 1) {\r
1079 ConfigureMipiCsi();\r
1080 }\r
1081\r
1082\r
1083 //\r
1084 // Do basic CPU init\r
1085 //\r
1086 Status = PlatformCpuInit (PeiServices, &SystemConfiguration, &PlatformCpuInfo);\r
1087\r
1088 //\r
1089 // Perform basic SSA related platform initialization\r
1090 //\r
1091 PlatformSsaInit (&SystemConfiguration,PeiServices);\r
1092\r
1093\r
1094 //\r
1095 // Do basic PCH init\r
1096 //\r
1097 Status = PlatformPchInit (&SystemConfiguration, PeiServices, PlatformInfo->PlatformType);\r
1098 ASSERT_EFI_ERROR (Status);\r
1099\r
1100 //\r
1101 // Initialize platform PPIs\r
1102 //\r
1103 Status = (*PeiServices)->InstallPpi (PeiServices, &mPpiList[0]);\r
1104 ASSERT_EFI_ERROR (Status);\r
1105\r
1106 if (PlatformInfo->BoardId != BOARD_ID_CVH) {\r
1107 InstallPlatformClocksNotify (PeiServices);\r
1108 InstallPlatformSysCtrlGPIONotify(PeiServices);\r
1109 }\r
1110\r
1111 //\r
1112 // Initialize platform PPIs\r
1113 //\r
1114 Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);\r
1115 ASSERT_EFI_ERROR (Status);\r
1116\r
1117 //\r
1118 // Initialize Measured Boot\r
1119 //\r
1120 Status = MeasuredBootInit (PeiServices, &SystemConfiguration);\r
1121 ASSERT_EFI_ERROR (Status);\r
1122\r
1123 return Status;\r
1124}\r
1125\r
1126/**\r
1127\r
1128 Return the mainblockcompact Fv.\r
1129\r
1130 @param FvNumber Our enumeration of the firmware volumes we care about.\r
1131\r
1132 @param FvAddress Base Address of the memory containing the firmware volume\r
1133\r
1134 @retval EFI_SUCCESS\r
1135 @retval EFI_NOT_FOUND\r
1136\r
1137**/\r
1138EFI_STATUS\r
1139EFIAPI\r
1140FindFv (\r
1141 IN EFI_PEI_FIND_FV_PPI *This,\r
1142 IN CONST EFI_PEI_SERVICES **PeiServices,\r
1143 IN OUT UINT8 *FvNumber,\r
1144 OUT EFI_FIRMWARE_VOLUME_HEADER **FVAddress\r
1145 )\r
1146{\r
1147 //\r
1148 // At present, we only have one Fv to search\r
1149 //\r
1150 if (*FvNumber == 0) {\r
1151 *FvNumber = 1;\r
1152 *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FixedPcdGet32 (PcdFlashFvMainBase);\r
1153 return EFI_SUCCESS;\r
1154 }\r
1155 else if (*FvNumber == 1) {\r
1156 *FvNumber = 2;\r
1157 *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FixedPcdGet32 (PcdFlashFvRecovery2Base);\r
1158 return EFI_SUCCESS;\r
1159 }\r
1160 else { // Not the one Fv we care about\r
1161 return EFI_NOT_FOUND;\r
1162 }\r
1163}\r
1164\r
1165EFI_STATUS\r
1166EFIAPI\r
1167CpuOnlyReset (\r
1168 IN CONST EFI_PEI_SERVICES **PeiServices\r
1169 )\r
1170{\r
1171// MsgBus32Write(CDV_UNIT_PUNIT, PUNIT_CPU_RST, 0x01)\r
1172#ifdef __GNUC__\r
1173 __asm__\r
1174 (\r
1175 "xorl %ecx, %ecx\n"\r
1176 "1:hlt; hlt; hlt\n"\r
1177 "jmp 1b\n"\r
1178 );\r
1179#else\r
1180 _asm {\r
1181 xor ecx, ecx\r
1182 HltLoop:\r
1183 hlt\r
1184 hlt\r
1185 hlt\r
1186 loop HltLoop\r
1187 }\r
1188#endif\r
1189 //\r
1190 // If we get here we need to mark it as a failure.\r
1191 //\r
1192 return EFI_UNSUPPORTED;\r
1193}\r
1194\r
1195\r
1196#ifdef __GNUC__\r
1197#pragma GCC pop_options\r
1198#else\r
1199#pragma optimize ("", on)\r
1200#endif\r
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