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3cbfba02 DW |
1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
4 | \r\r | |
9dc8036d MK |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
6 | \r | |
3cbfba02 DW |
7 | \r\r |
8 | \r | |
9 | Module Name:\r | |
10 | \r | |
11 | \r | |
12 | PlatformSsaInitPeim.c\r | |
13 | \r | |
14 | Abstract:\r | |
15 | \r | |
16 | \r | |
17 | --*/\r | |
18 | \r | |
19 | #include "PlatformEarlyInit.h"\r | |
20 | \r | |
21 | /**\r | |
22 | Perform SSA related platform initialization.\r | |
23 | \r | |
24 | **/\r | |
25 | VOID\r | |
26 | PlatformSsaInit (\r | |
27 | IN SYSTEM_CONFIGURATION *SystemConfiguration,\r | |
28 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
29 | )\r | |
30 | {\r | |
31 | \r | |
32 | DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - Start\n"));\r | |
33 | DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - SystemConfiguration->ISPDevSel 0x%x\n",SystemConfiguration->ISPDevSel));\r | |
34 | if(SystemConfiguration->ISPDevSel == 0x02)\r | |
35 | {\r | |
36 | //\r | |
37 | // Device 3 Interrupt Route\r | |
38 | //\r | |
39 | MmioWrite16 (\r | |
40 | (ILB_BASE_ADDRESS + R_PCH_ILB_D3IR),\r | |
41 | V_PCH_ILB_DXXIR_IAR_PIRQH // For IUNIT\r | |
42 | );\r | |
43 | MmioRead16(ILB_BASE_ADDRESS + R_PCH_ILB_D3IR); // Read Posted Writes Register\r | |
44 | DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - Device 3 Interrupt Route Done\n"));\r | |
45 | }\r | |
46 | \r | |
47 | //\r | |
48 | // Device 2 Interrupt Route\r | |
49 | //\r | |
50 | MmioWrite16 (\r | |
51 | (ILB_BASE_ADDRESS + R_PCH_ILB_D2IR),\r | |
52 | V_PCH_ILB_DXXIR_IAR_PIRQA // For IGD\r | |
53 | );\r | |
54 | MmioRead16(ILB_BASE_ADDRESS + R_PCH_ILB_D2IR); // Read Posted Writes Register\r | |
55 | DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - Device 2 Interrupt Route Done\n"));\r | |
56 | \r | |
57 | return;\r | |
58 | }\r |