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[mirror_edk2.git] / Vlv2TbltDevicePkg / SmBiosMiscDxe / MiscProcessorCacheFunction.c

/*++\r
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Copyright (c) 2006  - 2014, Intel Corporation. All rights reserved.<BR>\r
                                                                                   \r\r
  This program and the accompanying materials are licensed and made available under\r\r
  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
  The full text of the license may be found at                                     \r\r
  http://opensource.org/licenses/bsd-license.php.                                  \r\r
                                                                                   \r\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
                                                                                   \r\r
\r
\r
Module Name:\r
\r
  MiscProcessorCacheFunction.c\r
\r
Abstract:\r
\r
  BIOS processor cache details.\r
  Misc. subclass type 7.\r
  SMBIOS type 7.\r
\r
--*/\r
#include "CommonHeader.h"\r
#include "MiscSubclassDriver.h"\r
#include <Protocol/DataHub.h>\r
#include <Guid/DataHubRecords.h>\r
\r
\r
extern  SMBIOS_TABLE_TYPE7            *SmbiosRecordL1;\r
extern  SMBIOS_TABLE_TYPE7            *SmbiosRecordL2;\r
extern  SMBIOS_TABLE_TYPE7            *SmbiosRecordL3;\r
\r
\r
UINT32\r
ConvertBase2ToRaw (\r
  IN  EFI_EXP_BASE2_DATA             *Data)\r
{\r
  UINTN         Index;\r
  UINT32        RawData;\r
\r
  RawData = Data->Value;\r
  for (Index = 0; Index < (UINTN) Data->Exponent; Index++) {\r
     RawData <<= 1;\r
  }\r
\r
  return  RawData;\r
}\r
\r
\r
MISC_SMBIOS_TABLE_FUNCTION(MiscProcessorCache)\r
{\r
	EFI_SMBIOS_HANDLE     SmbiosHandle;\r
	SMBIOS_TABLE_TYPE7            *SmbiosRecordL1;\r
	SMBIOS_TABLE_TYPE7            *SmbiosRecordL2;\r
\r
	EFI_CACHE_SRAM_TYPE_DATA      CacheSramType;\r
	CHAR16                          *SocketDesignation;\r
	CHAR8                           *OptionalStrStart;\r
	UINTN                           SocketStrLen;\r
	STRING_REF                      TokenToGet;\r
	EFI_DATA_HUB_PROTOCOL           *DataHub;\r
	UINT64                          MonotonicCount;\r
	EFI_DATA_RECORD_HEADER          *Record;\r
	EFI_SUBCLASS_TYPE1_HEADER       *DataHeader;\r
	UINT8                           *SrcData;\r
	EFI_STATUS                      Status;\r
\r
	//\r
	// Memory Device LOcator\r
	//\r
	DEBUG ((EFI_D_ERROR, "type 7\n"));\r
\r
	TokenToGet = STRING_TOKEN (STR_SOCKET_DESIGNATION);\r
	SocketDesignation = SmbiosMiscGetString (TokenToGet);\r
	SocketStrLen = StrLen(SocketDesignation);\r
	if (SocketStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
	return EFI_UNSUPPORTED;\r
	}\r
\r
	SmbiosRecordL1 = AllocatePool(sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);\r
	ASSERT (SmbiosRecordL1 != NULL);\r
	ZeroMem(SmbiosRecordL1, sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);\r
\r
	SmbiosRecordL2 = AllocatePool(sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);\r
	ASSERT (SmbiosRecordL2 != NULL);\r
	ZeroMem(SmbiosRecordL2, sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);\r
\r
	//\r
	// Get the Data Hub Protocol. Assume only one instance\r
	//\r
	Status = gBS->LocateProtocol (\r
	                &gEfiDataHubProtocolGuid,\r
	                NULL,\r
	                (VOID **)&DataHub\r
	                );\r
	ASSERT_EFI_ERROR(Status);\r
\r
	MonotonicCount = 0;\r
	Record = NULL;\r
\r
	do {\r
	Status = DataHub->GetNextRecord (\r
	                    DataHub,\r
	                    &MonotonicCount,\r
	                    NULL,\r
	                    &Record\r
	                    );\r
		if (!EFI_ERROR(Status)) {\r
			if (Record->DataRecordClass == EFI_DATA_RECORD_CLASS_DATA) {\r
				DataHeader  = (EFI_SUBCLASS_TYPE1_HEADER *)(Record + 1);\r
				SrcData     = (UINT8  *)(DataHeader + 1);\r
				if (CompareGuid(&Record->DataRecordGuid, &gEfiCacheSubClassGuid) && (DataHeader->RecordType == CacheSizeRecordType)) {\r
          			if (DataHeader->SubInstance == EFI_CACHE_L1) {\r
						SmbiosRecordL1->InstalledSize += (UINT16) (ConvertBase2ToRaw((EFI_EXP_BASE2_DATA *)SrcData) >> 10);\r
						SmbiosRecordL1->MaximumCacheSize = SmbiosRecordL1->InstalledSize;\r
          			}\r
         			 else if (DataHeader->SubInstance == EFI_CACHE_L2) {\r
						SmbiosRecordL2->InstalledSize += (UINT16) (ConvertBase2ToRaw((EFI_EXP_BASE2_DATA *)SrcData) >> 10);\r
						SmbiosRecordL2->MaximumCacheSize = SmbiosRecordL2->InstalledSize;\r
          			} else {\r
           				 continue;\r
          			}\r
		  		}\r
	      	}\r
    	}\r
	} while (!EFI_ERROR(Status) && (MonotonicCount != 0));\r
\r
	//\r
	//Filling SMBIOS type 7 information for different cache levels.\r
	//\r
\r
	SmbiosRecordL1->Hdr.Type = EFI_SMBIOS_TYPE_CACHE_INFORMATION;\r
	SmbiosRecordL1->Hdr.Length = (UINT8) sizeof (SMBIOS_TABLE_TYPE7);\r
	SmbiosRecordL1->Hdr.Handle = 0;\r
\r
	SmbiosRecordL1->Associativity = CacheAssociativity8Way;\r
	SmbiosRecordL1->SystemCacheType = CacheTypeUnknown;\r
	SmbiosRecordL1->SocketDesignation = 0x01;\r
	SmbiosRecordL1->CacheSpeed = 0;\r
	SmbiosRecordL1->CacheConfiguration = 0x0180;\r
	ZeroMem (&CacheSramType, sizeof (EFI_CACHE_SRAM_TYPE_DATA));\r
	CacheSramType.Synchronous = 1;\r
	CopyMem(&SmbiosRecordL1->SupportedSRAMType, &CacheSramType, 2);\r
	CopyMem(&SmbiosRecordL1->CurrentSRAMType, &CacheSramType, 2);\r
	SmbiosRecordL1->ErrorCorrectionType = EfiCacheErrorSingleBit;\r
\r
\r
	SmbiosRecordL2->Hdr.Type = EFI_SMBIOS_TYPE_CACHE_INFORMATION;\r
	SmbiosRecordL2->Hdr.Length = (UINT8) sizeof (SMBIOS_TABLE_TYPE7);\r
	SmbiosRecordL2->Hdr.Handle = 0;\r
\r
	SmbiosRecordL2->Associativity = CacheAssociativity16Way;\r
	SmbiosRecordL2->SystemCacheType = CacheTypeInstruction;\r
	SmbiosRecordL2->SocketDesignation = 0x01;\r
	SmbiosRecordL2->CacheSpeed = 0;\r
	SmbiosRecordL2->CacheConfiguration = 0x0281;\r
	ZeroMem (&CacheSramType, sizeof (EFI_CACHE_SRAM_TYPE_DATA));\r
	CacheSramType.Synchronous = 1;\r
	CopyMem(&SmbiosRecordL2->SupportedSRAMType, &CacheSramType, 2);\r
	CopyMem(&SmbiosRecordL2->CurrentSRAMType, &CacheSramType, 2);\r
	SmbiosRecordL2->ErrorCorrectionType = EfiCacheErrorSingleBit;\r
\r
\r
\r
	//\r
	//Adding SMBIOS type 7 records to SMBIOS table.\r
	//\r
	SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
	OptionalStrStart = (CHAR8 *)(SmbiosRecordL1 + 1);\r
	UnicodeStrToAsciiStr(SocketDesignation, OptionalStrStart);\r
\r
	Smbios-> Add(\r
	           Smbios,\r
	           NULL,\r
	           &SmbiosHandle,\r
	           (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecordL1\r
	           );\r
\r
	//\r
	//VLV2 incorporates two SLM modules (quad cores) in the SoC. 2 cores share BIU/L2 cache\r
	//\r
	SmbiosRecordL2->InstalledSize = (SmbiosRecordL2->InstalledSize)/2;\r
	SmbiosRecordL2->MaximumCacheSize = SmbiosRecordL2->InstalledSize;\r
	SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
\r
	OptionalStrStart = (CHAR8 *)(SmbiosRecordL2 + 1);\r
	UnicodeStrToAsciiStr(SocketDesignation, OptionalStrStart);\r
\r
	Smbios-> Add(\r
	           Smbios,\r
	           NULL,\r
	           &SmbiosHandle,\r
	           (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecordL2\r
	           );\r
\r
	return EFI_SUCCESS;\r
}\r