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1 | /** @file\r | |
2 | \r | |
3 | Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r | |
4 | \r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include <Base.h>\r | |
16 | #include <Library/ArmLib.h>\r | |
17 | #include <Library/ArmCpuLib.h>\r | |
18 | #include <Library/ArmPlatformLib.h>\r | |
19 | #include <Library/IoLib.h>\r | |
20 | #include <Library/PcdLib.h>\r | |
21 | \r | |
22 | #include <Chipset/ArmCortexA9.h>\r | |
23 | \r | |
24 | VOID\r | |
25 | ArmEnableScu (\r | |
26 | VOID\r | |
27 | )\r | |
28 | {\r | |
29 | INTN ScuBase;\r | |
30 | \r | |
31 | ScuBase = ArmGetScuBaseAddress();\r | |
32 | \r | |
33 | // Invalidate all: write -1 to SCU Invalidate All register\r | |
34 | MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);\r | |
35 | // Enable SCU\r | |
36 | MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);\r | |
37 | }\r | |
38 | \r | |
39 | VOID\r | |
40 | ArmCpuSetup (\r | |
41 | IN UINTN MpId\r | |
42 | )\r | |
43 | {\r | |
44 | // Enable SWP instructions\r | |
45 | ArmEnableSWPInstruction ();\r | |
46 | \r | |
47 | // Enable program flow prediction, if supported.\r | |
48 | ArmEnableBranchPrediction ();\r | |
49 | \r | |
50 | // If MPCore then Enable the SCU\r | |
51 | if (ArmIsMpCore()) {\r | |
52 | // Signals the Cortex-A9 processor is taking part in coherency\r | |
53 | ArmSetAuxCrBit (A9_FEATURE_SMP);\r | |
54 | \r | |
55 | ArmEnableScu ();\r | |
56 | }\r | |
57 | }\r | |
58 | \r | |
59 | \r | |
60 | VOID\r | |
61 | ArmCpuSetupSmpNonSecure (\r | |
62 | IN UINTN MpId\r | |
63 | )\r | |
64 | {\r | |
65 | INTN ScuBase;\r | |
66 | \r | |
67 | // Make the SCU accessible in Non Secure world\r | |
68 | if (ArmPlatformIsPrimaryCore (MpId)) {\r | |
69 | ScuBase = ArmGetScuBaseAddress();\r | |
70 | \r | |
71 | // Allow NS access to SCU register\r | |
72 | MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);\r | |
73 | // Allow NS access to Private Peripherals\r | |
74 | MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);\r | |
75 | }\r | |
76 | }\r |