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1 | /** @file\r | |
2 | *\r | |
3 | * Copyright (c) 2011-2018, ARM Limited. All rights reserved.\r | |
4 | *\r | |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #include <Library/ArmGicLib.h>\r | |
16 | \r | |
17 | #include "ArmGicDxe.h"\r | |
18 | \r | |
19 | #define ARM_GIC_DEFAULT_PRIORITY 0x80\r | |
20 | \r | |
21 | extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;\r | |
22 | extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol;\r | |
23 | \r | |
24 | STATIC UINTN mGicDistributorBase;\r | |
25 | STATIC UINTN mGicRedistributorsBase;\r | |
26 | \r | |
27 | /**\r | |
28 | Enable interrupt source Source.\r | |
29 | \r | |
30 | @param This Instance pointer for this protocol\r | |
31 | @param Source Hardware source of the interrupt\r | |
32 | \r | |
33 | @retval EFI_SUCCESS Source interrupt enabled.\r | |
34 | @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r | |
35 | \r | |
36 | **/\r | |
37 | STATIC\r | |
38 | EFI_STATUS\r | |
39 | EFIAPI\r | |
40 | GicV3EnableInterruptSource (\r | |
41 | IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r | |
42 | IN HARDWARE_INTERRUPT_SOURCE Source\r | |
43 | )\r | |
44 | {\r | |
45 | if (Source >= mGicNumInterrupts) {\r | |
46 | ASSERT(FALSE);\r | |
47 | return EFI_UNSUPPORTED;\r | |
48 | }\r | |
49 | \r | |
50 | ArmGicEnableInterrupt (mGicDistributorBase, mGicRedistributorsBase, Source);\r | |
51 | \r | |
52 | return EFI_SUCCESS;\r | |
53 | }\r | |
54 | \r | |
55 | /**\r | |
56 | Disable interrupt source Source.\r | |
57 | \r | |
58 | @param This Instance pointer for this protocol\r | |
59 | @param Source Hardware source of the interrupt\r | |
60 | \r | |
61 | @retval EFI_SUCCESS Source interrupt disabled.\r | |
62 | @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r | |
63 | \r | |
64 | **/\r | |
65 | STATIC\r | |
66 | EFI_STATUS\r | |
67 | EFIAPI\r | |
68 | GicV3DisableInterruptSource (\r | |
69 | IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r | |
70 | IN HARDWARE_INTERRUPT_SOURCE Source\r | |
71 | )\r | |
72 | {\r | |
73 | if (Source >= mGicNumInterrupts) {\r | |
74 | ASSERT(FALSE);\r | |
75 | return EFI_UNSUPPORTED;\r | |
76 | }\r | |
77 | \r | |
78 | ArmGicDisableInterrupt (mGicDistributorBase, mGicRedistributorsBase, Source);\r | |
79 | \r | |
80 | return EFI_SUCCESS;\r | |
81 | }\r | |
82 | \r | |
83 | /**\r | |
84 | Return current state of interrupt source Source.\r | |
85 | \r | |
86 | @param This Instance pointer for this protocol\r | |
87 | @param Source Hardware source of the interrupt\r | |
88 | @param InterruptState TRUE: source enabled, FALSE: source disabled.\r | |
89 | \r | |
90 | @retval EFI_SUCCESS InterruptState is valid\r | |
91 | @retval EFI_DEVICE_ERROR InterruptState is not valid\r | |
92 | \r | |
93 | **/\r | |
94 | STATIC\r | |
95 | EFI_STATUS\r | |
96 | EFIAPI\r | |
97 | GicV3GetInterruptSourceState (\r | |
98 | IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r | |
99 | IN HARDWARE_INTERRUPT_SOURCE Source,\r | |
100 | IN BOOLEAN *InterruptState\r | |
101 | )\r | |
102 | {\r | |
103 | if (Source >= mGicNumInterrupts) {\r | |
104 | ASSERT(FALSE);\r | |
105 | return EFI_UNSUPPORTED;\r | |
106 | }\r | |
107 | \r | |
108 | *InterruptState = ArmGicIsInterruptEnabled (\r | |
109 | mGicDistributorBase,\r | |
110 | mGicRedistributorsBase,\r | |
111 | Source\r | |
112 | );\r | |
113 | \r | |
114 | return EFI_SUCCESS;\r | |
115 | }\r | |
116 | \r | |
117 | /**\r | |
118 | Signal to the hardware that the End Of Interrupt state\r | |
119 | has been reached.\r | |
120 | \r | |
121 | @param This Instance pointer for this protocol\r | |
122 | @param Source Hardware source of the interrupt\r | |
123 | \r | |
124 | @retval EFI_SUCCESS Source interrupt EOI'ed.\r | |
125 | @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r | |
126 | \r | |
127 | **/\r | |
128 | STATIC\r | |
129 | EFI_STATUS\r | |
130 | EFIAPI\r | |
131 | GicV3EndOfInterrupt (\r | |
132 | IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r | |
133 | IN HARDWARE_INTERRUPT_SOURCE Source\r | |
134 | )\r | |
135 | {\r | |
136 | if (Source >= mGicNumInterrupts) {\r | |
137 | ASSERT(FALSE);\r | |
138 | return EFI_UNSUPPORTED;\r | |
139 | }\r | |
140 | \r | |
141 | ArmGicV3EndOfInterrupt (Source);\r | |
142 | return EFI_SUCCESS;\r | |
143 | }\r | |
144 | \r | |
145 | /**\r | |
146 | EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r | |
147 | \r | |
148 | @param InterruptType Defines the type of interrupt or exception that\r | |
149 | occurred on the processor. This parameter is\r | |
150 | processor architecture specific.\r | |
151 | @param SystemContext A pointer to the processor context when\r | |
152 | the interrupt occurred on the processor.\r | |
153 | \r | |
154 | @return None\r | |
155 | \r | |
156 | **/\r | |
157 | STATIC\r | |
158 | VOID\r | |
159 | EFIAPI\r | |
160 | GicV3IrqInterruptHandler (\r | |
161 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
162 | IN EFI_SYSTEM_CONTEXT SystemContext\r | |
163 | )\r | |
164 | {\r | |
165 | UINT32 GicInterrupt;\r | |
166 | HARDWARE_INTERRUPT_HANDLER InterruptHandler;\r | |
167 | \r | |
168 | GicInterrupt = ArmGicV3AcknowledgeInterrupt ();\r | |
169 | \r | |
170 | // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the\r | |
171 | // number of interrupt (ie: Spurious interrupt).\r | |
172 | if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {\r | |
173 | // The special interrupt do not need to be acknowledge\r | |
174 | return;\r | |
175 | }\r | |
176 | \r | |
177 | InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];\r | |
178 | if (InterruptHandler != NULL) {\r | |
179 | // Call the registered interrupt handler.\r | |
180 | InterruptHandler (GicInterrupt, SystemContext);\r | |
181 | } else {\r | |
182 | DEBUG ((DEBUG_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));\r | |
183 | GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, GicInterrupt);\r | |
184 | }\r | |
185 | }\r | |
186 | \r | |
187 | // The protocol instance produced by this driver\r | |
188 | EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {\r | |
189 | RegisterInterruptSource,\r | |
190 | GicV3EnableInterruptSource,\r | |
191 | GicV3DisableInterruptSource,\r | |
192 | GicV3GetInterruptSourceState,\r | |
193 | GicV3EndOfInterrupt\r | |
194 | };\r | |
195 | \r | |
196 | /**\r | |
197 | Get interrupt trigger type of an interrupt\r | |
198 | \r | |
199 | @param This Instance pointer for this protocol\r | |
200 | @param Source Hardware source of the interrupt.\r | |
201 | @param TriggerType Returns interrupt trigger type.\r | |
202 | \r | |
203 | @retval EFI_SUCCESS Source interrupt supported.\r | |
204 | @retval EFI_UNSUPPORTED Source interrupt is not supported.\r | |
205 | **/\r | |
206 | STATIC\r | |
207 | EFI_STATUS\r | |
208 | EFIAPI\r | |
209 | GicV3GetTriggerType (\r | |
210 | IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This,\r | |
211 | IN HARDWARE_INTERRUPT_SOURCE Source,\r | |
212 | OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType\r | |
213 | )\r | |
214 | {\r | |
215 | UINTN RegAddress;\r | |
216 | UINTN Config1Bit;\r | |
217 | EFI_STATUS Status;\r | |
218 | \r | |
219 | Status = GicGetDistributorIcfgBaseAndBit (\r | |
220 | Source,\r | |
221 | &RegAddress,\r | |
222 | &Config1Bit\r | |
223 | );\r | |
224 | \r | |
225 | if (EFI_ERROR (Status)) {\r | |
226 | return Status;\r | |
227 | }\r | |
228 | \r | |
229 | if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {\r | |
230 | *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;\r | |
231 | } else {\r | |
232 | *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;\r | |
233 | }\r | |
234 | \r | |
235 | return EFI_SUCCESS;\r | |
236 | }\r | |
237 | \r | |
238 | /**\r | |
239 | Set interrupt trigger type of an interrupt\r | |
240 | \r | |
241 | @param This Instance pointer for this protocol\r | |
242 | @param Source Hardware source of the interrupt.\r | |
243 | @param TriggerType Interrupt trigger type.\r | |
244 | \r | |
245 | @retval EFI_SUCCESS Source interrupt supported.\r | |
246 | @retval EFI_UNSUPPORTED Source interrupt is not supported.\r | |
247 | **/\r | |
248 | STATIC\r | |
249 | EFI_STATUS\r | |
250 | EFIAPI\r | |
251 | GicV3SetTriggerType (\r | |
252 | IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This,\r | |
253 | IN HARDWARE_INTERRUPT_SOURCE Source,\r | |
254 | IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType\r | |
255 | )\r | |
256 | {\r | |
257 | UINTN RegAddress;\r | |
258 | UINTN Config1Bit;\r | |
259 | UINT32 Value;\r | |
260 | EFI_STATUS Status;\r | |
261 | BOOLEAN SourceEnabled;\r | |
262 | \r | |
263 | if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)\r | |
264 | && (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH)) {\r | |
265 | DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \\r | |
266 | TriggerType));\r | |
267 | ASSERT (FALSE);\r | |
268 | return EFI_UNSUPPORTED;\r | |
269 | }\r | |
270 | \r | |
271 | Status = GicGetDistributorIcfgBaseAndBit (\r | |
272 | Source,\r | |
273 | &RegAddress,\r | |
274 | &Config1Bit\r | |
275 | );\r | |
276 | \r | |
277 | if (EFI_ERROR (Status)) {\r | |
278 | return Status;\r | |
279 | }\r | |
280 | \r | |
281 | Status = GicV3GetInterruptSourceState (\r | |
282 | (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,\r | |
283 | Source,\r | |
284 | &SourceEnabled\r | |
285 | );\r | |
286 | \r | |
287 | if (EFI_ERROR (Status)) {\r | |
288 | return Status;\r | |
289 | }\r | |
290 | \r | |
291 | Value = (TriggerType == EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)\r | |
292 | ? ARM_GIC_ICDICFR_EDGE_TRIGGERED\r | |
293 | : ARM_GIC_ICDICFR_LEVEL_TRIGGERED;\r | |
294 | \r | |
295 | // Before changing the value, we must disable the interrupt,\r | |
296 | // otherwise GIC behavior is UNPREDICTABLE.\r | |
297 | if (SourceEnabled) {\r | |
298 | GicV3DisableInterruptSource (\r | |
299 | (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,\r | |
300 | Source\r | |
301 | );\r | |
302 | }\r | |
303 | \r | |
304 | MmioAndThenOr32 (\r | |
305 | RegAddress,\r | |
306 | ~(0x1 << Config1Bit),\r | |
307 | Value << Config1Bit\r | |
308 | );\r | |
309 | // Restore interrupt state\r | |
310 | if (SourceEnabled) {\r | |
311 | GicV3EnableInterruptSource (\r | |
312 | (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,\r | |
313 | Source\r | |
314 | );\r | |
315 | }\r | |
316 | \r | |
317 | return EFI_SUCCESS;\r | |
318 | }\r | |
319 | \r | |
320 | EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol = {\r | |
321 | (HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,\r | |
322 | (HARDWARE_INTERRUPT2_ENABLE)GicV3EnableInterruptSource,\r | |
323 | (HARDWARE_INTERRUPT2_DISABLE)GicV3DisableInterruptSource,\r | |
324 | (HARDWARE_INTERRUPT2_INTERRUPT_STATE)GicV3GetInterruptSourceState,\r | |
325 | (HARDWARE_INTERRUPT2_END_OF_INTERRUPT)GicV3EndOfInterrupt,\r | |
326 | GicV3GetTriggerType,\r | |
327 | GicV3SetTriggerType\r | |
328 | };\r | |
329 | \r | |
330 | /**\r | |
331 | Shutdown our hardware\r | |
332 | \r | |
333 | DXE Core will disable interrupts and turn off the timer and disable interrupts\r | |
334 | after all the event handlers have run.\r | |
335 | \r | |
336 | @param[in] Event The Event that is being processed\r | |
337 | @param[in] Context Event Context\r | |
338 | **/\r | |
339 | VOID\r | |
340 | EFIAPI\r | |
341 | GicV3ExitBootServicesEvent (\r | |
342 | IN EFI_EVENT Event,\r | |
343 | IN VOID *Context\r | |
344 | )\r | |
345 | {\r | |
346 | UINTN Index;\r | |
347 | \r | |
348 | // Acknowledge all pending interrupts\r | |
349 | for (Index = 0; Index < mGicNumInterrupts; Index++) {\r | |
350 | GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);\r | |
351 | }\r | |
352 | \r | |
353 | for (Index = 0; Index < mGicNumInterrupts; Index++) {\r | |
354 | GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, Index);\r | |
355 | }\r | |
356 | \r | |
357 | // Disable Gic Interface\r | |
358 | ArmGicV3DisableInterruptInterface ();\r | |
359 | \r | |
360 | // Disable Gic Distributor\r | |
361 | ArmGicDisableDistributor (mGicDistributorBase);\r | |
362 | }\r | |
363 | \r | |
364 | /**\r | |
365 | Initialize the state information for the CPU Architectural Protocol\r | |
366 | \r | |
367 | @param ImageHandle of the loaded driver\r | |
368 | @param SystemTable Pointer to the System Table\r | |
369 | \r | |
370 | @retval EFI_SUCCESS Protocol registered\r | |
371 | @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure\r | |
372 | @retval EFI_DEVICE_ERROR Hardware problems\r | |
373 | \r | |
374 | **/\r | |
375 | EFI_STATUS\r | |
376 | GicV3DxeInitialize (\r | |
377 | IN EFI_HANDLE ImageHandle,\r | |
378 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
379 | )\r | |
380 | {\r | |
381 | EFI_STATUS Status;\r | |
382 | UINTN Index;\r | |
383 | UINT32 RegOffset;\r | |
384 | UINTN RegShift;\r | |
385 | UINT64 CpuTarget;\r | |
386 | UINT64 MpId;\r | |
387 | \r | |
388 | // Make sure the Interrupt Controller Protocol is not already installed in\r | |
389 | // the system.\r | |
390 | ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r | |
391 | \r | |
392 | mGicDistributorBase = PcdGet64 (PcdGicDistributorBase);\r | |
393 | mGicRedistributorsBase = PcdGet64 (PcdGicRedistributorsBase);\r | |
394 | mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);\r | |
395 | \r | |
396 | // We will be driving this GIC in native v3 mode, i.e., with Affinity\r | |
397 | // Routing enabled. So ensure that the ARE bit is set.\r | |
398 | if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r | |
399 | MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE);\r | |
400 | }\r | |
401 | \r | |
402 | for (Index = 0; Index < mGicNumInterrupts; Index++) {\r | |
403 | GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);\r | |
404 | \r | |
405 | // Set Priority\r | |
406 | RegOffset = Index / 4;\r | |
407 | RegShift = (Index % 4) * 8;\r | |
408 | MmioAndThenOr32 (\r | |
409 | mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),\r | |
410 | ~(0xff << RegShift),\r | |
411 | ARM_GIC_DEFAULT_PRIORITY << RegShift\r | |
412 | );\r | |
413 | }\r | |
414 | \r | |
415 | // Targets the interrupts to the Primary Cpu\r | |
416 | \r | |
417 | if (FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r | |
418 | // Only Primary CPU will run this code. We can identify our GIC CPU ID by\r | |
419 | // reading the GIC Distributor Target register. The 8 first\r | |
420 | // GICD_ITARGETSRn are banked to each connected CPU. These 8 registers\r | |
421 | // hold the CPU targets fields for interrupts 0-31. More Info in the GIC\r | |
422 | // Specification about "Interrupt Processor Targets Registers"\r | |
423 | \r | |
424 | // Read the first Interrupt Processor Targets Register (that corresponds\r | |
425 | // to the 4 first SGIs)\r | |
426 | CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);\r | |
427 | \r | |
428 | // The CPU target is a bit field mapping each CPU to a GIC CPU Interface.\r | |
429 | // This value is 0 when we run on a uniprocessor platform.\r | |
430 | if (CpuTarget != 0) {\r | |
431 | // The 8 first Interrupt Processor Targets Registers are read-only\r | |
432 | for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {\r | |
433 | MmioWrite32 (\r | |
434 | mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4),\r | |
435 | CpuTarget\r | |
436 | );\r | |
437 | }\r | |
438 | }\r | |
439 | } else {\r | |
440 | MpId = ArmReadMpidr ();\r | |
441 | CpuTarget = MpId &\r | |
442 | (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);\r | |
443 | \r | |
444 | if ((MmioRead32 (\r | |
445 | mGicDistributorBase + ARM_GIC_ICDDCR\r | |
446 | ) & ARM_GIC_ICDDCR_DS) != 0) {\r | |
447 | \r | |
448 | // If the Disable Security (DS) control bit is set, we are dealing with a\r | |
449 | // GIC that has only one security state. In this case, let's assume we are\r | |
450 | // executing in non-secure state (which is appropriate for DXE modules)\r | |
451 | // and that no other firmware has performed any configuration on the GIC.\r | |
452 | // This means we need to reconfigure all interrupts to non-secure Group 1\r | |
453 | // first.\r | |
454 | \r | |
455 | MmioWrite32 (\r | |
456 | mGicRedistributorsBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDISR,\r | |
457 | 0xffffffff\r | |
458 | );\r | |
459 | \r | |
460 | for (Index = 32; Index < mGicNumInterrupts; Index += 32) {\r | |
461 | MmioWrite32 (\r | |
462 | mGicDistributorBase + ARM_GIC_ICDISR + Index / 8,\r | |
463 | 0xffffffff\r | |
464 | );\r | |
465 | }\r | |
466 | }\r | |
467 | \r | |
468 | // Route the SPIs to the primary CPU. SPIs start at the INTID 32\r | |
469 | for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {\r | |
470 | MmioWrite64 (\r | |
471 | mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),\r | |
472 | CpuTarget\r | |
473 | );\r | |
474 | }\r | |
475 | }\r | |
476 | \r | |
477 | // Set binary point reg to 0x7 (no preemption)\r | |
478 | ArmGicV3SetBinaryPointer (0x7);\r | |
479 | \r | |
480 | // Set priority mask reg to 0xff to allow all priorities through\r | |
481 | ArmGicV3SetPriorityMask (0xff);\r | |
482 | \r | |
483 | // Enable gic cpu interface\r | |
484 | ArmGicV3EnableInterruptInterface ();\r | |
485 | \r | |
486 | // Enable gic distributor\r | |
487 | ArmGicEnableDistributor (mGicDistributorBase);\r | |
488 | \r | |
489 | Status = InstallAndRegisterInterruptService (\r | |
490 | &gHardwareInterruptV3Protocol,\r | |
491 | &gHardwareInterrupt2V3Protocol,\r | |
492 | GicV3IrqInterruptHandler,\r | |
493 | GicV3ExitBootServicesEvent\r | |
494 | );\r | |
495 | \r | |
496 | return Status;\r | |
497 | }\r |