[mirror_edk2.git] / ArmPkg / Drivers / CpuDxe / ArmV6 / Mmu.c

/*++\r
\r
Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r
Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>\r
\r
This program and the accompanying materials                          \r
are licensed and made available under the terms and conditions of the BSD License         \r
which accompanies this distribution.  The full text of the license may be found at        \r
http://opensource.org/licenses/bsd-license.php                                            \r
                                                                                          \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
\r
--*/\r
\r
#include "CpuDxe.h"\r
\r
// First Level Descriptors\r
typedef UINT32    ARM_FIRST_LEVEL_DESCRIPTOR;\r
\r
// Second Level Descriptors\r
typedef UINT32    ARM_PAGE_TABLE_ENTRY;\r
\r
EFI_STATUS \r
SectionToGcdAttributes (\r
  IN  UINT32  SectionAttributes,\r
  OUT UINT64  *GcdAttributes\r
  )\r
{\r
  *GcdAttributes = 0;\r
\r
  // determine cacheability attributes\r
  switch(SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) {\r
    case TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED:\r
      *GcdAttributes |= EFI_MEMORY_UC;\r
      break;\r
    case TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE:\r
      *GcdAttributes |= EFI_MEMORY_UC;\r
      break;\r
    case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC:\r
      *GcdAttributes |= EFI_MEMORY_WT;\r
      break;\r
    case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC:\r
      *GcdAttributes |= EFI_MEMORY_WB;\r
      break;\r
    case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE:\r
      *GcdAttributes |= EFI_MEMORY_WC;\r
      break;\r
    case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC:\r
      *GcdAttributes |= EFI_MEMORY_WB;\r
      break;\r
    case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE:\r
      *GcdAttributes |= EFI_MEMORY_UC;\r
      break;\r
    default:\r
      return EFI_UNSUPPORTED;\r
  }\r
\r
  // determine protection attributes\r
  switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {\r
    case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write\r
      //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;\r
      break;\r
\r
    case TT_DESCRIPTOR_SECTION_AP_RW_NO:\r
    case TT_DESCRIPTOR_SECTION_AP_RW_RW:\r
      // normal read/write access, do not add additional attributes\r
      break;\r
\r
    // read only cases map to write-protect\r
    case TT_DESCRIPTOR_SECTION_AP_RO_NO:\r
    case TT_DESCRIPTOR_SECTION_AP_RO_RO:\r
      *GcdAttributes |= EFI_MEMORY_WP;\r
      break;\r
\r
    default:\r
      return EFI_UNSUPPORTED;\r
  }\r
\r
  // now process eXectue Never attribute\r
  if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) != 0 ) {\r
    *GcdAttributes |= EFI_MEMORY_XP;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
PageToGcdAttributes (\r
  IN  UINT32  PageAttributes,\r
  OUT UINT64  *GcdAttributes\r
  )\r
{\r
  *GcdAttributes = 0;\r
\r
  // determine cacheability attributes\r
  switch(PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) {\r
    case TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED:\r
      *GcdAttributes |= EFI_MEMORY_UC;\r
      break;\r
    case TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE:\r
      *GcdAttributes |= EFI_MEMORY_UC;\r
      break;\r
    case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC:\r
      *GcdAttributes |= EFI_MEMORY_WT;\r
      break;\r
    case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC:\r
      *GcdAttributes |= EFI_MEMORY_WB;\r
      break;\r
    case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE:\r
      *GcdAttributes |= EFI_MEMORY_WC;\r
      break;\r
    case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC:\r
      *GcdAttributes |= EFI_MEMORY_WB;\r
      break;\r
    case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE:\r
      *GcdAttributes |= EFI_MEMORY_UC;\r
      break;\r
    default:\r
      return EFI_UNSUPPORTED;\r
  }\r
\r
  // determine protection attributes\r
  switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) {\r
    case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write\r
      //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;\r
      break;\r
\r
    case TT_DESCRIPTOR_PAGE_AP_RW_NO:\r
    case TT_DESCRIPTOR_PAGE_AP_RW_RW:\r
      // normal read/write access, do not add additional attributes\r
      break;\r
\r
    // read only cases map to write-protect\r
    case TT_DESCRIPTOR_PAGE_AP_RO_NO:\r
    case TT_DESCRIPTOR_PAGE_AP_RO_RO:\r
      *GcdAttributes |= EFI_MEMORY_WP;\r
      break;\r
\r
    default:\r
      return EFI_UNSUPPORTED;\r
  }\r
\r
  // now process eXectue Never attribute\r
  if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) != 0 ) {\r
    *GcdAttributes |= EFI_MEMORY_XP;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
SyncCacheConfigPage (\r
  IN     UINT32                             SectionIndex,\r
  IN     UINT32                             FirstLevelDescriptor,\r
  IN     UINTN                              NumberOfDescriptors,\r
  IN     EFI_GCD_MEMORY_SPACE_DESCRIPTOR    *MemorySpaceMap,\r
  IN OUT EFI_PHYSICAL_ADDRESS               *NextRegionBase,\r
  IN OUT UINT64                             *NextRegionLength,\r
  IN OUT UINT32                             *NextSectionAttributes\r
  )\r
{\r
  EFI_STATUS                          Status;\r
  UINT32                              i;\r
  volatile ARM_PAGE_TABLE_ENTRY       *SecondLevelTable;\r
  UINT32                              NextPageAttributes = 0;\r
  UINT32                              PageAttributes = 0;\r
  UINT32                              BaseAddress;\r
  UINT64                              GcdAttributes;\r
\r
  // Get the Base Address from FirstLevelDescriptor;\r
  BaseAddress = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(SectionIndex << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
\r
  // Convert SectionAttributes into PageAttributes\r
  NextPageAttributes =\r
      TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(*NextSectionAttributes,0) |\r
      TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(*NextSectionAttributes);\r
\r
  // obtain page table base\r
  SecondLevelTable = (ARM_PAGE_TABLE_ENTRY *)(FirstLevelDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);\r
\r
  for (i=0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {\r
    if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) {\r
      // extract attributes (cacheability and permissions)\r
      PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK);\r
\r
      if (NextPageAttributes == 0) {\r
        // start on a new region\r
        *NextRegionLength = 0;\r
        *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r
        NextPageAttributes = PageAttributes;\r
      } else if (PageAttributes != NextPageAttributes) {\r
        // Convert Section Attributes into GCD Attributes\r
        Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes);\r
        ASSERT_EFI_ERROR (Status);\r
\r
        // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
        SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);\r
\r
        // start on a new region\r
        *NextRegionLength = 0;\r
        *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r
        NextPageAttributes = PageAttributes;\r
      }\r
    } else if (NextPageAttributes != 0) {\r
      // Convert Page Attributes into GCD Attributes\r
      Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes);\r
      ASSERT_EFI_ERROR (Status);\r
\r
      // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
      SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);\r
\r
      *NextRegionLength = 0;\r
      *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r
      NextPageAttributes = 0;\r
    }\r
    *NextRegionLength += TT_DESCRIPTOR_PAGE_SIZE;\r
  }\r
\r
  // Convert back PageAttributes into SectionAttributes\r
  *NextSectionAttributes =\r
      TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(NextPageAttributes,0) |\r
      TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(NextPageAttributes);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
SyncCacheConfig (\r
  IN  EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r
  )\r
{\r
  EFI_STATUS                          Status;\r
  UINT32                              i;\r
  EFI_PHYSICAL_ADDRESS                NextRegionBase;\r
  UINT64                              NextRegionLength;\r
  UINT32                              NextSectionAttributes = 0;\r
  UINT32                              SectionAttributes = 0;\r
  UINT64                              GcdAttributes;\r
  volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;\r
  UINTN                               NumberOfDescriptors;\r
  EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap;\r
\r
\r
  DEBUG ((EFI_D_PAGE, "SyncCacheConfig()\n"));\r
\r
  // This code assumes MMU is enabled and filed with section translations\r
  ASSERT (ArmMmuEnabled ());\r
\r
  //\r
  // Get the memory space map from GCD\r
  //\r
  MemorySpaceMap = NULL;\r
  Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r
  ASSERT_EFI_ERROR (Status);\r
\r
\r
  // The GCD implementation maintains its own copy of the state of memory space attributes.  GCD needs\r
  // to know what the initial memory space attributes are.  The CPU Arch. Protocol does not provide a\r
  // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were\r
  // a client) to update its copy of the attributes.  This is bad architecture and should be replaced\r
  // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.\r
\r
  // obtain page table base\r
  FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTTBR0BaseAddress ());\r
\r
  // Get the first region\r
  NextSectionAttributes = FirstLevelTable[0] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);\r
\r
  // iterate through each 1MB descriptor\r
  NextRegionBase = NextRegionLength = 0;\r
  for (i=0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) {\r
    if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {\r
      // extract attributes (cacheability and permissions)\r
      SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);\r
\r
      if (NextSectionAttributes == 0) {\r
        // start on a new region\r
        NextRegionLength = 0;\r
        NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
        NextSectionAttributes = SectionAttributes;\r
      } else if (SectionAttributes != NextSectionAttributes) {\r
        // Convert Section Attributes into GCD Attributes\r
        Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);\r
        ASSERT_EFI_ERROR (Status);\r
\r
        // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
        SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r
\r
        // start on a new region\r
        NextRegionLength = 0;\r
        NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
        NextSectionAttributes = SectionAttributes;\r
      }\r
      NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;\r
    } else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(FirstLevelTable[i])) {\r
      Status = SyncCacheConfigPage (\r
          i,FirstLevelTable[i],\r
          NumberOfDescriptors, MemorySpaceMap,\r
          &NextRegionBase,&NextRegionLength,&NextSectionAttributes);\r
      ASSERT_EFI_ERROR (Status);\r
    } else {\r
      // We do not support yet 16MB sections\r
      ASSERT ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) != TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION);\r
\r
      // start on a new region\r
      if (NextSectionAttributes != 0) {\r
        // Convert Section Attributes into GCD Attributes\r
        Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);\r
        ASSERT_EFI_ERROR (Status);\r
\r
        // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
        SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r
\r
        NextRegionLength = 0;\r
        NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
        NextSectionAttributes = 0;\r
      }\r
      NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;\r
    }\r
  } // section entry loop\r
\r
  if (NextSectionAttributes != 0) {\r
    // Convert Section Attributes into GCD Attributes\r
    Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);\r
    ASSERT_EFI_ERROR (Status);\r
\r
    // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
    SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
\r
\r
EFI_STATUS\r
UpdatePageEntries (\r
  IN EFI_PHYSICAL_ADDRESS      BaseAddress,\r
  IN UINT64                    Length,\r
  IN UINT64                    Attributes,\r
  IN EFI_PHYSICAL_ADDRESS      VirtualMask\r
  )\r
{\r
  EFI_STATUS    Status;\r
  UINT32        EntryValue;\r
  UINT32        EntryMask;\r
  UINT32        FirstLevelIdx;\r
  UINT32        Offset;\r
  UINT32        NumPageEntries;\r
  UINT32        Descriptor;\r
  UINT32        p;\r
  UINT32        PageTableIndex;\r
  UINT32        PageTableEntry;\r
  UINT32        CurrentPageTableEntry;\r
  VOID          *Mva;\r
\r
  volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;\r
  volatile ARM_PAGE_TABLE_ENTRY         *PageTable;\r
\r
  Status = EFI_SUCCESS;\r
\r
  // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
  // EntryValue: values at bit positions specified by EntryMask\r
  EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK;\r
  EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;\r
  // Although the PI spec is unclear on this the GCD guarantees that only\r
  // one Attribute bit is set at a time, so we can safely use a switch statement\r
  switch (Attributes) {\r
    case EFI_MEMORY_UC:\r
      // modify cacheability attributes\r
      EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
      // map to strongly ordered\r
      EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r
      break;\r
\r
    case EFI_MEMORY_WC:\r
      // modify cacheability attributes\r
      EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
      // map to normal non-cachable\r
      EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r
      break;\r
\r
    case EFI_MEMORY_WT:\r
      // modify cacheability attributes\r
      EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
      // write through with no-allocate\r
      EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0\r
      break;\r
\r
    case EFI_MEMORY_WB:\r
      // modify cacheability attributes\r
      EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
      // write back (with allocate)\r
      EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1\r
      break;\r
\r
    case EFI_MEMORY_WP:\r
    case EFI_MEMORY_XP:\r
    case EFI_MEMORY_UCE:\r
      // cannot be implemented UEFI definition unclear for ARM\r
      // Cause a page fault if these ranges are accessed.\r
      EntryValue = TT_DESCRIPTOR_PAGE_TYPE_FAULT;\r
      DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r
      break;\r
\r
    default:\r
      return EFI_UNSUPPORTED;\r
  }\r
\r
  // Obtain page table base\r
  FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
\r
  // Calculate number of 4KB page table entries to change\r
  NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;\r
  \r
  // Iterate for the number of 4KB pages to change\r
  Offset = 0;\r
  for(p = 0; p < NumPageEntries; p++) {\r
    // Calculate index into first level translation table for page table value\r
    \r
    FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
    ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
\r
    // Read the descriptor from the first level page table\r
    Descriptor = FirstLevelTable[FirstLevelIdx];\r
\r
    // Does this descriptor need to be converted from section entry to 4K pages?\r
    if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) {\r
      Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
      if (EFI_ERROR(Status)) {\r
        // Exit for loop\r
        break; \r
      } \r
      \r
      // Re-read descriptor\r
      Descriptor = FirstLevelTable[FirstLevelIdx];\r
    }\r
\r
    // Obtain page table base address\r
    PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor);\r
\r
    // Calculate index into the page table\r
    PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;\r
    ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);\r
\r
    // Get the entry\r
    CurrentPageTableEntry = PageTable[PageTableIndex];\r
\r
    // Mask off appropriate fields\r
    PageTableEntry = CurrentPageTableEntry & ~EntryMask;\r
\r
    // Mask in new attributes and/or permissions\r
    PageTableEntry |= EntryValue;\r
\r
    if (VirtualMask != 0) {\r
      // Make this virtual address point at a physical page\r
      PageTableEntry &= ~VirtualMask;\r
    }\r
   \r
    if (CurrentPageTableEntry  != PageTableEntry) {\r
      Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));\r
      if ((CurrentPageTableEntry & TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) == TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) {\r
        // The current section mapping is cacheable so Clean/Invalidate the MVA of the page\r
        // Note assumes switch(Attributes), not ARMv7 possibilities\r
        WriteBackInvalidateDataCacheRange (Mva, TT_DESCRIPTOR_PAGE_SIZE);\r
      }\r
\r
      // Only need to update if we are changing the entry  \r
      PageTable[PageTableIndex] = PageTableEntry; \r
      ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);\r
    }\r
\r
    Status = EFI_SUCCESS;\r
    Offset += TT_DESCRIPTOR_PAGE_SIZE;\r
    \r
  } // End first level translation table loop\r
\r
  return Status;\r
}\r
\r
\r
\r
EFI_STATUS\r
UpdateSectionEntries (\r
  IN EFI_PHYSICAL_ADDRESS      BaseAddress,\r
  IN UINT64                    Length,\r
  IN UINT64                    Attributes,\r
  IN EFI_PHYSICAL_ADDRESS      VirtualMask\r
  )\r
{\r
  EFI_STATUS    Status = EFI_SUCCESS;\r
  UINT32        EntryMask;\r
  UINT32        EntryValue;\r
  UINT32        FirstLevelIdx;\r
  UINT32        NumSections;\r
  UINT32        i;\r
  UINT32        CurrentDescriptor;\r
  UINT32        Descriptor;\r
  VOID          *Mva;\r
  volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;\r
\r
  // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
  // EntryValue: values at bit positions specified by EntryMask\r
\r
  // Make sure we handle a section range that is unmapped \r
  EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK;\r
  EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;\r
\r
  // Although the PI spec is unclear on this the GCD guarantees that only\r
  // one Attribute bit is set at a time, so we can safely use a switch statement\r
  switch(Attributes) {\r
    case EFI_MEMORY_UC:\r
      // modify cacheability attributes\r
      EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
      // map to strongly ordered\r
      EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r
      break;\r
\r
    case EFI_MEMORY_WC:\r
      // modify cacheability attributes\r
      EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
      // map to normal non-cachable\r
      EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r
      break;\r
\r
    case EFI_MEMORY_WT:\r
      // modify cacheability attributes\r
      EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
      // write through with no-allocate\r
      EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0\r
      break;\r
\r
    case EFI_MEMORY_WB:\r
      // modify cacheability attributes\r
      EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
      // write back (with allocate)\r
      EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1\r
      break;\r
\r
    case EFI_MEMORY_WP:\r
    case EFI_MEMORY_XP:\r
    case EFI_MEMORY_RP:\r
    case EFI_MEMORY_UCE:\r
      // cannot be implemented UEFI definition unclear for ARM\r
      // Cause a page fault if these ranges are accessed.\r
      EntryValue = TT_DESCRIPTOR_SECTION_TYPE_FAULT;\r
      DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r
      break;\r
\r
\r
    default:\r
      return EFI_UNSUPPORTED;\r
  }\r
\r
  // obtain page table base\r
  FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
\r
  // calculate index into first level translation table for start of modification\r
  FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
  ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
\r
  // calculate number of 1MB first level entries this applies to\r
  NumSections = Length / TT_DESCRIPTOR_SECTION_SIZE;\r
  \r
  // iterate through each descriptor\r
  for(i=0; i<NumSections; i++) {\r
    CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];\r
\r
    // has this descriptor already been coverted to pages?\r
    if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor)) {\r
      // forward this 1MB range to page table function instead\r
      Status = UpdatePageEntries ((FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT, TT_DESCRIPTOR_SECTION_SIZE, Attributes, VirtualMask);\r
    } else {\r
      // still a section entry\r
      \r
      // mask off appropriate fields\r
      Descriptor = CurrentDescriptor & ~EntryMask;\r
\r
      // mask in new attributes and/or permissions\r
      Descriptor |= EntryValue;\r
      if (VirtualMask != 0) {\r
        Descriptor &= ~VirtualMask;\r
      }\r
\r
      if (CurrentDescriptor  != Descriptor) {\r
        Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
        if ((CurrentDescriptor & TT_DESCRIPTOR_SECTION_CACHEABLE_MASK) == TT_DESCRIPTOR_SECTION_CACHEABLE_MASK) {\r
          // The current section mapping is cacheable so Clean/Invalidate the MVA of the section\r
          // Note assumes switch(Attributes), not ARMv7 possabilities\r
          WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);\r
        }\r
\r
        // Only need to update if we are changing the descriptor  \r
        FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r
        ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);\r
      }\r
\r
      Status = EFI_SUCCESS;\r
    }\r
  }\r
\r
  return Status;\r
}\r
\r
EFI_STATUS \r
ConvertSectionToPages (\r
  IN EFI_PHYSICAL_ADDRESS  BaseAddress\r
  )\r
{\r
  EFI_STATUS              Status;\r
  EFI_PHYSICAL_ADDRESS    PageTableAddr;\r
  UINT32                  FirstLevelIdx;\r
  UINT32                  SectionDescriptor;\r
  UINT32                  PageTableDescriptor;\r
  UINT32                  PageDescriptor;\r
  UINT32                  Index;\r
\r
  volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;\r
  volatile ARM_PAGE_TABLE_ENTRY         *PageTable;\r
\r
  DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));\r
\r
  // Obtain page table base\r
  FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
\r
  // Calculate index into first level translation table for start of modification\r
  FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
  ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
\r
  // Get section attributes and convert to page attributes\r
  SectionDescriptor = FirstLevelTable[FirstLevelIdx];\r
  PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE;\r
  PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(SectionDescriptor,0);\r
  PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(SectionDescriptor);\r
  PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(SectionDescriptor,0);\r
  PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(SectionDescriptor);\r
  PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S(SectionDescriptor);\r
\r
  // Allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)\r
  Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, 1, &PageTableAddr);\r
  if (EFI_ERROR(Status)) {\r
    return Status;\r
  }\r
\r
  PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;\r
\r
  // Write the page table entries out\r
  for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {\r
    PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;\r
  }\r
\r
  // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
  WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, TT_DESCRIPTOR_PAGE_SIZE);\r
\r
  // Formulate page table entry, Domain=0, NS=0\r
  PageTableDescriptor = (((UINTN)PageTableAddr) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
\r
  // Write the page table entry out, replacing section entry\r
  FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;\r
\r
  return EFI_SUCCESS;\r
}\r
\r
\r
\r
EFI_STATUS\r
SetMemoryAttributes (\r
  IN EFI_PHYSICAL_ADDRESS      BaseAddress,\r
  IN UINT64                    Length,\r
  IN UINT64                    Attributes,\r
  IN EFI_PHYSICAL_ADDRESS      VirtualMask\r
  )\r
{\r
  EFI_STATUS    Status;\r
  \r
  if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {\r
    // Is the base and length a multiple of 1 MB?\r
    DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
    Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);\r
  } else {\r
    // Base and/or length is not a multiple of 1 MB\r
    DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
    Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);\r
  }\r
\r
  // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
  // flush and invalidate pages\r
  //TODO: Do we really need to invalidate the caches everytime we change the memory attributes ?\r
  ArmCleanInvalidateDataCache ();\r
\r
  ArmInvalidateInstructionCache ();\r
\r
  // Invalidate all TLB entries so changes are synced\r
  ArmInvalidateTlb ();\r
\r
  return Status;\r
}\r