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ARM Packages: Minor typo, mispellings and coding style changes
[mirror_edk2.git] / ArmPkg / Drivers / CpuDxe / Mmu.c
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1/*++\r
2\r
3Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r
4Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>\r
5\r
6This program and the accompanying materials \r
7are licensed and made available under the terms and conditions of the BSD License \r
8which accompanies this distribution. The full text of the license may be found at \r
9http://opensource.org/licenses/bsd-license.php \r
10 \r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
13\r
14\r
15--*/\r
16\r
17#include "CpuDxe.h"\r
18\r
19// First Level Descriptors\r
20typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;\r
21\r
22// Second Level Descriptors\r
23typedef UINT32 ARM_PAGE_TABLE_ENTRY;\r
24\r
25EFI_STATUS \r
26SectionToGcdAttributes (\r
27 IN UINT32 SectionAttributes,\r
28 OUT UINT64 *GcdAttributes\r
29 )\r
30{\r
31 *GcdAttributes = 0;\r
32\r
33 // determine cacheability attributes\r
34 switch(SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) {\r
35 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED:\r
36 *GcdAttributes |= EFI_MEMORY_UC;\r
37 break;\r
38 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE:\r
39 *GcdAttributes |= EFI_MEMORY_UC;\r
40 break;\r
41 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC:\r
42 *GcdAttributes |= EFI_MEMORY_WT;\r
43 break;\r
44 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC:\r
45 *GcdAttributes |= EFI_MEMORY_WB;\r
46 break;\r
47 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE:\r
48 *GcdAttributes |= EFI_MEMORY_WC;\r
49 break;\r
50 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC:\r
51 *GcdAttributes |= EFI_MEMORY_WB;\r
52 break;\r
53 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE:\r
54 *GcdAttributes |= EFI_MEMORY_UC;\r
55 break;\r
56 default:\r
57 return EFI_UNSUPPORTED;\r
58 }\r
59\r
60 // determine protection attributes\r
61 switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {\r
62 case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write\r
63 //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;\r
64 break;\r
65\r
66 case TT_DESCRIPTOR_SECTION_AP_RW_NO:\r
67 case TT_DESCRIPTOR_SECTION_AP_RW_RW:\r
68 // normal read/write access, do not add additional attributes\r
69 break;\r
70\r
71 // read only cases map to write-protect\r
72 case TT_DESCRIPTOR_SECTION_AP_RO_NO:\r
73 case TT_DESCRIPTOR_SECTION_AP_RO_RO:\r
74 *GcdAttributes |= EFI_MEMORY_WP;\r
75 break;\r
76\r
77 default:\r
78 return EFI_UNSUPPORTED;\r
79 }\r
80\r
81 // now process eXectue Never attribute\r
82 if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) != 0 ) {\r
83 *GcdAttributes |= EFI_MEMORY_XP;\r
84 }\r
85\r
86 return EFI_SUCCESS;\r
87}\r
88\r
89EFI_STATUS\r
90PageToGcdAttributes (\r
91 IN UINT32 PageAttributes,\r
92 OUT UINT64 *GcdAttributes\r
93 )\r
94{\r
95 *GcdAttributes = 0;\r
96\r
97 // determine cacheability attributes\r
98 switch(PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) {\r
99 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED:\r
100 *GcdAttributes |= EFI_MEMORY_UC;\r
101 break;\r
102 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE:\r
103 *GcdAttributes |= EFI_MEMORY_UC;\r
104 break;\r
105 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC:\r
106 *GcdAttributes |= EFI_MEMORY_WT;\r
107 break;\r
108 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC:\r
109 *GcdAttributes |= EFI_MEMORY_WB;\r
110 break;\r
111 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE:\r
112 *GcdAttributes |= EFI_MEMORY_WC;\r
113 break;\r
114 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC:\r
115 *GcdAttributes |= EFI_MEMORY_WB;\r
116 break;\r
117 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE:\r
118 *GcdAttributes |= EFI_MEMORY_UC;\r
119 break;\r
120 default:\r
121 return EFI_UNSUPPORTED;\r
122 }\r
123\r
124 // determine protection attributes\r
125 switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) {\r
126 case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write\r
127 //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;\r
128 break;\r
129\r
130 case TT_DESCRIPTOR_PAGE_AP_RW_NO:\r
131 case TT_DESCRIPTOR_PAGE_AP_RW_RW:\r
132 // normal read/write access, do not add additional attributes\r
133 break;\r
134\r
135 // read only cases map to write-protect\r
136 case TT_DESCRIPTOR_PAGE_AP_RO_NO:\r
137 case TT_DESCRIPTOR_PAGE_AP_RO_RO:\r
138 *GcdAttributes |= EFI_MEMORY_WP;\r
139 break;\r
140\r
141 default:\r
142 return EFI_UNSUPPORTED;\r
143 }\r
144\r
145 // now process eXectue Never attribute\r
146 if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) != 0 ) {\r
147 *GcdAttributes |= EFI_MEMORY_XP;\r
148 }\r
149\r
150 return EFI_SUCCESS;\r
151}\r
152\r
153/**\r
154 Searches memory descriptors covered by given memory range.\r
155\r
156 This function searches into the Gcd Memory Space for descriptors\r
157 (from StartIndex to EndIndex) that contains the memory range\r
158 specified by BaseAddress and Length.\r
159\r
160 @param MemorySpaceMap Gcd Memory Space Map as array.\r
161 @param NumberOfDescriptors Number of descriptors in map.\r
162 @param BaseAddress BaseAddress for the requested range.\r
163 @param Length Length for the requested range.\r
164 @param StartIndex Start index into the Gcd Memory Space Map.\r
165 @param EndIndex End index into the Gcd Memory Space Map.\r
166\r
167 @retval EFI_SUCCESS Search successfully.\r
168 @retval EFI_NOT_FOUND The requested descriptors does not exist.\r
169\r
170**/\r
171EFI_STATUS\r
172SearchGcdMemorySpaces (\r
173 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
174 IN UINTN NumberOfDescriptors,\r
175 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
176 IN UINT64 Length,\r
177 OUT UINTN *StartIndex,\r
178 OUT UINTN *EndIndex\r
179 )\r
180{\r
181 UINTN Index;\r
182\r
183 *StartIndex = 0;\r
184 *EndIndex = 0;\r
185 for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
186 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&\r
187 BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
188 *StartIndex = Index;\r
189 }\r
190 if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&\r
191 BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
192 *EndIndex = Index;\r
193 return EFI_SUCCESS;\r
194 }\r
195 }\r
196 return EFI_NOT_FOUND;\r
197}\r
198\r
199\r
200/**\r
201 Sets the attributes for a specified range in Gcd Memory Space Map.\r
202\r
203 This function sets the attributes for a specified range in\r
204 Gcd Memory Space Map.\r
205\r
206 @param MemorySpaceMap Gcd Memory Space Map as array\r
207 @param NumberOfDescriptors Number of descriptors in map\r
208 @param BaseAddress BaseAddress for the range\r
209 @param Length Length for the range\r
210 @param Attributes Attributes to set\r
211\r
212 @retval EFI_SUCCESS Memory attributes set successfully\r
213 @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space\r
214\r
215**/\r
216EFI_STATUS\r
217SetGcdMemorySpaceAttributes (\r
218 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
219 IN UINTN NumberOfDescriptors,\r
220 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
221 IN UINT64 Length,\r
222 IN UINT64 Attributes\r
223 )\r
224{\r
225 EFI_STATUS Status;\r
226 UINTN Index;\r
227 UINTN StartIndex;\r
228 UINTN EndIndex;\r
229 EFI_PHYSICAL_ADDRESS RegionStart;\r
230 UINT64 RegionLength;\r
231\r
232 //\r
233 // Get all memory descriptors covered by the memory range\r
234 //\r
235 Status = SearchGcdMemorySpaces (\r
236 MemorySpaceMap,\r
237 NumberOfDescriptors,\r
238 BaseAddress,\r
239 Length,\r
240 &StartIndex,\r
241 &EndIndex\r
242 );\r
243 if (EFI_ERROR (Status)) {\r
244 return Status;\r
245 }\r
246\r
247 //\r
248 // Go through all related descriptors and set attributes accordingly\r
249 //\r
250 for (Index = StartIndex; Index <= EndIndex; Index++) {\r
251 if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r
252 continue;\r
253 }\r
254 //\r
255 // Calculate the start and end address of the overlapping range\r
256 //\r
257 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {\r
258 RegionStart = BaseAddress;\r
259 } else {\r
260 RegionStart = MemorySpaceMap[Index].BaseAddress;\r
261 }\r
262 if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
263 RegionLength = BaseAddress + Length - RegionStart;\r
264 } else {\r
265 RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;\r
266 }\r
267 //\r
268 // Set memory attributes according to MTRR attribute and the original attribute of descriptor\r
269 //\r
270 gDS->SetMemorySpaceAttributes (\r
271 RegionStart,\r
272 RegionLength,\r
273 (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)\r
274 );\r
275 }\r
276\r
277 return EFI_SUCCESS;\r
278}\r
279\r
280EFI_STATUS\r
281SyncCacheConfigPage (\r
282 IN UINT32 SectionIndex,\r
283 IN UINT32 FirstLevelDescriptor,\r
284 IN UINTN NumberOfDescriptors,\r
285 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
286 IN OUT EFI_PHYSICAL_ADDRESS *NextRegionBase,\r
287 IN OUT UINT64 *NextRegionLength,\r
288 IN OUT UINT32 *NextSectionAttributes\r
289 )\r
290{\r
291 EFI_STATUS Status;\r
292 UINT32 i;\r
293 volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable;\r
294 UINT32 NextPageAttributes = 0;\r
295 UINT32 PageAttributes = 0;\r
296 UINT32 BaseAddress;\r
297 UINT64 GcdAttributes;\r
298\r
299 // Get the Base Address from FirstLevelDescriptor;\r
300 BaseAddress = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(SectionIndex << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
301\r
302 // Convert SectionAttributes into PageAttributes\r
303 NextPageAttributes =\r
304 TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(*NextSectionAttributes,0) |\r
305 TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(*NextSectionAttributes);\r
306\r
307 // obtain page table base\r
308 SecondLevelTable = (ARM_PAGE_TABLE_ENTRY *)(FirstLevelDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);\r
309\r
310 for (i=0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {\r
311 if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) {\r
312 // extract attributes (cacheability and permissions)\r
313 PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK);\r
314\r
315 if (NextPageAttributes == 0) {\r
316 // start on a new region\r
317 *NextRegionLength = 0;\r
318 *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r
319 NextPageAttributes = PageAttributes;\r
320 } else if (PageAttributes != NextPageAttributes) {\r
321 // Convert Section Attributes into GCD Attributes\r
322 Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes);\r
323 ASSERT_EFI_ERROR (Status);\r
324\r
325 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
326 SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);\r
327\r
328 // start on a new region\r
329 *NextRegionLength = 0;\r
330 *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r
331 NextPageAttributes = PageAttributes;\r
332 }\r
333 } else if (NextPageAttributes != 0) {\r
334 // Convert Page Attributes into GCD Attributes\r
335 Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes);\r
336 ASSERT_EFI_ERROR (Status);\r
337\r
338 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
339 SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);\r
340\r
341 *NextRegionLength = 0;\r
342 *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r
343 NextPageAttributes = 0;\r
344 }\r
345 *NextRegionLength += TT_DESCRIPTOR_PAGE_SIZE;\r
346 }\r
347\r
348 // Convert back PageAttributes into SectionAttributes\r
349 *NextSectionAttributes =\r
350 TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(NextPageAttributes,0) |\r
351 TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(NextPageAttributes);\r
352\r
353 return EFI_SUCCESS;\r
354}\r
355\r
356EFI_STATUS\r
357SyncCacheConfig (\r
358 IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r
359 )\r
360{\r
361 EFI_STATUS Status;\r
362 UINT32 i;\r
363 EFI_PHYSICAL_ADDRESS NextRegionBase;\r
364 UINT64 NextRegionLength;\r
365 UINT32 NextSectionAttributes = 0;\r
366 UINT32 SectionAttributes = 0;\r
367 UINT64 GcdAttributes;\r
368 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
369 UINTN NumberOfDescriptors;\r
370 EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r
371\r
372\r
373 DEBUG ((EFI_D_PAGE, "SyncCacheConfig()\n"));\r
374\r
375 // This code assumes MMU is enabled and filed with section translations\r
376 ASSERT (ArmMmuEnabled ());\r
377\r
378 //\r
379 // Get the memory space map from GCD\r
380 //\r
381 MemorySpaceMap = NULL;\r
382 Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r
383 ASSERT_EFI_ERROR (Status);\r
384\r
385\r
386 // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs\r
387 // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a\r
388 // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were\r
389 // a client) to update its copy of the attributes. This is bad architecture and should be replaced\r
390 // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.\r
391\r
392 // obtain page table base\r
393 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTTBR0BaseAddress ());\r
394\r
395 // Get the first region\r
396 NextSectionAttributes = FirstLevelTable[0] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);\r
397\r
398 // iterate through each 1MB descriptor\r
399 NextRegionBase = NextRegionLength = 0;\r
400 for (i=0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) {\r
401 if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {\r
402 // extract attributes (cacheability and permissions)\r
403 SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);\r
404\r
405 if (NextSectionAttributes == 0) {\r
406 // start on a new region\r
407 NextRegionLength = 0;\r
408 NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
409 NextSectionAttributes = SectionAttributes;\r
410 } else if (SectionAttributes != NextSectionAttributes) {\r
411 // Convert Section Attributes into GCD Attributes\r
412 Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);\r
413 ASSERT_EFI_ERROR (Status);\r
414\r
415 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
416 SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r
417\r
418 // start on a new region\r
419 NextRegionLength = 0;\r
420 NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
421 NextSectionAttributes = SectionAttributes;\r
422 }\r
423 NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;\r
424 } else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(FirstLevelTable[i])) {\r
425 Status = SyncCacheConfigPage (\r
426 i,FirstLevelTable[i],\r
427 NumberOfDescriptors, MemorySpaceMap,\r
428 &NextRegionBase,&NextRegionLength,&NextSectionAttributes);\r
429 ASSERT_EFI_ERROR (Status);\r
430 } else {\r
431 // We do not support yet 16MB sections\r
432 ASSERT ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) != TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION);\r
433\r
434 // start on a new region\r
435 if (NextSectionAttributes != 0) {\r
436 // Convert Section Attributes into GCD Attributes\r
437 Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);\r
438 ASSERT_EFI_ERROR (Status);\r
439\r
440 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
441 SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r
442\r
443 NextRegionLength = 0;\r
444 NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
445 NextSectionAttributes = 0;\r
446 }\r
447 NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;\r
448 }\r
449 } // section entry loop\r
450\r
451 if (NextSectionAttributes != 0) {\r
452 // Convert Section Attributes into GCD Attributes\r
453 Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);\r
454 ASSERT_EFI_ERROR (Status);\r
455\r
456 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
457 SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r
458 }\r
459\r
460 return EFI_SUCCESS;\r
461}\r
462\r
463\r
464\r
465EFI_STATUS\r
466UpdatePageEntries (\r
467 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
468 IN UINT64 Length,\r
469 IN UINT64 Attributes,\r
470 IN EFI_PHYSICAL_ADDRESS VirtualMask\r
471 )\r
472{\r
473 EFI_STATUS Status;\r
474 UINT32 EntryValue;\r
475 UINT32 EntryMask;\r
476 UINT32 FirstLevelIdx;\r
477 UINT32 Offset;\r
478 UINT32 NumPageEntries;\r
479 UINT32 Descriptor;\r
480 UINT32 p;\r
481 UINT32 PageTableIndex;\r
482 UINT32 PageTableEntry;\r
483 UINT32 CurrentPageTableEntry;\r
484 VOID *Mva;\r
485\r
486 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
487 volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r
488\r
489 Status = EFI_SUCCESS;\r
490\r
491 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
492 // EntryValue: values at bit positions specified by EntryMask\r
493 EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK;\r
494 EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;\r
495 // Although the PI spec is unclear on this the GCD guarantees that only\r
496 // one Attribute bit is set at a time, so we can safely use a switch statement\r
497 switch (Attributes) {\r
498 case EFI_MEMORY_UC:\r
499 // modify cacheability attributes\r
500 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
501 // map to strongly ordered\r
502 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r
503 break;\r
504\r
505 case EFI_MEMORY_WC:\r
506 // modify cacheability attributes\r
507 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
508 // map to normal non-cachable\r
509 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r
510 break;\r
511\r
512 case EFI_MEMORY_WT:\r
513 // modify cacheability attributes\r
514 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
515 // write through with no-allocate\r
516 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0\r
517 break;\r
518\r
519 case EFI_MEMORY_WB:\r
520 // modify cacheability attributes\r
521 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
522 // write back (with allocate)\r
523 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1\r
524 break;\r
525\r
526 case EFI_MEMORY_WP:\r
527 case EFI_MEMORY_XP:\r
528 case EFI_MEMORY_UCE:\r
529 // cannot be implemented UEFI definition unclear for ARM\r
530 // Cause a page fault if these ranges are accessed.\r
531 EntryValue = TT_DESCRIPTOR_PAGE_TYPE_FAULT;\r
532 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r
533 break;\r
534\r
535 default:\r
536 return EFI_UNSUPPORTED;\r
537 }\r
538\r
539 // Obtain page table base\r
540 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
541\r
542 // Calculate number of 4KB page table entries to change\r
543 NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;\r
544 \r
545 // Iterate for the number of 4KB pages to change\r
546 Offset = 0;\r
547 for(p = 0; p < NumPageEntries; p++) {\r
548 // Calculate index into first level translation table for page table value\r
549 \r
550 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
551 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
552\r
553 // Read the descriptor from the first level page table\r
554 Descriptor = FirstLevelTable[FirstLevelIdx];\r
555\r
556 // Does this descriptor need to be converted from section entry to 4K pages?\r
557 if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) {\r
558 Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
559 if (EFI_ERROR(Status)) {\r
560 // Exit for loop\r
561 break; \r
562 } \r
563 \r
564 // Re-read descriptor\r
565 Descriptor = FirstLevelTable[FirstLevelIdx];\r
566 }\r
567\r
568 // Obtain page table base address\r
569 PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor);\r
570\r
571 // Calculate index into the page table\r
572 PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;\r
573 ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);\r
574\r
575 // Get the entry\r
576 CurrentPageTableEntry = PageTable[PageTableIndex];\r
577\r
578 // Mask off appropriate fields\r
579 PageTableEntry = CurrentPageTableEntry & ~EntryMask;\r
580\r
581 // Mask in new attributes and/or permissions\r
582 PageTableEntry |= EntryValue;\r
583\r
584 if (VirtualMask != 0) {\r
585 // Make this virtual address point at a physical page\r
586 PageTableEntry &= ~VirtualMask;\r
587 }\r
588 \r
589 if (CurrentPageTableEntry != PageTableEntry) {\r
590 Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));\r
591 if ((CurrentPageTableEntry & TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) == TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) {\r
592 // The current section mapping is cacheable so Clean/Invalidate the MVA of the page\r
593 // Note assumes switch(Attributes), not ARMv7 possibilities\r
594 WriteBackInvalidateDataCacheRange (Mva, TT_DESCRIPTOR_PAGE_SIZE);\r
595 }\r
596\r
597 // Only need to update if we are changing the entry \r
598 PageTable[PageTableIndex] = PageTableEntry; \r
599 ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);\r
600 }\r
601\r
602 Status = EFI_SUCCESS;\r
603 Offset += TT_DESCRIPTOR_PAGE_SIZE;\r
604 \r
605 } // End first level translation table loop\r
606\r
607 return Status;\r
608}\r
609\r
610\r
611\r
612EFI_STATUS\r
613UpdateSectionEntries (\r
614 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
615 IN UINT64 Length,\r
616 IN UINT64 Attributes,\r
617 IN EFI_PHYSICAL_ADDRESS VirtualMask\r
618 )\r
619{\r
620 EFI_STATUS Status = EFI_SUCCESS;\r
621 UINT32 EntryMask;\r
622 UINT32 EntryValue;\r
623 UINT32 FirstLevelIdx;\r
624 UINT32 NumSections;\r
625 UINT32 i;\r
626 UINT32 CurrentDescriptor;\r
627 UINT32 Descriptor;\r
628 VOID *Mva;\r
629 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
630\r
631 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
632 // EntryValue: values at bit positions specified by EntryMask\r
633\r
634 // Make sure we handle a section range that is unmapped \r
635 EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK;\r
636 EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;\r
637\r
638 // Although the PI spec is unclear on this the GCD guarantees that only\r
639 // one Attribute bit is set at a time, so we can safely use a switch statement\r
640 switch(Attributes) {\r
641 case EFI_MEMORY_UC:\r
642 // modify cacheability attributes\r
643 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
644 // map to strongly ordered\r
645 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r
646 break;\r
647\r
648 case EFI_MEMORY_WC:\r
649 // modify cacheability attributes\r
650 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
651 // map to normal non-cachable\r
652 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r
653 break;\r
654\r
655 case EFI_MEMORY_WT:\r
656 // modify cacheability attributes\r
657 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
658 // write through with no-allocate\r
659 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0\r
660 break;\r
661\r
662 case EFI_MEMORY_WB:\r
663 // modify cacheability attributes\r
664 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
665 // write back (with allocate)\r
666 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1\r
667 break;\r
668\r
669 case EFI_MEMORY_WP:\r
670 case EFI_MEMORY_XP:\r
671 case EFI_MEMORY_RP:\r
672 case EFI_MEMORY_UCE:\r
673 // cannot be implemented UEFI definition unclear for ARM\r
674 // Cause a page fault if these ranges are accessed.\r
675 EntryValue = TT_DESCRIPTOR_SECTION_TYPE_FAULT;\r
676 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r
677 break;\r
678\r
679\r
680 default:\r
681 return EFI_UNSUPPORTED;\r
682 }\r
683\r
684 // obtain page table base\r
685 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
686\r
687 // calculate index into first level translation table for start of modification\r
688 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
689 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
690\r
691 // calculate number of 1MB first level entries this applies to\r
692 NumSections = Length / TT_DESCRIPTOR_SECTION_SIZE;\r
693 \r
694 // iterate through each descriptor\r
695 for(i=0; i<NumSections; i++) {\r
696 CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];\r
697\r
698 // has this descriptor already been coverted to pages?\r
699 if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor)) {\r
700 // forward this 1MB range to page table function instead\r
701 Status = UpdatePageEntries ((FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT, TT_DESCRIPTOR_SECTION_SIZE, Attributes, VirtualMask);\r
702 } else {\r
703 // still a section entry\r
704 \r
705 // mask off appropriate fields\r
706 Descriptor = CurrentDescriptor & ~EntryMask;\r
707\r
708 // mask in new attributes and/or permissions\r
709 Descriptor |= EntryValue;\r
710 if (VirtualMask != 0) {\r
711 Descriptor &= ~VirtualMask;\r
712 }\r
713\r
714 if (CurrentDescriptor != Descriptor) {\r
715 Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
716 if ((CurrentDescriptor & TT_DESCRIPTOR_SECTION_CACHEABLE_MASK) == TT_DESCRIPTOR_SECTION_CACHEABLE_MASK) {\r
717 // The current section mapping is cacheable so Clean/Invalidate the MVA of the section\r
718 // Note assumes switch(Attributes), not ARMv7 possabilities\r
719 WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);\r
720 }\r
721\r
722 // Only need to update if we are changing the descriptor \r
723 FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r
724 ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);\r
725 }\r
726\r
727 Status = EFI_SUCCESS;\r
728 }\r
729 }\r
730\r
731 return Status;\r
732}\r
733\r
734EFI_STATUS \r
735ConvertSectionToPages (\r
736 IN EFI_PHYSICAL_ADDRESS BaseAddress\r
737 )\r
738{\r
739 EFI_STATUS Status;\r
740 EFI_PHYSICAL_ADDRESS PageTableAddr;\r
741 UINT32 FirstLevelIdx;\r
742 UINT32 SectionDescriptor;\r
743 UINT32 PageTableDescriptor;\r
744 UINT32 PageDescriptor;\r
745 UINT32 Index;\r
746\r
747 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
748 volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r
749\r
750 DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));\r
751\r
752 // Obtain page table base\r
753 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
754\r
755 // Calculate index into first level translation table for start of modification\r
756 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
757 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
758\r
759 // Get section attributes and convert to page attributes\r
760 SectionDescriptor = FirstLevelTable[FirstLevelIdx];\r
761 PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE;\r
762 PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(SectionDescriptor,0);\r
763 PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(SectionDescriptor);\r
764 PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(SectionDescriptor,0);\r
765 PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(SectionDescriptor);\r
766 PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S(SectionDescriptor);\r
767\r
768 // Allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)\r
769 Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, 1, &PageTableAddr);\r
770 if (EFI_ERROR(Status)) {\r
771 return Status;\r
772 }\r
773\r
774 PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;\r
775\r
776 // Write the page table entries out\r
777 for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {\r
778 PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;\r
779 }\r
780\r
781 // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
782 WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, TT_DESCRIPTOR_PAGE_SIZE);\r
783\r
784 // Formulate page table entry, Domain=0, NS=0\r
785 PageTableDescriptor = (((UINTN)PageTableAddr) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
786\r
787 // Write the page table entry out, replacing section entry\r
788 FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;\r
789\r
790 return EFI_SUCCESS;\r
791}\r
792\r
793\r
794\r
795EFI_STATUS\r
796SetMemoryAttributes (\r
797 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
798 IN UINT64 Length,\r
799 IN UINT64 Attributes,\r
800 IN EFI_PHYSICAL_ADDRESS VirtualMask\r
801 )\r
802{\r
803 EFI_STATUS Status;\r
804 \r
805 if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {\r
806 // Is the base and length a multiple of 1 MB?\r
807 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
808 Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);\r
809 } else {\r
810 // Base and/or length is not a multiple of 1 MB\r
811 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
812 Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);\r
813 }\r
814\r
815 // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
816 // flush and invalidate pages\r
817 //TODO: Do we really need to invalidate the caches everytime we change the memory attributes ?\r
818 ArmCleanInvalidateDataCache ();\r
819\r
820 ArmInvalidateInstructionCache ();\r
821\r
822 // Invalidate all TLB entries so changes are synced\r
823 ArmInvalidateTlb ();\r
824\r
825 return Status;\r
826}\r
827\r
828\r
829/**\r
830 This function modifies the attributes for the memory region specified by BaseAddress and\r
831 Length from their current attributes to the attributes specified by Attributes.\r
832\r
833 @param This The EFI_CPU_ARCH_PROTOCOL instance.\r
834 @param BaseAddress The physical address that is the start address of a memory region.\r
835 @param Length The size in bytes of the memory region.\r
836 @param Attributes The bit mask of attributes to set for the memory region.\r
837\r
838 @retval EFI_SUCCESS The attributes were set for the memory region.\r
839 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
840 BaseAddress and Length cannot be modified.\r
841 @retval EFI_INVALID_PARAMETER Length is zero.\r
842 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
843 the memory resource range.\r
844 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
845 resource range specified by BaseAddress and Length.\r
846 The bit mask of attributes is not support for the memory resource\r
847 range specified by BaseAddress and Length.\r
848\r
849**/\r
850EFI_STATUS\r
851EFIAPI\r
852CpuSetMemoryAttributes (\r
853 IN EFI_CPU_ARCH_PROTOCOL *This,\r
854 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
855 IN UINT64 Length,\r
856 IN UINT64 Attributes\r
857 )\r
858{\r
859 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));\r
860 if ( ((BaseAddress & ~TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK) != 0) || ((Length & ~TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK) != 0)){\r
861 // minimum granularity is SIZE_4KB (4KB on ARM)\r
862 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is SIZE_4KB\n", BaseAddress, Length, Attributes));\r
863 return EFI_UNSUPPORTED;\r
864 }\r
865 \r
866 return SetMemoryAttributes (BaseAddress, Length, Attributes, 0);\r
867}\r
868\r
869\r
870\r
871//\r
872// Add a new protocol to support \r
873//\r
874\r
875EFI_STATUS\r
876EFIAPI\r
877CpuConvertPagesToUncachedVirtualAddress (\r
878 IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,\r
879 IN EFI_PHYSICAL_ADDRESS Address,\r
880 IN UINTN Length,\r
881 IN EFI_PHYSICAL_ADDRESS VirtualMask,\r
882 OUT UINT64 *Attributes OPTIONAL\r
883 )\r
884{\r
885 EFI_STATUS Status;\r
886 EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;\r
887 \r
888 \r
889 if (Attributes != NULL) {\r
890 Status = gDS->GetMemorySpaceDescriptor (Address, &GcdDescriptor);\r
891 if (!EFI_ERROR (Status)) {\r
892 *Attributes = GcdDescriptor.Attributes;\r
893 }\r
894 }\r
895\r
896 //\r
897 // Make this address range page fault if accessed. If it is a DMA buffer than this would \r
898 // be the PCI address. Code should always use the CPU address, and we will or in VirtualMask\r
899 // to that address. \r
900 //\r
901 Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_WP, 0);\r
902 if (!EFI_ERROR (Status)) {\r
903 Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask);\r
904 }\r
905\r
906 DEBUG ((DEBUG_INFO | DEBUG_LOAD, "ConvertPagesToUncachedVirtualAddress()\n Unmapped 0x%08lx Mapped 0x%08lx 0x%x bytes\n", Address, Address | VirtualMask, Length));\r
907\r
908 return Status;\r
909}\r
910\r
911\r
912EFI_STATUS\r
913EFIAPI\r
914CpuReconvertPages (\r
915 IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,\r
916 IN EFI_PHYSICAL_ADDRESS Address,\r
917 IN UINTN Length,\r
918 IN EFI_PHYSICAL_ADDRESS VirtualMask,\r
919 IN UINT64 Attributes\r
920 )\r
921{\r
922 EFI_STATUS Status;\r
923\r
924 DEBUG ((DEBUG_INFO | DEBUG_LOAD, "CpuReconvertPages(%lx, %x, %lx, %lx)\n", Address, Length, VirtualMask, Attributes));\r
925 \r
926 //\r
927 // Unmap the alaised Address\r
928 //\r
929 Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0);\r
930 if (!EFI_ERROR (Status)) {\r
931 //\r
932 // Restore atttributes\r
933 //\r
934 Status = SetMemoryAttributes (Address, Length, Attributes, 0);\r
935 }\r
936 \r
937 return Status;\r
938}\r
939\r
940\r
941VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages = {\r
942 CpuConvertPagesToUncachedVirtualAddress,\r
943 CpuReconvertPages\r
944};\r
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