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1 | /** @file\r | |
2 | *\r | |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
4 | * \r | |
5 | * This program and the accompanying materials \r | |
6 | * are licensed and made available under the terms and conditions of the BSD License \r | |
7 | * which accompanies this distribution. The full text of the license may be found at \r | |
8 | * http://opensource.org/licenses/bsd-license.php \r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #include <Library/IoLib.h>\r | |
16 | #include <Library/DebugLib.h>\r | |
17 | #include <Library/ArmLib.h>\r | |
18 | #include <Library/L2X0CacheLib.h>\r | |
19 | #include <Library/PcdLib.h>\r | |
20 | \r | |
21 | #define L2x0WriteReg(reg,val) MmioWrite32(PcdGet32(PcdL2x0ControllerBase) + reg, val)\r | |
22 | #define L2x0ReadReg(reg) MmioRead32(PcdGet32(PcdL2x0ControllerBase) + reg)\r | |
23 | \r | |
24 | // Initialize PL320 L2 Cache Controller\r | |
25 | VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled) {\r | |
26 | UINT32 Data;\r | |
27 | UINT32 Revision;\r | |
28 | UINT32 Aux;\r | |
29 | UINT32 PfCtl;\r | |
30 | UINT32 PwrCtl;\r | |
31 | \r | |
32 | // Check if L2x0 is present and is an ARM implementation\r | |
33 | Data = L2x0ReadReg(L2X0_CACHEID);\r | |
34 | if ((Data >> 24) != L2X0_CACHEID_IMPLEMENTER_ARM) {\r | |
35 | ASSERT(0);\r | |
36 | return;\r | |
37 | }\r | |
38 | \r | |
39 | // Check if L2x0 is PL310\r | |
40 | if (((Data >> 6) & 0xF) != L2X0_CACHEID_PARTNUM_PL310) {\r | |
41 | ASSERT(0);\r | |
42 | return;\r | |
43 | }\r | |
44 | \r | |
45 | // RTL release\r | |
46 | Revision = Data & 0x3F;\r | |
47 | \r | |
48 | // Check if L2x0 is already enabled then we disable it\r | |
49 | Data = L2x0ReadReg(L2X0_CTRL);\r | |
50 | if (Data & L2X0_CTRL_ENABLED) {\r | |
51 | L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_DISABLED);\r | |
52 | }\r | |
53 | \r | |
54 | //\r | |
55 | // Set up global configurations\r | |
56 | //\r | |
57 | \r | |
58 | // Auxiliary register: Non-secure interrupt access Control + Event monitor bus enable + SBO\r | |
59 | Aux = L2X0_AUXCTRL_NSAC | L2X0_AUXCTRL_EM | L2X0_AUXCTRL_SBO;\r | |
60 | // Use AWCACHE attributes for WA\r | |
61 | Aux |= L2x0_AUXCTRL_AW_AWCACHE;\r | |
62 | // Use default Size\r | |
63 | Data = L2x0ReadReg(L2X0_AUXCTRL);\r | |
64 | Aux |= Data & (0x7 << 17);\r | |
65 | // Use default associativity\r | |
66 | Aux |= Data & (0x1 << 16);\r | |
67 | // Enabled I & D Prefetch\r | |
68 | Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH;\r | |
69 | \r | |
70 | if (Revision >= 5) {\r | |
71 | // Prefetch Offset Register\r | |
72 | PfCtl = L2x0ReadReg(L2X0_PFCTRL);\r | |
73 | // - Prefetch increment set to 0\r | |
74 | // - Prefetch dropping off\r | |
75 | // - Double linefills off\r | |
76 | L2x0WriteReg(L2X0_PFCTRL, PfCtl);\r | |
77 | \r | |
78 | // Power Control Register - L2X0_PWRCTRL\r | |
79 | PwrCtl = L2x0ReadReg(L2X0_PWRCTRL);\r | |
80 | // - Standby when idle off\r | |
81 | // - Dynamic clock gating off\r | |
82 | // - Nc,NC-shared dropping off\r | |
83 | L2x0WriteReg(L2X0_PWRCTRL, PwrCtl);\r | |
84 | }\r | |
85 | \r | |
86 | if (Revision >= 4) {\r | |
87 | // Tag RAM Latency register\r | |
88 | // - Use default latency\r | |
89 | \r | |
90 | // Data RAM Latency Control register\r | |
91 | // - Use default latency\r | |
92 | } else if (Revision >= 2) {\r | |
93 | L2x0WriteReg(L230_TAG_LATENCY,\r | |
94 | (L2_TAG_ACCESS_LATENCY << 8)\r | |
95 | | (L2_TAG_ACCESS_LATENCY << 4)\r | |
96 | | L2_TAG_SETUP_LATENCY\r | |
97 | );\r | |
98 | \r | |
99 | L2x0WriteReg(L230_DATA_LATENCY,\r | |
100 | (L2_DATA_ACCESS_LATENCY << 8)\r | |
101 | | (L2_DATA_ACCESS_LATENCY << 4)\r | |
102 | | L2_DATA_SETUP_LATENCY\r | |
103 | );\r | |
104 | } else {\r | |
105 | Aux |= (L2_TAG_ACCESS_LATENCY << 6)\r | |
106 | | (L2_DATA_ACCESS_LATENCY << 3)\r | |
107 | | L2_DATA_ACCESS_LATENCY;\r | |
108 | }\r | |
109 | \r | |
110 | // Write Auxiliary value\r | |
111 | L2x0WriteReg(L2X0_AUXCTRL, Aux);\r | |
112 | \r | |
113 | //\r | |
114 | // Invalidate all entries in cache\r | |
115 | //\r | |
116 | L2x0WriteReg(L2X0_INVWAY, 0xffff);\r | |
117 | // Poll cache maintenance register until invalidate operation is complete\r | |
118 | while(L2x0ReadReg(L2X0_INVWAY) & 0xffff);\r | |
119 | \r | |
120 | // Write to the Lockdown D and Lockdown I Register 9 if required\r | |
121 | // - Not required\r | |
122 | \r | |
123 | // Clear any residual raw interrupts\r | |
124 | L2x0WriteReg(L2X0_INTCLEAR, 0x1FF);\r | |
125 | \r | |
126 | // Enable the cache\r | |
127 | if (CacheEnabled) {\r | |
128 | L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_ENABLED);\r | |
129 | }\r | |
130 | }\r |