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1 | #------------------------------------------------------------------------------\r | |
2 | #\r | |
3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
4 | # Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r | |
5 | # Copyright (c) 2016, Linaro Limited. All rights reserved.\r | |
6 | #\r | |
7 | # This program and the accompanying materials\r | |
8 | # are licensed and made available under the terms and conditions of the BSD License\r | |
9 | # which accompanies this distribution. The full text of the license may be found at\r | |
10 | # http://opensource.org/licenses/bsd-license.php\r | |
11 | #\r | |
12 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | #\r | |
15 | #------------------------------------------------------------------------------\r | |
16 | \r | |
17 | #include <AsmMacroIoLibV8.h>\r | |
18 | \r | |
19 | .set DAIF_RD_FIQ_BIT, (1 << 6)\r | |
20 | .set DAIF_RD_IRQ_BIT, (1 << 7)\r | |
21 | \r | |
22 | ASM_FUNC(ArmReadMidr)\r | |
23 | mrs x0, midr_el1 // Read from Main ID Register (MIDR)\r | |
24 | ret\r | |
25 | \r | |
26 | ASM_FUNC(ArmCacheInfo)\r | |
27 | mrs x0, ctr_el0 // Read from Cache Type Regiter (CTR)\r | |
28 | ret\r | |
29 | \r | |
30 | ASM_FUNC(ArmGetInterruptState)\r | |
31 | mrs x0, daif\r | |
32 | tst w0, #DAIF_RD_IRQ_BIT // Check if IRQ is enabled. Enabled if 0 (Z=1)\r | |
33 | cset w0, eq // if Z=1 return 1, else 0\r | |
34 | ret\r | |
35 | \r | |
36 | ASM_FUNC(ArmGetFiqState)\r | |
37 | mrs x0, daif\r | |
38 | tst w0, #DAIF_RD_FIQ_BIT // Check if FIQ is enabled. Enabled if 0 (Z=1)\r | |
39 | cset w0, eq // if Z=1 return 1, else 0\r | |
40 | ret\r | |
41 | \r | |
42 | ASM_FUNC(ArmWriteCpacr)\r | |
43 | msr cpacr_el1, x0 // Coprocessor Access Control Reg (CPACR)\r | |
44 | ret\r | |
45 | \r | |
46 | ASM_FUNC(ArmWriteAuxCr)\r | |
47 | EL1_OR_EL2(x1)\r | |
48 | 1:msr actlr_el1, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r | |
49 | ret\r | |
50 | 2:msr actlr_el2, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r | |
51 | ret\r | |
52 | \r | |
53 | ASM_FUNC(ArmReadAuxCr)\r | |
54 | EL1_OR_EL2(x1)\r | |
55 | 1:mrs x0, actlr_el1 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r | |
56 | ret\r | |
57 | 2:mrs x0, actlr_el2 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r | |
58 | ret\r | |
59 | \r | |
60 | ASM_FUNC(ArmSetTTBR0)\r | |
61 | EL1_OR_EL2_OR_EL3(x1)\r | |
62 | 1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0)\r | |
63 | b 4f\r | |
64 | 2:msr ttbr0_el2, x0 // Translation Table Base Reg 0 (TTBR0)\r | |
65 | b 4f\r | |
66 | 3:msr ttbr0_el3, x0 // Translation Table Base Reg 0 (TTBR0)\r | |
67 | 4:isb\r | |
68 | ret\r | |
69 | \r | |
70 | ASM_FUNC(ArmGetTTBR0BaseAddress)\r | |
71 | EL1_OR_EL2(x1)\r | |
72 | 1:mrs x0, ttbr0_el1\r | |
73 | b 3f\r | |
74 | 2:mrs x0, ttbr0_el2\r | |
75 | 3:and x0, x0, 0xFFFFFFFFFFFF /* Look at bottom 48 bits */\r | |
76 | isb\r | |
77 | ret\r | |
78 | \r | |
79 | ASM_FUNC(ArmGetTCR)\r | |
80 | EL1_OR_EL2_OR_EL3(x1)\r | |
81 | 1:mrs x0, tcr_el1\r | |
82 | b 4f\r | |
83 | 2:mrs x0, tcr_el2\r | |
84 | b 4f\r | |
85 | 3:mrs x0, tcr_el3\r | |
86 | 4:isb\r | |
87 | ret\r | |
88 | \r | |
89 | ASM_FUNC(ArmSetTCR)\r | |
90 | EL1_OR_EL2_OR_EL3(x1)\r | |
91 | 1:msr tcr_el1, x0\r | |
92 | b 4f\r | |
93 | 2:msr tcr_el2, x0\r | |
94 | b 4f\r | |
95 | 3:msr tcr_el3, x0\r | |
96 | 4:isb\r | |
97 | ret\r | |
98 | \r | |
99 | ASM_FUNC(ArmGetMAIR)\r | |
100 | EL1_OR_EL2_OR_EL3(x1)\r | |
101 | 1:mrs x0, mair_el1\r | |
102 | b 4f\r | |
103 | 2:mrs x0, mair_el2\r | |
104 | b 4f\r | |
105 | 3:mrs x0, mair_el3\r | |
106 | 4:isb\r | |
107 | ret\r | |
108 | \r | |
109 | ASM_FUNC(ArmSetMAIR)\r | |
110 | EL1_OR_EL2_OR_EL3(x1)\r | |
111 | 1:msr mair_el1, x0\r | |
112 | b 4f\r | |
113 | 2:msr mair_el2, x0\r | |
114 | b 4f\r | |
115 | 3:msr mair_el3, x0\r | |
116 | 4:isb\r | |
117 | ret\r | |
118 | \r | |
119 | \r | |
120 | //\r | |
121 | //VOID\r | |
122 | //ArmUpdateTranslationTableEntry (\r | |
123 | // IN VOID *TranslationTableEntry // X0\r | |
124 | // IN VOID *MVA // X1\r | |
125 | // );\r | |
126 | ASM_FUNC(ArmUpdateTranslationTableEntry)\r | |
127 | dc civac, x0 // Clean and invalidate data line\r | |
128 | dsb sy\r | |
129 | EL1_OR_EL2_OR_EL3(x0)\r | |
130 | 1: tlbi vaae1, x1 // TLB Invalidate VA , EL1\r | |
131 | b 4f\r | |
132 | 2: tlbi vae2, x1 // TLB Invalidate VA , EL2\r | |
133 | b 4f\r | |
134 | 3: tlbi vae3, x1 // TLB Invalidate VA , EL3\r | |
135 | 4: dsb sy\r | |
136 | isb\r | |
137 | ret\r | |
138 | \r | |
139 | ASM_FUNC(ArmInvalidateTlb)\r | |
140 | EL1_OR_EL2_OR_EL3(x0)\r | |
141 | 1: tlbi vmalle1\r | |
142 | b 4f\r | |
143 | 2: tlbi alle2\r | |
144 | b 4f\r | |
145 | 3: tlbi alle3\r | |
146 | 4: dsb sy\r | |
147 | isb\r | |
148 | ret\r | |
149 | \r | |
150 | ASM_FUNC(ArmWriteCptr)\r | |
151 | msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR)\r | |
152 | ret\r | |
153 | \r | |
154 | ASM_FUNC(ArmWriteScr)\r | |
155 | msr scr_el3, x0 // Secure configuration register EL3\r | |
156 | isb\r | |
157 | ret\r | |
158 | \r | |
159 | ASM_FUNC(ArmWriteMVBar)\r | |
160 | msr vbar_el3, x0 // Exception Vector Base address for Monitor on EL3\r | |
161 | ret\r | |
162 | \r | |
163 | ASM_FUNC(ArmCallWFE)\r | |
164 | wfe\r | |
165 | ret\r | |
166 | \r | |
167 | ASM_FUNC(ArmCallSEV)\r | |
168 | sev\r | |
169 | ret\r | |
170 | \r | |
171 | ASM_FUNC(ArmReadCpuActlr)\r | |
172 | mrs x0, S3_1_c15_c2_0\r | |
173 | ret\r | |
174 | \r | |
175 | ASM_FUNC(ArmWriteCpuActlr)\r | |
176 | msr S3_1_c15_c2_0, x0\r | |
177 | dsb sy\r | |
178 | isb\r | |
179 | ret\r | |
180 | \r | |
181 | ASM_FUNC(ArmReadSctlr)\r | |
182 | EL1_OR_EL2_OR_EL3(x1)\r | |
183 | 1:mrs x0, sctlr_el1\r | |
184 | ret\r | |
185 | 2:mrs x0, sctlr_el2\r | |
186 | ret\r | |
187 | 3:mrs x0, sctlr_el3\r | |
188 | 4:ret\r | |
189 | \r | |
190 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |