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1 | #------------------------------------------------------------------------------ | |
2 | # | |
3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> | |
4 | # | |
5 | # This program and the accompanying materials | |
6 | # are licensed and made available under the terms and conditions of the BSD License | |
7 | # which accompanies this distribution. The full text of the license may be found at | |
8 | # http://opensource.org/licenses/bsd-license.php | |
9 | # | |
10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | # | |
13 | #------------------------------------------------------------------------------ | |
14 | ||
15 | .text | |
16 | .align 2 | |
17 | GCC_ASM_EXPORT(ArmCleanInvalidateDataCache) | |
18 | GCC_ASM_EXPORT(ArmCleanDataCache) | |
19 | GCC_ASM_EXPORT(ArmInvalidateDataCache) | |
20 | GCC_ASM_EXPORT(ArmInvalidateInstructionCache) | |
21 | GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA) | |
22 | GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA) | |
23 | GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA) | |
24 | GCC_ASM_EXPORT(ArmEnableMmu) | |
25 | GCC_ASM_EXPORT(ArmDisableMmu) | |
26 | GCC_ASM_EXPORT(ArmMmuEnabled) | |
27 | GCC_ASM_EXPORT(ArmEnableDataCache) | |
28 | GCC_ASM_EXPORT(ArmDisableDataCache) | |
29 | GCC_ASM_EXPORT(ArmEnableInstructionCache) | |
30 | GCC_ASM_EXPORT(ArmDisableInstructionCache) | |
31 | GCC_ASM_EXPORT(ArmEnableBranchPrediction) | |
32 | GCC_ASM_EXPORT(ArmDisableBranchPrediction) | |
33 | GCC_ASM_EXPORT(ArmDataMemoryBarrier) | |
34 | GCC_ASM_EXPORT(ArmDataSyncronizationBarrier) | |
35 | GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier) | |
36 | ||
37 | ||
38 | .set DC_ON, (1<<2) | |
39 | .set IC_ON, (1<<12) | |
40 | ||
41 | #------------------------------------------------------------------------------ | |
42 | ||
43 | ASM_PFX(ArmInvalidateDataCacheEntryByMVA): | |
44 | mcr p15, 0, r0, c7, c6, 1 @ invalidate single data cache line | |
45 | bx lr | |
46 | ||
47 | ASM_PFX(ArmCleanDataCacheEntryByMVA): | |
48 | mcr p15, 0, r0, c7, c10, 1 @ clean single data cache line | |
49 | bx lr | |
50 | ||
51 | ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): | |
52 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate single data cache line | |
53 | bx lr | |
54 | ||
55 | ASM_PFX(ArmEnableInstructionCache): | |
56 | ldr r1,=IC_ON | |
57 | mrc p15,0,r0,c1,c0,0 @Read control register configuration data | |
58 | orr r0,r0,r1 @Set I bit | |
59 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
60 | bx LR | |
61 | \s\s | |
62 | ASM_PFX(ArmDisableInstructionCache): | |
63 | ldr r1,=IC_ON | |
64 | mrc p15,0,r0,c1,c0,0 @Read control register configuration data | |
65 | bic r0,r0,r1 @Clear I bit. | |
66 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
67 | bx LR | |
68 | \s\s | |
69 | ASM_PFX(ArmInvalidateInstructionCache): | |
70 | mov r0,#0 | |
71 | mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache. | |
72 | \s\s @Also flushes the branch target cache. | |
73 | mov r0,#0 | |
74 | mcr p15,0,r0,c7,c10,4 @Data write buffer | |
75 | bx LR | |
76 | ||
77 | ASM_PFX(ArmEnableMmu): | |
78 | mrc p15,0,R0,c1,c0,0 | |
79 | orr R0,R0,#1 | |
80 | mcr p15,0,R0,c1,c0,0 | |
81 | bx LR | |
82 | ||
83 | ASM_PFX(ArmMmuEnabled): | |
84 | mrc p15,0,R0,c1,c0,0 | |
85 | and R0,R0,#1 | |
86 | bx LR | |
87 | ||
88 | ASM_PFX(ArmDisableMmu): | |
89 | mrc p15,0,R0,c1,c0,0 | |
90 | bic R0,R0,#1 | |
91 | mcr p15,0,R0,c1,c0,0 | |
92 | mov R0,#0 | |
93 | mcr p15,0,R0,c7,c10,4 @Drain write buffer | |
94 | bx LR | |
95 | ||
96 | ASM_PFX(ArmEnableDataCache): | |
97 | ldr R1,=DC_ON | |
98 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data | |
99 | orr R0,R0,R1 @Set C bit | |
100 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
101 | bx LR | |
102 | \s\s | |
103 | ASM_PFX(ArmDisableDataCache): | |
104 | ldr R1,=DC_ON | |
105 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data | |
106 | bic R0,R0,R1 @Clear C bit | |
107 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
108 | bx LR | |
109 | ||
110 | ASM_PFX(ArmCleanDataCache): | |
111 | mrc p15,0,r15,c7,c10,3 | |
112 | bne ASM_PFX(ArmCleanDataCache) | |
113 | mov R0,#0 | |
114 | mcr p15,0,R0,c7,c10,4\s\s@Drain write buffer | |
115 | bx LR | |
116 | ||
117 | ASM_PFX(ArmInvalidateDataCache): | |
118 | mov R0,#0 | |
119 | mcr p15,0,R0,c7,c6,0 @Invalidate entire data cache | |
120 | mov R0,#0 | |
121 | mcr p15,0,R0,c7,c10,4 @Drain write buffer | |
122 | bx LR | |
123 | ||
124 | ASM_PFX(ArmCleanInvalidateDataCache): | |
125 | mrc p15,0,r15,c7,c14,3 | |
126 | bne ASM_PFX(ArmCleanInvalidateDataCache) | |
127 | mov R0,#0 | |
128 | mcr p15,0,R0,c7,c10,4\s\s @Drain write buffer | |
129 | bx LR | |
130 | ||
131 | ASM_PFX(ArmEnableBranchPrediction): | |
132 | bx LR @Branch prediction is not supported. | |
133 | ||
134 | ASM_PFX(ArmDisableBranchPrediction): | |
135 | bx LR @Branch prediction is not supported. | |
136 | ||
137 | ASM_PFX(ArmDataMemoryBarrier): | |
138 | mov R0, #0 | |
139 | mcr P15, #0, R0, C7, C10, #5 @ check if this is OK? | |
140 | bx LR | |
141 | ||
142 | ASM_PFX(ArmDataSyncronizationBarrier): | |
143 | mov R0, #0 | |
144 | mcr P15, #0, R0, C7, C10, #4 @ check if this is OK? | |
145 | bx LR | |
146 | ||
147 | ASM_PFX(ArmInstructionSynchronizationBarrier): | |
148 | mov R0, #0 | |
149 | mcr P15, #0, R0, C7, C5, #4 @ check if this is OK? | |
150 | bx LR | |
151 | ||
152 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED | |
153 |