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1 | //------------------------------------------------------------------------------ | |
2 | // | |
3 | // Copyright (c) 2008-2010 Apple Inc. All rights reserved. | |
4 | // | |
5 | // All rights reserved. This program and the accompanying materials | |
6 | // are licensed and made available under the terms and conditions of the BSD License | |
7 | // which accompanies this distribution. The full text of the license may be found at | |
8 | // http://opensource.org/licenses/bsd-license.php | |
9 | // | |
10 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | // | |
13 | //------------------------------------------------------------------------------ | |
14 | ||
15 | ||
16 | EXPORT Cp15IdCode | |
17 | EXPORT Cp15CacheInfo | |
18 | EXPORT ArmEnableInterrupts | |
19 | EXPORT ArmDisableInterrupts | |
20 | EXPORT ArmGetInterruptState | |
21 | EXPORT ArmEnableFiq | |
22 | EXPORT ArmDisableFiq | |
23 | EXPORT ArmGetFiqState | |
24 | EXPORT ArmInvalidateTlb | |
25 | EXPORT ArmSetTranslationTableBaseAddress | |
26 | EXPORT ArmGetTranslationTableBaseAddress | |
27 | EXPORT ArmSetDomainAccessControl | |
28 | EXPORT ArmUpdateTranslationTableEntry | |
29 | EXPORT CPSRMaskInsert | |
30 | EXPORT CPSRRead | |
31 | EXPORT ReadCCSIDR | |
32 | EXPORT ReadCLIDR | |
33 | ||
34 | AREA ArmLibSupport, CODE, READONLY | |
35 | ||
36 | ||
37 | //------------------------------------------------------------------------------ | |
38 | ||
39 | Cp15IdCode | |
40 | mrc p15,0,R0,c0,c0,0 | |
41 | bx LR | |
42 | ||
43 | Cp15CacheInfo | |
44 | mrc p15,0,R0,c0,c0,1 | |
45 | bx LR | |
46 | ||
47 | ArmEnableInterrupts | |
48 | cpsie i | |
49 | bx LR | |
50 | ||
51 | ArmDisableInterrupts | |
52 | cpsid i | |
53 | bx LR | |
54 | ||
55 | ArmGetInterruptState | |
56 | mrs R0,CPSR | |
57 | tst R0,#0x80 ;Check if IRQ is enabled. | |
58 | moveq R0,#1 | |
59 | movne R0,#0 | |
60 | bx LR | |
61 | ||
62 | ArmEnableFiq | |
63 | cpsie f | |
64 | bx LR | |
65 | ||
66 | ArmDisableFiq | |
67 | cpsid f | |
68 | bx LR | |
69 | ||
70 | ArmGetFiqState | |
71 | mrs R0,CPSR | |
72 | tst R0,#0x40 ;Check if FIQ is enabled. | |
73 | moveq R0,#1 | |
74 | movne R0,#0 | |
75 | bx LR | |
76 | ||
77 | ArmInvalidateTlb | |
78 | mov r0,#0 | |
79 | mcr p15,0,r0,c8,c7,0 | |
80 | mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp | |
81 | dsb | |
82 | isb | |
83 | bx lr | |
84 | ||
85 | ArmSetTranslationTableBaseAddress | |
86 | mcr p15,0,r0,c2,c0,0 | |
87 | isb | |
88 | bx lr | |
89 | ||
90 | ArmGetTranslationTableBaseAddress | |
91 | mrc p15,0,r0,c2,c0,0 | |
92 | isb | |
93 | bx lr | |
94 | ||
95 | ||
96 | ArmSetDomainAccessControl | |
97 | mcr p15,0,r0,c3,c0,0 | |
98 | isb | |
99 | bx lr | |
100 | ||
101 | // | |
102 | //VOID | |
103 | //ArmUpdateTranslationTableEntry ( | |
104 | // IN VOID *TranslationTableEntry // R0 | |
105 | // IN VOID *MVA // R1 | |
106 | // ); | |
107 | ArmUpdateTranslationTableEntry | |
108 | mcr p15,0,R0,c7,c14,1 ; DCCIMVAC Clean data cache by MVA | |
109 | dsb | |
110 | mcr p15,0,R1,c8,c7,1 ; TLBIMVA TLB Invalidate MVA | |
111 | mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp | |
112 | dsb | |
113 | isb | |
114 | bx lr | |
115 | ||
116 | CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert | |
117 | stmfd sp!, {r4-r12, lr} ; save all the banked registers | |
118 | mov r3, sp ; copy the stack pointer into a non-banked register | |
119 | mrs r2, cpsr ; read the cpsr | |
120 | bic r2, r2, r0 ; clear mask in the cpsr | |
121 | and r1, r1, r0 ; clear bits outside the mask in the input | |
122 | orr r2, r2, r1 ; set field | |
123 | msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch) | |
124 | isb | |
125 | mov sp, r3 ; restore stack pointer | |
126 | ldmfd sp!, {r4-r12, lr} ; restore registers | |
127 | bx lr ; return (hopefully thumb-safe!) | |
128 | ||
129 | CPSRRead | |
130 | mrs r0, cpsr | |
131 | bx lr | |
132 | ||
133 | ||
134 | // UINT32 | |
135 | // ReadCCSIDR ( | |
136 | // IN UINT32 CSSELR | |
137 | // ) | |
138 | ReadCCSIDR | |
139 | mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR) | |
140 | isb | |
141 | mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR) | |
142 | bx lr | |
143 | ||
144 | ||
145 | // UINT32 | |
146 | // ReadCLIDR ( | |
147 | // IN UINT32 CSSELR | |
148 | // ) | |
149 | ReadCLIDR | |
150 | mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register | |
151 | bx lr | |
152 | ||
153 | ||
154 | END | |
155 | ||
156 |