[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.asm

//------------------------------------------------------------------------------ 
//
// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution.  The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------

    EXPORT  ArmInvalidateInstructionCache
    EXPORT  ArmInvalidateDataCacheEntryByMVA
    EXPORT  ArmCleanDataCacheEntryByMVA
    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
    EXPORT  ArmInvalidateDataCacheEntryBySetWay
    EXPORT  ArmCleanDataCacheEntryBySetWay
    EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay
    EXPORT  ArmDrainWriteBuffer
    EXPORT  ArmEnableMmu
    EXPORT  ArmDisableMmu
    EXPORT  ArmMmuEnabled
    EXPORT  ArmEnableDataCache
    EXPORT  ArmDisableDataCache
    EXPORT  ArmEnableInstructionCache
    EXPORT  ArmDisableInstructionCache
    EXPORT  ArmEnableBranchPrediction
    EXPORT  ArmDisableBranchPrediction

DC_ON       EQU     ( 0x1:SHL:2 )
IC_ON       EQU     ( 0x1:SHL:12 )
XP_ON       EQU     ( 0x1:SHL:23 )


    AREA    ArmCacheLib, CODE, READONLY
    PRESERVE8


ArmInvalidateDataCacheEntryByMVA
  DSB
  ISB
  MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line                                           
  DSB
  ISB
  BX      lr


ArmCleanDataCacheEntryByMVA
  DSB
  ISB
  MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line     
  DSB
  ISB
  BX      lr


ArmCleanInvalidateDataCacheEntryByMVA
  DSB
  ISB
  MCR     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  DSB
  ISB
  BX      lr


ArmInvalidateDataCacheEntryBySetWay
  DSB
  ISB
  mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line		
  DSB
  ISB
  bx      lr


ArmCleanInvalidateDataCacheEntryBySetWay
  DSB
  ISB
  mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line		
  DSB
  ISB
  bx      lr


ArmCleanDataCacheEntryBySetWay
  DSB
  ISB
  mcr     p15, 0, r0, c7, c10, 2       ; Clean this line		
  DSB
  ISB
  bx      lr


ArmDrainWriteBuffer
  DSB
  ISB
  mcr     p15, 0, r0, c7, c10, 4       ; Drain write buffer for sync
  DSB
  ISB
  bx      lr


ArmInvalidateInstructionCache
  DSB
  ISB
  MOV     R0,#0
  MCR     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
  MOV     R0,#0
  MCR     p15,0,R0,c7,c5,4      ;Instruction synchronization barrier
  DSB
  ISB
  BX      LR

ArmEnableMmu
  DSB
  ISB
  mrc     p15,0,R0,c1,c0,0
  orr     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0
  DSB
  ISB
  bx      LR

ArmMmuEnabled
  DSB
  ISB
  mrc     p15,0,R0,c1,c0,0
  and     R0,R0,#1
  DSB
  ISB
  bx      LR

ArmDisableMmu
  DSB
  ISB
  mov     R0,#0
  mcr     p15,0,R0,c13,c0,0     ;FCSE PID register must be cleared before disabling MMU
  mrc     p15,0,R0,c1,c0,0
  bic     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0      ;Disable MMU
  mov     R0,#0
  mcr     p15,0,R0,c7,c10,4     ;Data synchronization barrier
  mov     R0,#0
  mcr     p15,0,R0,c7,c5,4      ;Instruction synchronization barrier
  DSB
  ISB
  bx      LR

ArmEnableDataCache
  DSB
  ISB
  LDR     R1,=DC_ON
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  ORR     R0,R0,R1              ;Set C bit
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  DSB
  ISB
  BX      LR
    
ArmDisableDataCache
  DSB
  ISB
  LDR     R1,=DC_ON
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  BIC     R0,R0,R1              ;Clear C bit
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  DSB
  ISB
  BX      LR

ArmEnableInstructionCache
  DSB
  ISB
  LDR     R1,=IC_ON
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  ORR     R0,R0,R1              ;Set I bit
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  DSB
  ISB
  BX      LR
  
ArmDisableInstructionCache
  DSB
  ISB
  LDR     R1,=IC_ON
  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
  BIC     R0,R0,R1             ;Clear I bit.
  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
  DSB
  ISB
  BX      LR

ArmEnableBranchPrediction
  DSB
  ISB
  mrc     p15, 0, r0, c1, c0, 0
  orr     r0, r0, #0x00000800
  mcr     p15, 0, r0, c1, c0, 0
  DSB
  ISB
  bx      LR

ArmDisableBranchPrediction
  DSB
  ISB
  mrc     p15, 0, r0, c1, c0, 0
  bic     r0, r0, #0x00000800
  mcr     p15, 0, r0, c1, c0, 0
  DSB
  ISB
  bx      LR

    END
Commit	Line	Data
	1	//------------------------------------------------------------------------------
	2	//
	3	// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
	4	//
	5	// All rights reserved. This program and the accompanying materials
	6	// are licensed and made available under the terms and conditions of the BSD License
	7	// which accompanies this distribution. The full text of the license may be found at
	8	// http://opensource.org/licenses/bsd-license.php
	9	//
	10	// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
	11	// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
	12	//
	13	//------------------------------------------------------------------------------
	14
	15	EXPORT ArmInvalidateInstructionCache
	16	EXPORT ArmInvalidateDataCacheEntryByMVA
	17	EXPORT ArmCleanDataCacheEntryByMVA
	18	EXPORT ArmCleanInvalidateDataCacheEntryByMVA
	19	EXPORT ArmInvalidateDataCacheEntryBySetWay
	20	EXPORT ArmCleanDataCacheEntryBySetWay
	21	EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
	22	EXPORT ArmDrainWriteBuffer
	23	EXPORT ArmEnableMmu
	24	EXPORT ArmDisableMmu
	25	EXPORT ArmMmuEnabled
	26	EXPORT ArmEnableDataCache
	27	EXPORT ArmDisableDataCache
	28	EXPORT ArmEnableInstructionCache
	29	EXPORT ArmDisableInstructionCache
	30	EXPORT ArmEnableBranchPrediction
	31	EXPORT ArmDisableBranchPrediction
	32
	33	DC_ON EQU ( 0x1:SHL:2 )
	34	IC_ON EQU ( 0x1:SHL:12 )
	35	XP_ON EQU ( 0x1:SHL:23 )
	36
	37
	38	AREA ArmCacheLib, CODE, READONLY
	39	PRESERVE8
	40
	41
	42	ArmInvalidateDataCacheEntryByMVA
	43	DSB
	44	ISB
	45	MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
	46	DSB
	47	ISB
	48	BX lr
	49
	50
	51	ArmCleanDataCacheEntryByMVA
	52	DSB
	53	ISB
	54	MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
	55	DSB
	56	ISB
	57	BX lr
	58
	59
	60	ArmCleanInvalidateDataCacheEntryByMVA
	61	DSB
	62	ISB
	63	MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
	64	DSB
	65	ISB
	66	BX lr
	67
	68
	69	ArmInvalidateDataCacheEntryBySetWay
	70	DSB
	71	ISB
	72	mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
	73	DSB
	74	ISB
	75	bx lr
	76
	77
	78	ArmCleanInvalidateDataCacheEntryBySetWay
	79	DSB
	80	ISB
	81	mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
	82	DSB
	83	ISB
	84	bx lr
	85
	86
	87	ArmCleanDataCacheEntryBySetWay
	88	DSB
	89	ISB
	90	mcr p15, 0, r0, c7, c10, 2 ; Clean this line
	91	DSB
	92	ISB
	93	bx lr
	94
	95
	96	ArmDrainWriteBuffer
	97	DSB
	98	ISB
	99	mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
	100	DSB
	101	ISB
	102	bx lr
	103
	104
	105	ArmInvalidateInstructionCache
	106	DSB
	107	ISB
	108	MOV R0,#0
	109	MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
	110	MOV R0,#0
	111	MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
	112	DSB
	113	ISB
	114	BX LR
	115
	116	ArmEnableMmu
	117	DSB
	118	ISB
	119	mrc p15,0,R0,c1,c0,0
	120	orr R0,R0,#1
	121	mcr p15,0,R0,c1,c0,0
	122	DSB
	123	ISB
	124	bx LR
	125
	126	ArmMmuEnabled
	127	DSB
	128	ISB
	129	mrc p15,0,R0,c1,c0,0
	130	and R0,R0,#1
	131	DSB
	132	ISB
	133	bx LR
	134
	135	ArmDisableMmu
	136	DSB
	137	ISB
	138	mov R0,#0
	139	mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
	140	mrc p15,0,R0,c1,c0,0
	141	bic R0,R0,#1
	142	mcr p15,0,R0,c1,c0,0 ;Disable MMU
	143	mov R0,#0
	144	mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
	145	mov R0,#0
	146	mcr p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
	147	DSB
	148	ISB
	149	bx LR
	150
	151	ArmEnableDataCache
	152	DSB
	153	ISB
	154	LDR R1,=DC_ON
	155	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	156	ORR R0,R0,R1 ;Set C bit
	157	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
	158	DSB
	159	ISB
	160	BX LR
	161
	162	ArmDisableDataCache
	163	DSB
	164	ISB
	165	LDR R1,=DC_ON
	166	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	167	BIC R0,R0,R1 ;Clear C bit
	168	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
	169	DSB
	170	ISB
	171	BX LR
	172
	173	ArmEnableInstructionCache
	174	DSB
	175	ISB
	176	LDR R1,=IC_ON
	177	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	178	ORR R0,R0,R1 ;Set I bit
	179	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
	180	DSB
	181	ISB
	182	BX LR
	183
	184	ArmDisableInstructionCache
	185	DSB
	186	ISB
	187	LDR R1,=IC_ON
	188	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	189	BIC R0,R0,R1 ;Clear I bit.
	190	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
	191	DSB
	192	ISB
	193	BX LR
	194
	195	ArmEnableBranchPrediction
	196	DSB
	197	ISB
	198	mrc p15, 0, r0, c1, c0, 0
	199	orr r0, r0, #0x00000800
	200	mcr p15, 0, r0, c1, c0, 0
	201	DSB
	202	ISB
	203	bx LR
	204
	205	ArmDisableBranchPrediction
	206	DSB
	207	ISB
	208	mrc p15, 0, r0, c1, c0, 0
	209	bic r0, r0, #0x00000800
	210	mcr p15, 0, r0, c1, c0, 0
	211	DSB
	212	ISB
	213	bx LR
	214
	215	END