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ArmPkg: update RVCT assembly functions to use new RVCT_ASM_EXPORT macro
[mirror_edk2.git] / ArmPkg / Library / ArmLib / Common / Arm / ArmLibSupport.asm
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1//------------------------------------------------------------------------------\r
2//\r
3// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
4// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
5//\r
6// This program and the accompanying materials\r
7// are licensed and made available under the terms and conditions of the BSD License\r
8// which accompanies this distribution. The full text of the license may be found at\r
9// http://opensource.org/licenses/bsd-license.php\r
10//\r
11// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13//\r
14//------------------------------------------------------------------------------\r
15\r
16#include <AsmMacroIoLib.h>\r
17\r
18 INCLUDE AsmMacroIoLib.inc\r
19\r
20\r
21 INCLUDE AsmMacroExport.inc\r
22\r
23 RVCT_ASM_EXPORT ArmReadMidr\r
24 mrc p15,0,R0,c0,c0,0\r
25 bx LR\r
26\r
27 RVCT_ASM_EXPORT ArmCacheInfo\r
28 mrc p15,0,R0,c0,c0,1\r
29 bx LR\r
30\r
31 RVCT_ASM_EXPORT ArmGetInterruptState\r
32 mrs R0,CPSR\r
33 tst R0,#0x80 // Check if IRQ is enabled.\r
34 moveq R0,#1\r
35 movne R0,#0\r
36 bx LR\r
37\r
38 RVCT_ASM_EXPORT ArmGetFiqState\r
39 mrs R0,CPSR\r
40 tst R0,#0x40 // Check if FIQ is enabled.\r
41 moveq R0,#1\r
42 movne R0,#0\r
43 bx LR\r
44\r
45 RVCT_ASM_EXPORT ArmSetDomainAccessControl\r
46 mcr p15,0,r0,c3,c0,0\r
47 bx lr\r
48\r
49 RVCT_ASM_EXPORT CPSRMaskInsert\r
50 stmfd sp!, {r4-r12, lr} // save all the banked registers\r
51 mov r3, sp // copy the stack pointer into a non-banked register\r
52 mrs r2, cpsr // read the cpsr\r
53 bic r2, r2, r0 // clear mask in the cpsr\r
54 and r1, r1, r0 // clear bits outside the mask in the input\r
55 orr r2, r2, r1 // set field\r
56 msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)\r
57 isb\r
58 mov sp, r3 // restore stack pointer\r
59 ldmfd sp!, {r4-r12, lr} // restore registers\r
60 bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)\r
61\r
62 RVCT_ASM_EXPORT CPSRRead\r
63 mrs r0, cpsr\r
64 bx lr\r
65\r
66 RVCT_ASM_EXPORT ArmReadCpacr\r
67 mrc p15, 0, r0, c1, c0, 2\r
68 bx lr\r
69\r
70 RVCT_ASM_EXPORT ArmWriteCpacr\r
71 mcr p15, 0, r0, c1, c0, 2\r
72 isb\r
73 bx lr\r
74\r
75 RVCT_ASM_EXPORT ArmWriteAuxCr\r
76 mcr p15, 0, r0, c1, c0, 1\r
77 bx lr\r
78\r
79 RVCT_ASM_EXPORT ArmReadAuxCr\r
80 mrc p15, 0, r0, c1, c0, 1\r
81 bx lr\r
82\r
83 RVCT_ASM_EXPORT ArmSetTTBR0\r
84 mcr p15,0,r0,c2,c0,0\r
85 isb\r
86 bx lr\r
87\r
88 RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress\r
89 mrc p15,0,r0,c2,c0,0\r
90 LoadConstantToReg(0xFFFFC000, r1)\r
91 and r0, r0, r1\r
92 isb\r
93 bx lr\r
94\r
95//\r
96//VOID\r
97//ArmUpdateTranslationTableEntry (\r
98// IN VOID *TranslationTableEntry // R0\r
99// IN VOID *MVA // R1\r
100// );\r
101 RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry\r
102 mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA\r
103 dsb\r
104 mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA\r
105 mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r
106 dsb\r
107 isb\r
108 bx lr\r
109\r
110 RVCT_ASM_EXPORT ArmInvalidateTlb\r
111 mov r0,#0\r
112 mcr p15,0,r0,c8,c7,0\r
113 mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r
114 dsb\r
115 isb\r
116 bx lr\r
117\r
118 RVCT_ASM_EXPORT ArmReadScr\r
119 mrc p15, 0, r0, c1, c1, 0\r
120 bx lr\r
121\r
122 RVCT_ASM_EXPORT ArmWriteScr\r
123 mcr p15, 0, r0, c1, c1, 0\r
124 bx lr\r
125\r
126 RVCT_ASM_EXPORT ArmReadHVBar\r
127 mrc p15, 4, r0, c12, c0, 0\r
128 bx lr\r
129\r
130 RVCT_ASM_EXPORT ArmWriteHVBar\r
131 mcr p15, 4, r0, c12, c0, 0\r
132 bx lr\r
133\r
134 RVCT_ASM_EXPORT ArmReadMVBar\r
135 mrc p15, 0, r0, c12, c0, 1\r
136 bx lr\r
137\r
138 RVCT_ASM_EXPORT ArmWriteMVBar\r
139 mcr p15, 0, r0, c12, c0, 1\r
140 bx lr\r
141\r
142 RVCT_ASM_EXPORT ArmCallWFE\r
143 wfe\r
144 bx lr\r
145\r
146 RVCT_ASM_EXPORT ArmCallSEV\r
147 sev\r
148 bx lr\r
149\r
150 RVCT_ASM_EXPORT ArmReadSctlr\r
151 mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data)\r
152 bx lr\r
153\r
154\r
155 RVCT_ASM_EXPORT ArmReadCpuActlr\r
156 mrc p15, 0, r0, c1, c0, 1\r
157 bx lr\r
158\r
159 RVCT_ASM_EXPORT ArmWriteCpuActlr\r
160 mcr p15, 0, r0, c1, c0, 1\r
161 dsb\r
162 isb\r
163 bx lr\r
164\r
165 END\r