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1 | //------------------------------------------------------------------------------ | |
2 | // | |
3 | // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> | |
4 | // | |
5 | // This program and the accompanying materials | |
6 | // are licensed and made available under the terms and conditions of the BSD License | |
7 | // which accompanies this distribution. The full text of the license may be found at | |
8 | // http://opensource.org/licenses/bsd-license.php | |
9 | // | |
10 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | // | |
13 | //------------------------------------------------------------------------------ | |
14 | ||
15 | #include <AsmMacroIoLib.h> | |
16 | ||
17 | INCLUDE AsmMacroIoLib.inc | |
18 | ||
19 | EXPORT Cp15IdCode | |
20 | EXPORT Cp15CacheInfo | |
21 | EXPORT ArmIsMPCore | |
22 | EXPORT ArmEnableInterrupts | |
23 | EXPORT ArmDisableInterrupts | |
24 | EXPORT ArmGetInterruptState | |
25 | EXPORT ArmEnableFiq | |
26 | EXPORT ArmDisableFiq | |
27 | EXPORT ArmGetFiqState | |
28 | EXPORT ArmInvalidateTlb | |
29 | EXPORT ArmSetTTBR0 | |
30 | EXPORT ArmGetTTBR0BaseAddress | |
31 | EXPORT ArmSetDomainAccessControl | |
32 | EXPORT CPSRMaskInsert | |
33 | EXPORT CPSRRead | |
34 | ||
35 | AREA ArmLibSupport, CODE, READONLY | |
36 | ||
37 | Cp15IdCode | |
38 | mrc p15,0,R0,c0,c0,0 | |
39 | bx LR | |
40 | ||
41 | Cp15CacheInfo | |
42 | mrc p15,0,R0,c0,c0,1 | |
43 | bx LR | |
44 | ||
45 | ArmIsMPCore | |
46 | mrc p15,0,R0,c0,c0,5 | |
47 | // Get Multiprocessing extension (bit31) & U bit (bit30) | |
48 | and R0, R0, #0xC0000000 | |
49 | // if bit30 == 0 then the processor is part of a multiprocessor system) | |
50 | and R0, R0, #0x80000000 | |
51 | bx LR | |
52 | ||
53 | ArmEnableInterrupts | |
54 | mrs R0,CPSR | |
55 | bic R0,R0,#0x80 ;Enable IRQ interrupts | |
56 | msr CPSR_c,R0 | |
57 | bx LR | |
58 | ||
59 | ArmDisableInterrupts | |
60 | mrs R0,CPSR | |
61 | orr R1,R0,#0x80 ;Disable IRQ interrupts | |
62 | msr CPSR_c,R1 | |
63 | tst R0,#0x80 | |
64 | moveq R0,#1 | |
65 | movne R0,#0 | |
66 | bx LR | |
67 | ||
68 | ArmGetInterruptState | |
69 | mrs R0,CPSR | |
70 | tst R0,#0x80 ;Check if IRQ is enabled. | |
71 | moveq R0,#1 | |
72 | movne R0,#0 | |
73 | bx LR | |
74 | ||
75 | ArmEnableFiq | |
76 | mrs R0,CPSR | |
77 | bic R0,R0,#0x40 ;Enable IRQ interrupts | |
78 | msr CPSR_c,R0 | |
79 | bx LR | |
80 | ||
81 | ArmDisableFiq | |
82 | mrs R0,CPSR | |
83 | orr R1,R0,#0x40 ;Disable IRQ interrupts | |
84 | msr CPSR_c,R1 | |
85 | tst R0,#0x40 | |
86 | moveq R0,#1 | |
87 | movne R0,#0 | |
88 | bx LR | |
89 | ||
90 | ArmGetFiqState | |
91 | mrs R0,CPSR | |
92 | tst R0,#0x40 ;Check if IRQ is enabled. | |
93 | moveq R0,#1 | |
94 | movne R0,#0 | |
95 | bx LR | |
96 | ||
97 | ArmInvalidateTlb | |
98 | mov r0,#0 | |
99 | mcr p15,0,r0,c8,c7,0 | |
100 | bx lr | |
101 | ||
102 | ArmSetTTBR0 | |
103 | mcr p15,0,r0,c2,c0,0 | |
104 | bx lr | |
105 | ||
106 | ArmGetTTBR0BaseAddress | |
107 | mrc p15,0,r0,c2,c0,0 | |
108 | LoadConstantToReg(0xFFFFC000,r1) // and r0, r0, #0xFFFFC000 | |
109 | and r0, r0, r1 | |
110 | bx lr | |
111 | ||
112 | ArmSetDomainAccessControl | |
113 | mcr p15,0,r0,c3,c0,0 | |
114 | bx lr | |
115 | ||
116 | CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert | |
117 | stmfd sp!, {r4-r12, lr} ; save all the banked registers | |
118 | mov r3, sp ; copy the stack pointer into a non-banked register | |
119 | mrs r2, cpsr ; read the cpsr | |
120 | bic r2, r2, r0 ; clear mask in the cpsr | |
121 | and r1, r1, r0 ; clear bits outside the mask in the input | |
122 | orr r2, r2, r1 ; set field | |
123 | msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch) | |
124 | mov sp, r3 ; restore stack pointer | |
125 | ldmfd sp!, {r4-r12, lr} ; restore registers | |
126 | bx lr ; return (hopefully thumb-safe!) | |
127 | ||
128 | CPSRRead | |
129 | mrs r0, cpsr | |
130 | bx lr | |
131 | ||
132 | END | |
133 | ||
134 |